JPS6317191B2 - - Google Patents
Info
- Publication number
- JPS6317191B2 JPS6317191B2 JP55023142A JP2314280A JPS6317191B2 JP S6317191 B2 JPS6317191 B2 JP S6317191B2 JP 55023142 A JP55023142 A JP 55023142A JP 2314280 A JP2314280 A JP 2314280A JP S6317191 B2 JPS6317191 B2 JP S6317191B2
- Authority
- JP
- Japan
- Prior art keywords
- test
- board unit
- printed board
- random number
- printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012360 testing method Methods 0.000 claims description 54
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 14
- 238000010998 test method Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000007689 inspection Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000035939 shock Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2818—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Description
【発明の詳細な説明】
本発明は電子機器の装置試験に於けるプリント
板ユニツトの初期不良の排除を行うためのプリン
ト板ユニツトのバーンイン試験方式に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a burn-in test method for printed board units for eliminating initial defects in printed board units during device testing of electronic equipment.
近年電子機器においては機能が高度化し、規模
が大形化するに伴い当該機器の信頼度の向上が必
要となつてきている。 BACKGROUND ART In recent years, as electronic devices have become more sophisticated and larger in scale, it has become necessary to improve the reliability of the devices.
可動する機構部を具備することのない電子機器
の信頼度は、当該機器に装着されるプリント板ユ
ニツト、すなわちプリント基板に電子部品を搭載
して構成した電子回路の信頼度によつて主として
決定される。 The reliability of electronic devices that do not have moving mechanical parts is determined primarily by the reliability of the printed circuit board unit installed in the device, that is, the electronic circuit made up of electronic components mounted on a printed circuit board. Ru.
プリント板ユニツトの該プリント基板は殆どの
場合、画面以上のパターン数を相互にスルーホー
ル鍍金をすることにより接続して構成され、該プ
リント基板に搭載する電子部品の主体は、IC、
LSI等の半導体部品である。従つて電子機器の信
頼度を高めるためのプリント板ユニツトの信頼度
は、プリント基板及び該基板に搭載する半導体素
子等の品質によつて左右されることになる。 In most cases, the printed circuit board of a printed circuit board unit is constructed by connecting a number of patterns larger than the screen to each other by through-hole plating, and the main electronic components mounted on the printed circuit board are ICs,
Semiconductor parts such as LSI. Therefore, the reliability of a printed board unit for increasing the reliability of electronic equipment depends on the quality of the printed board and the semiconductor elements mounted on the board.
多層数のパターンで構成されるプリント基板は
パターン間を接続するためにパターン間を貫通す
る透孔をうがち、該内孔を50μm厚程度の銅鍍金
を施すことにより行われるが、通常パターンをな
している銅箔厚は50μm以下の厚さを有し、パタ
ーンと該内孔の銅鍍金との接続は、当該銅箔の層
が該孔内に露呈する部分に行われ、当該２つの金
属の接続部は、無電解鍍金及び電気鍍金によるク
リテイカルな手法によつて得られるために一般的
に品質の分散度は高く該基板と該電子部品とを半
田付するときの加熱及び装置の稼動時の発熱等に
よる熱衝撃によつて、不充分な接続のスルーホー
ル鍍金部が剥離し断線事故の発生となる。 Printed circuit boards consisting of multiple layers of patterns have through-holes that pass through the patterns to connect them, and the inner holes are plated with copper to a thickness of about 50 μm, but usually there are no patterns. The thickness of the copper foil is 50 μm or less, and the connection between the pattern and the copper plating of the inner hole is made in the part where the copper foil layer is exposed in the hole, and the connection between the two metals is made. Since the connection parts are obtained by critical methods such as electroless plating and electroplating, the quality generally has a high degree of dispersion, and there is a high degree of dispersion in quality during heating when soldering the board and the electronic component and during operation of the equipment. Due to thermal shock caused by heat generation, the plated portion of the through hole with insufficient connection may peel off, resulting in a disconnection accident.
半導体素子も亦同様に拡散し、エツチングされ
たシリコンの薄膜層間の接合、及び金属蒸着薄膜
層をワイヤリング接続等の微少面接続のため接合
力が微弱であり熱衝撃や機械的衝撃の対抗性は少
ない。 Semiconductor elements are also diffused in the same way, and the bonding force is weak due to the bonding between etched silicon thin film layers and microscopic surface connections such as wiring connections between metal evaporated thin film layers, and the resistance to thermal shock and mechanical shock is weak. few.
該プリント基板及び半導体素子は製造工程でチ
エツクされ検査及び試験が行われるが、検査及び
試験の雰囲気は常温で印加電圧は規定値の範囲で
あり、基本的には短時間テストの品質の保証を行
つている。斯る事から、プリント板ユニツトとし
て組み立てられた品質の保証は、検査及び試験の
保証品質レベルを充分高く執り、且つ綿密な検査
及び試験システムにより検査及び試験の洩れと誤
判定を防止し、必要に応じマージナルテストを行
うことによつてなされる。 The printed circuit boards and semiconductor devices are checked, inspected and tested during the manufacturing process, but the atmosphere for the inspections and tests is room temperature and the applied voltage is within the specified value range, so basically the quality of the short-time test is guaranteed. I'm going. Therefore, in order to guarantee the quality of the assembled printed circuit board unit, we must ensure that the quality level of inspection and testing is sufficiently high, and that we use a thorough inspection and testing system to prevent omissions and misjudgments in inspections and tests, and to ensure that the quality of printed board units is as high as possible. This is done by conducting a marginal test depending on the situation.
品質の保証されたプリント板ユニツトは装置に
装着され製品として組立てられるが、製品が出荷
されて故障となる原因の多くは機能ごとに構成さ
れ、実装されたプリント板ユニツト内の集積回路
等の素子であり、メーカでは出荷後も安定して動
作するよう種々の環境試験が行なわれる。このよ
うな試験のひとつに装置試験に先立ち、プリント
板ユニツトを全実装した装置全体を高温雰囲気中
に設置し、連続して長時間実稼動せしめ、この時
必要に応じ、印加電圧を高圧にして過電圧、稼動
を行い、装置のランニングテストにより該装置の
初期不良の発生を短時間内に強制して発生させ、
ユーザーでの実動時の信頼度の保持を計る試験が
ある。このような試験がいわゆるバーンイン試験
といわれるものであり、初期不良の検出に最も有
効な試験とされている。 Printed board units with guaranteed quality are installed in equipment and assembled as products, but many of the causes of product failures after shipment are due to components such as integrated circuits in the printed board units that are organized by function. Manufacturers conduct various environmental tests to ensure stable operation even after shipment. In one such test, prior to the device test, the entire device with all printed circuit board units mounted is placed in a high-temperature atmosphere and operated continuously for a long period of time, at which time the applied voltage may be increased as necessary. Overvoltage, operation, and running test of the device to force the initial failure of the device to occur within a short time,
There is a test to measure the reliability maintained during production by users. This type of test is called a burn-in test, and is considered the most effective test for detecting initial defects.
従来このような試験は各プリント板ユニツトを
装置としての機能をもつように実装し、実動作さ
せて行つているが、この試験方式では、装置実装
後の長時間の試験は納期短縮には逆効果である。 Conventionally, such tests have been carried out by mounting each printed board unit to function as a device and operating it in actual operation, but with this testing method, long tests after the device has been mounted are detrimental to shortening delivery times. It is an effect.
また通常、装置に於いて構成するプリント板ユ
ニツトの実装がなされないときは、プリント板ユ
ニツト相互の信号の授受が行われず、充分なラン
ニング効果が得られず、全てのプリント板ユニツ
トの実装を得てランニングテストを再び続行す
る。 Also, normally, when the printed board units that make up the equipment are not mounted, signals are not exchanged between the printed board units, and a sufficient running effect cannot be obtained, making it impossible to mount all the printed board units. and continue the running test again.
従つて、欠品せるプリント板ユニツトが補充さ
れる間、ランニングテストは中断され、試験期間
が延長され試験処理管理、納期管理上支障が生ず
るなどの欠点を有している。本発明はこれらの欠
点を解消することを目的とするもので、この目的
のため本発明は、高温雰囲気中に被試験プリント
板ユニツトを設け、過電圧を加えた状態で該被試
験プリント板ユニツトに入力信号を加え、試験を
行なうプリント板ユニツトの試験方式において、
前記被試験プリント板ユニツトに乱数信号発生回
路を具備し、該乱数信号発生回路の出力は被試験
プリント板ユニツトの入力端子に接続され、か
つ、該乱数信号発生回路は被試験プリント板ユニ
ツトの試験端子からの試験信号で起動されるよう
にし、乱数信号発生回路の出力により被試験プリ
ント板ユニツトのバーンイン試験を行うことを特
徴としているものである。斯の如き手法によれ
ば、実装される信号を受信するそれぞれのプリン
ト板ユニツトは他のプリント板ユニツトよりの信
号の授受を行う必要がない為にたとえ、プリント
板ユニツトに欠品するものが生じた場合でもラン
ニングテストを中断することはなく規定時間の続
行が可能であり、試験作業の工程管理はより容易
に行い得る。 Therefore, the running test is interrupted while the missing printed board units are replenished, and the test period is extended, causing problems in test processing management and delivery date management. The present invention aims to eliminate these drawbacks, and for this purpose, the present invention provides a printed circuit board unit under test in a high temperature atmosphere, and applies an overvoltage to the printed circuit board unit under test. In the test method for printed circuit board units that applies input signals and performs tests,
The printed board unit under test is equipped with a random number signal generation circuit, the output of the random number signal generation circuit is connected to the input terminal of the printed board unit under test, and the random number signal generation circuit is configured to perform a test of the printed board unit under test. It is characterized in that it is activated by a test signal from a terminal and performs a burn-in test of the printed board unit under test using the output of a random number signal generation circuit. According to such a method, each printed board unit that receives signals to be mounted does not need to send and receive signals from other printed board units, so it is possible for some printed board units to be out of stock. Even if a running test occurs, it is possible to continue the running test for the specified time without interrupting it, and process control of the test work can be performed more easily.
以下本発明を実施例によつて説明する。 The present invention will be explained below with reference to Examples.
図は本発明のプリント板ユニツト試験方式の一
実施例を示す図であり、プリント基板１には通常
の論理回路、記憶回路等の機能を果す回路部分２
が形成されており、この回路部分２には入力端子
５、出力端子７、電源端子４が設けられている。
３は本発明により設けられた乱数信号発生回路で
あり、乱数信号発生回路３の出力６は回路部分２
の入力端子５に接続されており、電源端子は回路
部分２と共用にされている。８は試験端子であ
り、この試験端子８からの試験信号により、乱数
信号発生回路３が起動され、乱数信号が発生され
る。この乱数信号が入力端子５を介して回路部分
２に与えられ所定の試験が行われる。 The figure shows an embodiment of the printed board unit testing method of the present invention.
is formed, and this circuit portion 2 is provided with an input terminal 5, an output terminal 7, and a power supply terminal 4.
3 is a random number signal generation circuit provided according to the present invention, and the output 6 of the random number signal generation circuit 3 is connected to the circuit portion 2.
The power supply terminal is shared with the circuit section 2. 8 is a test terminal, and a test signal from this test terminal 8 activates the random number signal generation circuit 3 to generate a random number signal. This random number signal is applied to the circuit section 2 via the input terminal 5 and a predetermined test is performed.
このようにプリント板ユニツトに乱数信号発生
回路３を具備し、試験信号からの試験信号で該乱
数信号発生回路３を起動し、この乱数信号で回路
部分２の試験が行え、装置を構成するプリント板
ユニツト全てが実装されていない状態であつても
各プリント板ユニツトの機能を動作させ、試験が
できるものである。 In this way, the printed circuit board unit is equipped with the random number signal generating circuit 3, the random number signal generating circuit 3 is activated by the test signal from the test signal, and the circuit portion 2 can be tested using this random number signal. Even if all the board units are not mounted, the functions of each printed board unit can be operated and tested.
従つてプリント板ユニツト単位でランダムにシ
エルフに組込み高温を加え、電圧を高圧としてバ
ーンイン試験を行うことができ前述の欠点は解消
されることとなる。 Therefore, the burn-in test can be carried out by randomly assembling the printed board unit into the shelf, applying high temperature, and increasing the voltage, thereby eliminating the above-mentioned drawbacks.
なお本実施例においてはプリント板ユニツト上
に乱数信号発生回路３を形成した例を示してある
が、必らずしもこれに限定されることなく乱数信
号発生回路を別に構成し、各端子に所定の端子を
接続できるプラグイン構成としておくことも可能
である。 Although this embodiment shows an example in which the random number signal generation circuit 3 is formed on the printed board unit, the present invention is not limited to this, and the random number signal generation circuit may be configured separately and connected to each terminal. It is also possible to have a plug-in configuration to which predetermined terminals can be connected.
内部部分２の動作周波数が高低いずれの場合に
おいても、乱数信号発生回路３からの乱数信号を
可変することにより、あらゆる内部部分２の試験
が行える。 Regardless of whether the operating frequency of the internal section 2 is high or low, any test of the internal section 2 can be performed by varying the random number signal from the random number signal generation circuit 3.
図は本発明の一実施例を示す図であり、１はプ
リント基板、２は回路部分、３は乱数信号発生回
路、４は電源端子、８は試験端子である。
The figure shows an embodiment of the present invention, in which 1 is a printed circuit board, 2 is a circuit section, 3 is a random number signal generation circuit, 4 is a power supply terminal, and 8 is a test terminal.
Claims (1)
設け、過電圧を加えた状態で該被試験プリント板
ユニツトに入力信号を加え、試験を行なうプリン
ト板ユニツトの試験方式において、前記被試験プ
リント板ユニツトに乱数信号発生回路を具備し、
該乱数信号発生回路の出力は被試験プリント板ユ
ニツトの入力端子に接続され、かつ、該乱数信号
発生回路は被試験プリント板ユニツトの試験端子
からの試験信号で起動されるようにし、乱数信号
発生回路の出力により被試験プリント板ユニツト
のバーンイン試験を行なうことを特徴とするプリ
ント板ユニツトの試験方法。1 In a test method for a printed board unit in which a printed board unit under test is placed in a high temperature atmosphere and an input signal is applied to the printed board unit under test while an overvoltage is applied, a random number is applied to the printed board unit under test. Equipped with a signal generation circuit,
The output of the random number signal generation circuit is connected to the input terminal of the printed circuit board unit under test, and the random number signal generation circuit is activated by a test signal from the test terminal of the printed circuit board unit under test. A test method for a printed board unit characterized by performing a burn-in test on the printed board unit under test using the output of a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2314280A JPS56119863A (en) | 1980-02-26 | 1980-02-26 | Testing method for printed board unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2314280A JPS56119863A (en) | 1980-02-26 | 1980-02-26 | Testing method for printed board unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56119863A JPS56119863A (en) | 1981-09-19 |
| JPS6317191B2 true JPS6317191B2 (en) | 1988-04-12 |
Family
ID=12102304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2314280A Granted JPS56119863A (en) | 1980-02-26 | 1980-02-26 | Testing method for printed board unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56119863A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5348678A (en) * | 1976-10-15 | 1978-05-02 | Toshiba Corp | Integrated circuit package |
-
1980
- 1980-02-26 JP JP2314280A patent/JPS56119863A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5348678A (en) * | 1976-10-15 | 1978-05-02 | Toshiba Corp | Integrated circuit package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56119863A (en) | 1981-09-19 |
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