JPS63171845U - - Google Patents
Info
- Publication number
- JPS63171845U JPS63171845U JP6565487U JP6565487U JPS63171845U JP S63171845 U JPS63171845 U JP S63171845U JP 6565487 U JP6565487 U JP 6565487U JP 6565487 U JP6565487 U JP 6565487U JP S63171845 U JPS63171845 U JP S63171845U
- Authority
- JP
- Japan
- Prior art keywords
- address
- bit address
- storage device
- selector
- specifies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例の記憶装置の回路図
、第２図は従来例の記憶装置の回路図である。
１……ＤＲＡＭ、２……セレクタ。
FIG. 1 is a circuit diagram of a storage device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional storage device. 1...DRAM, 2...Selector.
Claims (1)
アドレスを奇数ビツトアドレスと偶数ビツトアド
レスとに分割して指定するセレクタを具備したこ
とを特徴とする記憶装置。 1. A storage device comprising a selector that divides and specifies an address of a dynamic random access memory into an odd bit address and an even bit address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6565487U JPS63171845U (en) | 1987-04-28 | 1987-04-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6565487U JPS63171845U (en) | 1987-04-28 | 1987-04-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63171845U true JPS63171845U (en) | 1988-11-08 |
Family
ID=30902929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6565487U Pending JPS63171845U (en) | 1987-04-28 | 1987-04-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63171845U (en) |
-
1987
- 1987-04-28 JP JP6565487U patent/JPS63171845U/ja active Pending
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