JPS63169378A - Sputtering method - Google Patents

Sputtering method

Info

Publication number
JPS63169378A
JPS63169378A JP62000363A JP36387A JPS63169378A JP S63169378 A JPS63169378 A JP S63169378A JP 62000363 A JP62000363 A JP 62000363A JP 36387 A JP36387 A JP 36387A JP S63169378 A JPS63169378 A JP S63169378A
Authority
JP
Japan
Prior art keywords
substrate
bias voltage
sputtering
film
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62000363A
Other languages
Japanese (ja)
Other versions
JPH0791639B2 (en
Inventor
Hideki Tateishi
秀樹 立石
Yutaka Saito
裕 斉藤
Shinji Sasaki
新治 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62000363A priority Critical patent/JPH0791639B2/en
Priority to US07/137,562 priority patent/US4853102A/en
Priority to KR1019870015286A priority patent/KR910001879B1/en
Priority to EP88100054A priority patent/EP0275021B1/en
Priority to DE3854276T priority patent/DE3854276T2/en
Publication of JPS63169378A publication Critical patent/JPS63169378A/en
Publication of JPH0791639B2 publication Critical patent/JPH0791639B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To deposit a film forming material capable of infiltrating into the minute stepped parts, grooves, and holes with a low bias voltage not causing the film defect such as bulging by impressing a negative bias voltage on the surface of a substrate to be treated in the title sputtering device. CONSTITUTION:The substrate 25 such as a semiconductor device and the target 5 on the film forming material are provided in a vacuum vessel 1 in opposition to each other, and gaseous Ar is introduced from a gas inlet 19. A target coil 6 and a substrate coil 14 are energized to generate magnetic fields in the directions opposite to each other, and a cusped magnetic field formed by the lines of magnetic force 26 is generated. A sputtering voltage is further impressed on a sputtering electrode 4 to generate high-density plasma 27 of the same shape as the lines of magnetic fore 26. A DC bias is impressed on the surface of the substrate 25 by a DC power source 22 or a high-frequency power is impressed on a substrate electrode 10 by a high-frequency power source 21 to induce a bias voltage on the surface of the substrate 25. Consequently, the surface of the substrate 25 is kept at a negative bias potential, high-density plasma is produced in the vicinity of the substrate by the cusped magnetic field, and a film infiltrating into the small stepped parts, grooves, and holes of the substrate surface is formed with a low bias voltage not causing film defects.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は薄膜のスパッタ成膜技術に係り、特に半導体装
置等の基板表面の微細な段差、溝あをいは穴に、成膜材
料をつき回わり良く付着させるスパッタ方法に関するも
のである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to thin film sputter deposition technology, and in particular to the application of a deposition material to fine steps, grooves, and holes on the surface of a substrate such as a semiconductor device. This relates to a sputtering method that provides relatively good adhesion.

〔従来の技術〕[Conventional technology]

スパッタリング成膜技術において、プラズマに印加する
磁界を強くして、成膜対象へ流入する1流を増加させる
試みは、例えば特開昭60−221565号に記載され
ている。即ち、マグネトロン製スパクタ電極と、基板と
を対向させ、基板表面に負のバイアス電圧を印加するこ
とにより、マグネトロン型スパッタ電極上に発生するプ
ラズマ中のイオンの一部を、基板式面に流入させる、一
種のバイアススパッタ装置症となっている。
In the sputtering film forming technique, an attempt to increase the amount of flow flowing into the film to be formed by increasing the magnetic field applied to the plasma is described in, for example, Japanese Patent Laid-Open No. 60-221565. That is, by placing a magnetron sputter electrode and a substrate facing each other and applying a negative bias voltage to the substrate surface, some of the ions in the plasma generated on the magnetron sputter electrode flow into the substrate surface. , it has become a kind of bias sputtering device disease.

一方、米国特許U8P3.325.594号にカスプ磁
界を用いたスパッタリング成膜技術が記載されている。
On the other hand, US Patent U8P3.325.594 describes a sputtering film forming technique using a cusp magnetic field.

即ち、スパ2り′1極と成膜対象基板とを対向装置し、
2組の電磁石により、その間にカスプ磁界を形成してプ
ラズマ1aWEを向上させ、成膜速度の向上を計るもの
である。成膜速度向上のためKは上記カスプ磁界の補助
によったスパッタリング成膜法よりは、その後に公知と
なったマグネトロンスバクタ成腿法の万が装置構成が簡
単で効果が大きいため、カスプ磁界を用いることは顧み
られなかった。
That is, the spa 2'1 pole and the substrate to be film-formed are placed facing each other,
Two sets of electromagnets are used to form a cusp magnetic field between them to improve the plasma 1aWE and improve the film forming rate. In order to increase the film formation speed, K is a method using a cusp magnetic field, which is more effective than the sputtering film formation method using the cusp magnetic field, since the device configuration is simpler and the effect is greater than the sputtering film formation method that is assisted by the cusp magnetic field. The use of was not considered.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

バイアススパッタ法とは基板に成膜材料を堆積しながら
、同時に基板表面に負のバイアス電圧を印加し、プラズ
マ中のイオンを入射させ、イオンのエネルギを成j屓粒
子に与え成績粒子の表面移動度を高めることにより、等
、穴へのつき回り性を向上させるものである。したがっ
て基板に入射するイオン量を向上させることが重要であ
り、この手段としては、基板上のプラズマ密度を向上さ
せ基板に流入するイオン電流を向上させること、あるい
はバイアス電圧を向上させることが考えられる。
Bias sputtering is a process in which a film material is deposited on a substrate, and at the same time a negative bias voltage is applied to the substrate surface, ions in the plasma are incident, and the energy of the ions is imparted to the forming particles, causing the particles to move on the surface. By increasing the strength, it is possible to improve the ability to go around holes. Therefore, it is important to increase the amount of ions that enter the substrate, and possible ways to do this include increasing the plasma density on the substrate and increasing the ion current flowing into the substrate, or increasing the bias voltage. .

従来のマグネトロンスパッタ電極はプラズマを基板に向
かいあったスパッタ′に極聚面忙閉じ込めるものである
ため、単に基板表面にバイアス電圧を印加しただけでは
基板上のプラズマ密度は十分には向上しない。我々の予
備実験では、バイアス電圧−1oovの時、基板上のプ
ラズマ密度は2x、Dtam−1程度であり、このn基
板に流入するイオン電流はα5 A/φ125程闇で、
またtOμ肩角の深さtOμ−の穴への成膜材料(An
)のつき回りは十分ではなかった。
Since conventional magnetron sputtering electrodes confine plasma to the sputter facing the substrate, simply applying a bias voltage to the substrate surface does not sufficiently increase the plasma density on the substrate. In our preliminary experiment, when the bias voltage is -1oov, the plasma density on the substrate is about 2x, Dtam-1, and the ion current flowing into this n-substrate is about α5 A/φ125,
In addition, the film-forming material (An
) was not sufficiently frequent.

一方、バイアス電圧を高くするとスパッタ膜に吸蔵され
るArガス量が増えることが知られている。
On the other hand, it is known that increasing the bias voltage increases the amount of Ar gas occluded in the sputtered film.

我々の予備実験から、スパッタ後アニールすることKよ
り、高いバイアス′或圧で成膜したスパッタ膜にボイド
、膨れが発生すること、この発生下限は140V、[度
であることが判った。
From our preliminary experiments, we have found that post-sputter annealing causes voids and blisters to occur in sputtered films formed at a high bias pressure, and that the lower limit for this occurrence is 140 V, [degrees].

本発明の目的はボイド、膨れなどの膜不良を生じない低
バイアス電圧で、微細な段差、溝あるいは大忙成膜材料
をつき回りよく付着させるために、基板に流入するイオ
ン電流を向上させるスパッタ方法を提供することにある
The purpose of the present invention is to provide a sputtering method that improves the ion current flowing into a substrate in order to uniformly adhere fine steps, grooves, or large-scale deposition materials with a low bias voltage that does not cause film defects such as voids and blisters. Our goal is to provide the following.

またバイアス電圧を制(至)することにより、基板に流
入するイオン量をほぼ一定に保ったまま、基板に入射す
るイオンエネルギを制御できるスパッタ方法を提供する
ことにある。
Another object of the present invention is to provide a sputtering method that can control the energy of ions entering the substrate while keeping the amount of ions flowing into the substrate substantially constant by controlling the bias voltage.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、カグス磁界を用いたプラズマの高密度化と
、基板側電極にバイアスを印加するバイアススパッタを
結びつけて達成される。
The above object is achieved by combining plasma densification using a Kags magnetic field and bias sputtering that applies a bias to the substrate side electrode.

〔作用〕[Effect]

スパッタ電極と基板電極とを対向して配置し。 A sputter electrode and a substrate electrode are placed facing each other.

その間にカスプ磁界を形成することにより、高密度プラ
ズマがスパッタ電極表面から基板表面近傍まで発生する
。さらに基板表面に負のバイアス電圧を印加することK
より、基板表面近傍のプラズマ中の高密度イオンが膜不
良を生じない低バイアス電圧で基板にひきこまれ、基板
流入イオン電流が向上する。この結果、基板表mK付着
したスパッタ粒子の、基板表面での移動度が向上し、 
Iiしくは、基板表面の段差上部角、#1、穴入口の角
に付着した膜材料がスパッタされ、段差下部、溝。
By forming a cusp magnetic field in between, high-density plasma is generated from the surface of the sputtering electrode to near the surface of the substrate. Furthermore, applying a negative bias voltage to the substrate surface K
Therefore, high-density ions in the plasma near the substrate surface are drawn into the substrate at a low bias voltage that does not cause film defects, and the ion current flowing into the substrate is improved. As a result, the mobility of the sputtered particles adhering to the substrate surface is improved,
Specifically, the film material adhering to the upper corner of the step #1 on the substrate surface and the corner of the hole entrance is sputtered to form the lower step and the groove.

穴底面へ褥付着する。このため膜不良を生じることなく
段差、噂、穴へのスパッタ材料のつき回りを向上させる
ことができる。
Bed adheres to the bottom of the hole. Therefore, it is possible to improve the distribution of sputtered material to steps, gaps, and holes without causing film defects.

また高密度プラズマの発生とは独立にバイアス電圧を設
定できるので、基板に流入するイオン電流をはぼ一定に
保ったまま、基板に入射するイオンエネルギを制御でき
る。
Furthermore, since the bias voltage can be set independently of the generation of high-density plasma, the ion energy incident on the substrate can be controlled while the ion current flowing into the substrate is kept approximately constant.

〔実施例〕〔Example〕

以下本発明の一実施例を第1図により説明する。 An embodiment of the present invention will be described below with reference to FIG.

初めに本実施例の構成を述べる。First, the configuration of this embodiment will be described.

真空容器1の上部の開口2K、絶縁物3を介してスパッ
タ電極4が取付けられている。該スパッタ電極4の真空
室側にはスパクタ成映材料より成るタルゲット5.大気
Illは磁界発生用のターゲットコイル6およびヨ〜り
7が、さらに該夕〜ゲクト5の外周には該ターゲットと
の間に放電を生じない距離だけターゲットより噛てて、
絶縁体8を介して真空容器1に7ノード28が取付けら
れている。
A sputter electrode 4 is attached to an opening 2K at the top of the vacuum container 1 via an insulator 3. On the vacuum chamber side of the sputter electrode 4 is a target 5 made of sputtering material. The atmosphere Ill has a target coil 6 and a yaw 7 for generating a magnetic field, and furthermore, on the outer periphery of the target 5, there is a distance between the target and the target so as not to cause an electric discharge.
Seven nodes 28 are attached to the vacuum vessel 1 via insulators 8.

ヨーク7はターゲットコイル6により発生する漏えい磁
束密度を強めるために用いられている。
The yoke 7 is used to strengthen the leakage magnetic flux density generated by the target coil 6.

アノード28の電位は必要に応じて、フローティング、
アースあるいは任意の正、負の電位となるよう配線され
ている。
The potential of the anode 28 can be set to floating,
Wired to earth or any positive or negative potential.

該真空容器1の下部の開口9には基板25を載置する基
板電極10があり、基板電極10の周囲には真空シール
機能を持つ絶縁体11を介して、ターゲット5と基板電
極100表面に垂直な方向に移動可能な基板押え12が
、さらに基板押え12の周囲には真空シール機能を持つ
絶縁体13を介してシールド14か、真空容器1に対し
て固定で取付けられている。
There is a substrate electrode 10 on which a substrate 25 is placed in the opening 9 at the bottom of the vacuum container 1. Around the substrate electrode 10, an insulator 11 having a vacuum sealing function is placed between the target 5 and the surface of the substrate electrode 100. A vertically movable substrate holder 12 is further fixedly attached to a shield 14 or to the vacuum container 1 via an insulator 13 having a vacuum sealing function around the substrate holder 12.

また真空容器1の下部の他の開口15には、真9!谷器
1に対して真空シールされた状態に取付けられたコイル
容器16の中に基板コイル17が取付けられている。
Further, the other opening 15 at the bottom of the vacuum container 1 has a true 9! A substrate coil 17 is installed in a coil container 16 that is attached to the valley device 1 in a vacuum-sealed state.

真空容器1内は排気手段18により真空排気されるとと
もにガス導入手段19によりガスが導入されて、王とし
て10Torr台の圧力に保たれる。
The inside of the vacuum container 1 is evacuated by the exhaust means 18, and gas is introduced by the gas introduction means 19, so that the pressure is maintained at approximately 10 Torr.

スパッタ電極4、基板電極IQ、基板押え12.ターゲ
ットコイル6、基板コイル17には各々スパッタ電源2
0.高周波電源21、直流を源22、ターゲットコイル
電源23.基板コイル電源24が、また真空容器1はア
ースに接続されている。
Sputter electrode 4, substrate electrode IQ, substrate holder 12. A sputter power supply 2 is connected to the target coil 6 and the substrate coil 17, respectively.
0. High frequency power source 21, DC source 22, target coil power source 23. The substrate coil power supply 24 and the vacuum vessel 1 are connected to ground.

基板表面に直流′9イアス電圧を電力Ωする場合(ま高
周波電源21が、高周波バイアス電圧を印加する場合に
は直流電源22が各々不要である。また高周波バイアス
電圧−を印加する場合には基板押え12は高周波プラズ
マのシールドのため、絶縁物で作られる。
When applying a DC'9 bias voltage to the substrate surface, the DC power supply 22 is not required (when the high frequency power supply 21 applies a high frequency bias voltage), and when applying a high frequency bias voltage -, the high frequency power supply 22 is not required. The presser foot 12 is made of an insulating material to shield high frequency plasma.

ターゲットコイル6とターゲットコイル電源23および
基板コイル17と基板コイル電源24はこれら電磁石に
限らず、これと等価な磁界を発生する永久磁石を用いて
もよい。
The target coil 6 and the target coil power supply 23 and the substrate coil 17 and the substrate coil power supply 24 are not limited to these electromagnets, but permanent magnets that generate a magnetic field equivalent to the electromagnets may be used.

スパッタ成膜処理を受ける基板25は、基板押え1肋−
ターゲット5側に、基板電極10より離間した状態で、
図示しない搬送機構により基板電極10上に載置された
後、基板押え12で保持される。
The substrate 25 to be subjected to the sputtering film forming process is placed on the substrate holder 1.
On the target 5 side, spaced apart from the substrate electrode 10,
After being placed on the substrate electrode 10 by a transport mechanism (not shown), it is held by a substrate presser 12.

以上の構成の本実施例は以下のように動作する。This embodiment with the above configuration operates as follows.

真空容器10図示しない入口より搬送された基板25は
、基板電極10上罠載置された後、基板押え12により
固定される。排気手段15により真空容器1内の高真空
排気した後、ガス導入手段19i’(よりArガスを導
入し、所定のスパッタ圧に保つ。ターゲットコイル電源
26及び基板コイル電源24により、それぞれターゲッ
トコイル6及び基板コイル14に、相互に逆向きの磁界
を発生するようにコイル電流を印加すると第1図に示す
磁力線26の形状のカスプ磁界が発生する。さらにスパ
ッタ*m20よりスパッタ電極4にスパッタ電圧を印加
すると、磁力線26と同形状の高密度プラズマ27が、
ターゲット50表面から基板25の表面近傍まで発生す
る。
A substrate 25 is conveyed from an inlet (not shown) of the vacuum container 10, placed on the substrate electrode 10, and then fixed by a substrate holder 12. After the vacuum chamber 1 is evacuated to a high vacuum by the exhaust means 15, Ar gas is introduced from the gas introduction means 19i' (to maintain a predetermined sputtering pressure). When a coil current is applied to the substrate coil 14 and the substrate coil 14 so as to generate mutually opposite magnetic fields, a cusp magnetic field having the shape of the magnetic lines of force 26 shown in FIG. When applied, a high-density plasma 27 having the same shape as the magnetic field lines 26 is generated.
It occurs from the surface of the target 50 to near the surface of the substrate 25.

直りL電TM22より基板押え12を弁じて基板250
表面に直流バイアスを印加するか、もしくは高周波電源
21より基板電極10に高周波電力を印加し基板25上
にさらに高周波プラズマを発生させ、基板25の表面に
バイアス電圧を誘起することにより、基板表面を負のバ
イアス電位に保ち、プラズマ27中のイオンを基板25
上に流入される。
Press the board holder 12 from the straight L electric TM22 and press the board 250.
By applying a DC bias to the surface or applying high frequency power from the high frequency power source 21 to the substrate electrode 10 to further generate high frequency plasma on the substrate 25 and inducing a bias voltage on the surface of the substrate 25, the substrate surface is A negative bias potential is maintained to direct ions in the plasma 27 to the substrate 25.
It flows upward.

以上のように本実施例ではカスプ磁界により高密度プラ
ズマを基板25の近房まで発生させることができるため
、膜不艮を生じない低バイアス電圧においても、段差、
溝、穴にスパッタ材料をつき回りよ(成膜するだけの十
分なイオン電流を得ることができる。
As described above, in this embodiment, high-density plasma can be generated up to the vicinity of the substrate 25 by the cusp magnetic field.
Apply the sputtered material to the grooves and holes (you can obtain enough ion current to form a film).

本実施例での流入電流の測定例を第2図に示す′。An example of measuring the inflow current in this embodiment is shown in FIG.

第2図は、基板バイアス電圧: −100V 、基板ζ
ターゲットの間14:so簡でのデータである。基板コ
イル電流/ターゲットコイル電流の比が小さい時はプラ
ズマリングの中心径は基板の径より大きい。
Figure 2 shows substrate bias voltage: -100V, substrate ζ
14: So easy data between targets. When the ratio of substrate coil current/target coil current is small, the center diameter of the plasma ring is larger than the diameter of the substrate.

この比を大きくするとプラズマリングの中心径を基板の
径と等しくできる。そして従来技術に比べ約5倍のlX
10”Cmのプラズマ密度と、約2倍の1・1人の基板
流入電流(ψ125内)が得られた。
By increasing this ratio, the center diameter of the plasma ring can be made equal to the diameter of the substrate. And about 5 times more lX than conventional technology
A plasma density of 10"Cm and a substrate inflow current (within ψ125) of about twice as much as 1.1 people were obtained.

基板流入イオン電流を変えて、バイアススパッタ法で微
細穴へAjを成膜した時のAI のつき回り法を88M
写真から判定した結果を第1表に示す(穴深さに#’J
1sm、成膜速度は1200Il/rn i n )。
The AI throwing method when depositing Aj into microholes by bias sputtering by changing the ion current flowing into the substrate is 88M.
The results determined from the photos are shown in Table 1.
1 sm, and the film formation rate was 1200 Il/rn i n ).

○印は穴側面へのAJ付着が平坦部膜厚の概ね40嘩以
上であることを示す。このようにイオン電流が1A//
φ125で1.0乎方Jrnの穴への1つき回りが十分
であることを確認できた。
The ○ mark indicates that the AJ adhesion to the side surface of the hole is approximately 40 mm or more of the film thickness at the flat part. In this way, the ionic current is 1A//
It was confirmed that φ125 is sufficient for one turn into a hole of 1.0 Jrn.

M1表 つき回り特性 また第3因に本実施例でのバイアス電圧と流入電流の関
係を示す(縦軸はに1対重位である)。第2図と同様、
基板とターゲットの間隔は5011Bである。バイアス
電圧を一100Vから一40Vまで変えても流入イオン
電流はほぼ一定である。すなわち基板に流入するイオン
電流をほぼ一定に保ったまま、基板に入射するイオンエ
ネルギー総量を幅広(制御することができる。
Table M1 shows the relationship between the bias voltage and the inflow current in this embodiment as the third factor (the vertical axis is weighted against 1). Similar to Figure 2,
The distance between the substrate and the target is 5011B. Even if the bias voltage is changed from -100V to -40V, the inflow ion current remains almost constant. That is, the total amount of ion energy incident on the substrate can be controlled over a wide range while keeping the ion current flowing into the substrate substantially constant.

〔発明の効果〕〔Effect of the invention〕

本発明によれば低バイアス電圧で高い基板流入イオンを
流を得ることができるので、ボイド、フクレなどの膜不
良を生ずることなく、段差、溝、穴につき回りよくスバ
ンタ膜を付着させることができる。また高密度プラズマ
の発生とは独立に基板バイアス電圧を設定できるので、
基板に流入するイオン量をほぼ一定に保ったまま、イオ
ンエネルギを制御することができ、膜質制御の余裕度が
向上する。
According to the present invention, it is possible to obtain a high flow of ions flowing into the substrate with a low bias voltage, so the Svantha film can be adhered to the step, groove, and hole without causing film defects such as voids and blisters. . Also, since the substrate bias voltage can be set independently of high-density plasma generation,
The ion energy can be controlled while the amount of ions flowing into the substrate is kept almost constant, improving latitude in film quality control.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の縦断面図、第2図は本発明
の実施例での基板流入電流データを示す図、第3図は本
発明の実施例でのバイアス電圧と流入電流データを示す
図である。 1・・・真空容器、2・・・開口、3・・・絶縁物、4
・・・スパッタ電極、s・・・ターゲット、6・・・タ
ーゲットコイル、7°・・ヨーク、8・・・絶縁体、9
゛・・開口、10・・・基板電極、11・・・絶縁体、
12・・・基板押え、13・・・絶縁体、14・・・シ
ールド、15・・・開口、16・・・コイル容器、17
・・・基板コイル、18・・・排気手段、19・・・ガ
ス導入手段、20・・・スパッタ電源、21・・・高周
波電源、22“・直流電源、23・・・ターゲットコイ
ル電源、24・・・基板コイル電源、25・・・基板、
26・・・磁力線、27・・・プラズマ、28・・・ア
ノード。
FIG. 1 is a longitudinal cross-sectional view of an embodiment of the present invention, FIG. 2 is a diagram showing substrate inflow current data in an embodiment of the present invention, and FIG. 3 is a diagram showing bias voltage and inflow current in an embodiment of the present invention. It is a figure showing data. 1... Vacuum container, 2... Opening, 3... Insulator, 4
...Sputter electrode, s...Target, 6...Target coil, 7°...Yoke, 8...Insulator, 9
゛...Opening, 10...Substrate electrode, 11...Insulator,
12... Substrate holder, 13... Insulator, 14... Shield, 15... Opening, 16... Coil container, 17
. . . Substrate coil, 18 . . . Exhaust means, 19 . . . Gas introduction means, 20 . ... board coil power supply, 25... board,
26...Magnetic field lines, 27...Plasma, 28...Anode.

Claims (1)

【特許請求の範囲】 1、電圧が印加されたスパッタ電極に載置された被スパ
ッタ物質を所定の間隔を隔てて対面する試料基板へスパ
ッタするスパッタリング方法において、該ターゲットと
基板間にカスプ磁界を形成することにより高密度プラズ
マを発生させるとともに、基板表面にバイアス電圧を印
加することにより、基板表面にイオンを入射させながら
、ターゲットからはじき出されたスパッタ材料を基板に
付着させて成膜することを特徴とするスパッタ方法。 2、特許請求の範囲第1項記載のスパッタ方法において
、前記基板表面に直流電圧を印加することを特徴とする
スパッタ方法。 3、特許請求の範囲第1項記載のスパッタ方法において
、前記基板を載置する基板電極に高周波電圧を印加し、
基板表面側に負の直流バイアス電圧を誘起することを特
徴とするスパッタ方法。
[Claims] 1. In a sputtering method in which a material to be sputtered placed on a sputtering electrode to which a voltage is applied is sputtered onto a sample substrate facing each other at a predetermined distance, a cusp magnetic field is applied between the target and the substrate. By forming a high-density plasma, and applying a bias voltage to the substrate surface, ions are incident on the substrate surface, and the sputtering material ejected from the target is attached to the substrate to form a film. Characteristic sputtering method. 2. The sputtering method according to claim 1, characterized in that a DC voltage is applied to the surface of the substrate. 3. In the sputtering method according to claim 1, applying a high frequency voltage to a substrate electrode on which the substrate is placed,
A sputtering method characterized by inducing a negative DC bias voltage on the surface side of a substrate.
JP62000363A 1987-01-07 1987-01-07 Spatter method Expired - Fee Related JPH0791639B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP62000363A JPH0791639B2 (en) 1987-01-07 1987-01-07 Spatter method
US07/137,562 US4853102A (en) 1987-01-07 1987-12-24 Sputtering process and an apparatus for carrying out the same
KR1019870015286A KR910001879B1 (en) 1987-01-07 1987-12-30 Method and apparatus for sputtering film formation
EP88100054A EP0275021B1 (en) 1987-01-07 1988-01-05 Sputtering process and an apparatus for carrying out the same
DE3854276T DE3854276T2 (en) 1987-01-07 1988-01-05 Cathode sputtering method and device for carrying out the same.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62000363A JPH0791639B2 (en) 1987-01-07 1987-01-07 Spatter method

Publications (2)

Publication Number Publication Date
JPS63169378A true JPS63169378A (en) 1988-07-13
JPH0791639B2 JPH0791639B2 (en) 1995-10-04

Family

ID=11471711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62000363A Expired - Fee Related JPH0791639B2 (en) 1987-01-07 1987-01-07 Spatter method

Country Status (1)

Country Link
JP (1) JPH0791639B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6287986B1 (en) 1998-06-02 2001-09-11 Fujitsu Limited Sputtering film forming method, sputtering film forming equipment, and semiconductor device manufacturing method
JP2016511798A (en) * 2013-02-21 2016-04-21 エリコン サーフェス ソリューションズ アーゲー、 トリュープバッハ DLC coating with introductory layer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61194174A (en) * 1985-02-22 1986-08-28 Hitachi Ltd Sputtering device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61194174A (en) * 1985-02-22 1986-08-28 Hitachi Ltd Sputtering device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6287986B1 (en) 1998-06-02 2001-09-11 Fujitsu Limited Sputtering film forming method, sputtering film forming equipment, and semiconductor device manufacturing method
KR100394982B1 (en) * 1998-06-02 2003-08-19 후지쯔 가부시끼가이샤 Sputtering film forming method, sputtering film forming equipment, and semiconductor device manufacturing method
JP2016511798A (en) * 2013-02-21 2016-04-21 エリコン サーフェス ソリューションズ アーゲー、 トリュープバッハ DLC coating with introductory layer

Also Published As

Publication number Publication date
JPH0791639B2 (en) 1995-10-04

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