JPS63169051A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63169051A
JPS63169051A JP65787A JP65787A JPS63169051A JP S63169051 A JPS63169051 A JP S63169051A JP 65787 A JP65787 A JP 65787A JP 65787 A JP65787 A JP 65787A JP S63169051 A JPS63169051 A JP S63169051A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
semiconductor element
epoxy resin
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP65787A
Other languages
Japanese (ja)
Inventor
Hisashi Sawaki
佐脇 久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP65787A priority Critical patent/JPS63169051A/en
Publication of JPS63169051A publication Critical patent/JPS63169051A/en
Pending legal-status Critical Current

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To increase the life of a semiconductor device by sealing a semiconductor element with first resin, covering the surface with a metal layer, and further sealing the surface of the metal layer with second resin to suppress the corrosion of the wirings on the element. CONSTITUTION:A first epoxy resin 1 so preformed as to cover a semiconductor element 4 secured to an island 7 is formed, and the surface is covered with a metal plating layer 2. In this case, the periphery of a lead 6 is so removed at the layer 2 as not to be electrically in contact with a bonding wire 5 and the leads 6. Further, the surface is covered with second epoxy resin 3 in which the surface becomes a final state. Thus, moisture transmitting time is increased to scarcely cause an aluminum wiring corrosion and to extend the life of a product.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に係シ、特にその樹脂封止部に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a resin sealing portion thereof.

〔従来の技術〕[Conventional technology]

従来、w脂封止型半導体装fMri、第3図に示す如く
、アイランド7に固着された半導体素子4の外周部を、
充填材や添加剤等を含んだエポキシ糸舖脂3によって成
形されている。半導体素子4上のランドは、ボンディン
グワイヤ5でリード6に電気的に接続されている。
Conventionally, in the w fat-sealed semiconductor device fMRI, as shown in FIG.
It is molded from epoxy thread or fat 3 containing fillers and additives. Lands on the semiconductor element 4 are electrically connected to leads 6 by bonding wires 5.

〔発明の解決しようとする問題点〕[Problem to be solved by the invention]

前述した従来のm脂封止型の半導体装置は、封止材村上
してエボ牛シ系+*8WI3を使用しているため、不貢
的eC水分を透過させる。この透過した水分は、樹脂3
中の不純物を溶出させ、半導体素子4衣囲のアルミニウ
ム配線パターンを14食させ、半導体装置の動作不良に
碑く。このため、封止用材料のエポキシ賛催に種々の冷
加剤を加えて対策を竹なっているが、水分の透過を小さ
くすることria(釆ず、半導体素子1のアル、−ニウ
ム配#jlが腐食される事故がたびたび匙こっている。
The conventional mold-sealed semiconductor device described above uses the sealing material Murakami Ebogyushi +*8WI3, which allows non-contributing eC moisture to pass through. This permeated moisture is transferred to the resin 3
The impurities inside are eluted and the aluminum wiring pattern surrounding the semiconductor element 4 is exposed to 14 times, resulting in malfunction of the semiconductor device. For this reason, countermeasures have been taken by adding various cooling agents to the epoxy sealing material. Accidents where JL corrodes occur frequently.

本発明の目的は、前記問題点を解決し、水分の透過i@
腿を遅くシ、半導体素子表面の配源の贋食をおさえ、製
品寿命を伸はした半導体装置を提供することにある。
The purpose of the present invention is to solve the above problems and to improve the water permeability i@
It is an object of the present invention to provide a semiconductor device which has a longer product life by slowing down the process, suppressing the forgery of the distribution of the semiconductor element surface.

〔問題点をll+決するための手段〕[Means for resolving issues]

本発明の構成は、半導体素子が懐胎で封止された半導体
装置において、前記牛麹体紫子が第1の樹脂で封止され
、この第1の樹脂の表面が金pA層で機われ、さらにこ
の金私層の表面が第2の樹脂で封止されてなることを%
徴とする。
The structure of the present invention is such that in a semiconductor device in which a semiconductor element is sealed in a sterilized manner, the bovine malt violet is sealed with a first resin, the surface of the first resin is covered with a gold pA layer, Furthermore, the surface of this gold layer is sealed with a second resin.
be a sign.

〔実施例〕〔Example〕

次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.

第1図は本発明の第1の実施例の半導体装備を示す断面
図である。同図において、本実施例は、デュアル・イン
ラインのパッケージ(DIP)型で、アイランド7に固
着した半導体素子4を核うプリフォームされたillの
エポキシ樹脂1i1を形成し、その表面を金属メヅキ層
2で〜う。この時、メ9キ層2はボンディングワイヤ5
.リード6と電気的に接触しないように、リード6の周
囲等は除去されている。さらに、この表面を最終形態と
なる第2のエポキシ樹脂3で櫟う。
FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. In the figure, this embodiment is of a dual in-line package (DIP) type, and a preformed epoxy resin 1i1 is formed around a semiconductor element 4 fixed to an island 7, and its surface is covered with a metal mesh layer. It's 2. At this time, the bonding wire 5
.. The periphery of the lead 6 is removed to prevent electrical contact with the lead 6. Furthermore, this surface is coated with a second epoxy resin 3 to form the final form.

ここで、第1のエポキシ樹脂1rt%遡常の低圧トラン
スファ法によって行った。その後、パラジウム人ペース
トをプリフォーム済エポキシ明脂に塗布、活性化処理(
10%HC1,1分)khい、無電解ニッケルメッキを
2μm乃至3μm程度形成する。しかる後、第2のエポ
キシ樹脂3を低圧トランスファ法によって成形する。二
ヴケルメッキ液は、通常の硫酸ニッケル、シリアン酸ナ
トリウム系のメッキ液で、65°C135分間浸漬した
Here, a conventional low pressure transfer method using 1rt% of the first epoxy resin was used. After that, palladium paste is applied to the preformed epoxy resin and activated (
10%HC (1 minute), electroless nickel plating is formed to a thickness of about 2 to 3 μm. Thereafter, the second epoxy resin 3 is molded by a low pressure transfer method. The NIVKEL plating solution was a normal nickel sulfate and sodium syanate based plating solution, and the samples were immersed at 65°C for 135 minutes.

第2図は本4−明の第2の実施例の住°壱体装飯を示す
断面図である。同図において、本実施例の牛専体装餉は
、薄型パッケージである。第1図と異なるB「は、牛樹
体紮子4の上面のみ、メ9キ層を施している点である。
FIG. 2 is a sectional view showing the housing equipment of the second embodiment of the present invention. In the same figure, the beef exclusive packaging according to this embodiment is a thin package. The difference from Fig. 1 is that only the upper surface of the cylindrical ligament 4 is coated with a metal layer.

半導体素子4の下1fDは、アイランド7にて保hδれ
−〔いることもあって、DIPと#に#丘1bJ様な効
呆力坏すられだ。
The lower 1fD of the semiconductor element 4 is held by the island 7, so that the DIP and # have a similar effect to the #hill 1bJ.

従来の叫脂ルj止型のDIP型半導体装崗を、85”0
.85q6RHの雰Wz中で保W−すると、200H乃
至300Hで飽オロするが、本発明に従−) fc勤向
形DIP型のものを同条件で保管すると、700H乃至
800Hと約3倍に伸ひる。同様のことは、PCT(プ
レッシャー・クツカー・テスト)でも確認されている。
The conventional DIP type semiconductor mounting plate with 85”0
.. When stored in an atmosphere Wz of 85q6RH, it becomes saturated at 200H to 300H, but according to the present invention, when an fc working type DIP type is stored under the same conditions, it increases by about 3 times from 700H to 800H. Hiru. The same thing has been confirmed in the PCT (Pressure Kutzker Test).

その結果、種々の耐湿性試験において、本弁明によれば
、水分の透過時間が長くなり、アルハニウム配線腐食が
起きにくくなり、製品寿命も3倍に伸びた。
As a result, in various moisture resistance tests, according to the present invention, moisture permeation time became longer, corrosion of aluminum wiring became less likely to occur, and product life was extended three times.

また第2の実&例の薄型パッケージの場合は、側面方向
からの水分の浸入は、はぼ無視出来るため、上面のみで
有効であると考えられる。
Furthermore, in the case of the thin package of the second embodiment and example, the infiltration of moisture from the side direction can be almost ignored, so it is considered that it is effective only on the top surface.

なお、本実施例では、ニッケルメッキを例に述べたが、
他の金属のメッキでも効果がある。
In addition, in this example, nickel plating was described as an example, but
It is also effective for plating other metals.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、本発明は、エポキシ樹脂の中間部分
に、金Jll1層を形成することで、閣脂封止型半導体
装置内部への水分透過率が低減する効果がある。
As explained above, the present invention has the effect of reducing the moisture permeability into the interior of the epoxy resin-sealed semiconductor device by forming the gold layer in the middle portion of the epoxy resin.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例の牛傅体装置を示す断面
図、第2図は不発明の第2の実施例の半導体装置を示す
断面図、第3図は従来の半導体装置を示す断面図である
。 1.3・・・・・・エポキシ系m脂、2・・・・・・金
属メッキ層、4・・・・・・半導体素子(ペレット)、
5・・・・・・ボンディングワイヤ、6・・・・・・リ
ード、7・・・・・・アイランド。
FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing a semiconductor device according to a second embodiment of the invention, and FIG. 3 is a conventional semiconductor device. FIG. 1.3...Epoxy resin, 2...Metal plating layer, 4...Semiconductor element (pellet),
5...Bonding wire, 6...Lead, 7...Island.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体素子が樹脂で封止された半導体装置におい
て、前記半導体素子が第1の樹脂で封止され、この第1
の樹脂の表面が金属層で覆われ、さらに前記金属層の表
面が第2の樹脂で封止されてなることを特徴とする半導
体装置。
(1) In a semiconductor device in which a semiconductor element is sealed with a resin, the semiconductor element is sealed with a first resin, and the semiconductor element is sealed with a first resin.
A semiconductor device characterized in that a surface of the resin is covered with a metal layer, and a surface of the metal layer is further sealed with a second resin.
(2)金属層が、無電解ニッケルメッキ層である特許請
求の範囲第(1)項記載の半導体装置。
(2) The semiconductor device according to claim (1), wherein the metal layer is an electroless nickel plating layer.
JP65787A 1987-01-05 1987-01-05 Semiconductor device Pending JPS63169051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP65787A JPS63169051A (en) 1987-01-05 1987-01-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP65787A JPS63169051A (en) 1987-01-05 1987-01-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63169051A true JPS63169051A (en) 1988-07-13

Family

ID=11479794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP65787A Pending JPS63169051A (en) 1987-01-05 1987-01-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63169051A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089879A (en) * 1990-03-13 1992-02-18 Kabushiki Kaisha Toshiba Resin seal type semiconductor device
JPH04127456A (en) * 1989-09-14 1992-04-28 Toshiba Corp Resin-sealed semiconductor device and its manufacture
KR20010069478A (en) * 2001-03-27 2001-07-25 김영선 Plastic Package with Metal Sealing : PPMS

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04127456A (en) * 1989-09-14 1992-04-28 Toshiba Corp Resin-sealed semiconductor device and its manufacture
US5089879A (en) * 1990-03-13 1992-02-18 Kabushiki Kaisha Toshiba Resin seal type semiconductor device
KR20010069478A (en) * 2001-03-27 2001-07-25 김영선 Plastic Package with Metal Sealing : PPMS

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