JPS63166099A - Data rearranging circuit - Google Patents

Abstract

PURPOSE:To easily test a ROM by providing a selector, and writing ROM contents in a RAM in test mode and then reading the data out of the RAM for inspection. CONSTITUTION:The selector 5 is provided which performs switching so that input data is written in converted addresses of the RAM 4 normally, but the converted addresses themselves are written in the addresses of the RAM 4 in test mode. When the ROM 2 is tested, a test mode instruction signal, etc., are supplied to the selector 5, which inputs a converted address outputted by the ROM 2 as an address of the RAM 4 and writes the converted address itself in the address. Consequently, when reading operation is performed, the positions and contents of time slots of data read out of the RAM 4 one after another are inspected to test the ROM 2 itself. Consequently, the ROM can easily be tested without requiring any external complicate pattern generator.

Description

[Detailed Description of the Invention] [Summary] The present invention converts the write address of time-division multiplexed input data in a ROM, stores the input data in the RAM at that address, and stores the input data in the RAM according to the read address. In order to easily perform a functional test of the RAM in a data rearrangement circuit that uses input data as output data, a selector is provided so that the ROM contents can be written to the RAM in test mode, and then the data can be read out from the RAM for inspection. It is something.

[Industrial application field]

The present invention relates to a data rearrangement circuit, and in particular, a counter that generates a write address for input data, a ROM that converts the write address and rearranges the input data, and a counter that generates a read address.
The present invention relates to a data rearrangement circuit comprising a RAM that stores input data at the converted address and outputs already written data at the read address.

Data rearranging circuits are used in encoding (decoding) devices for band compression of image signals, etc., and have functions such as rearranging them to make them easier to process, and rearranging processed results to make them easier to multiplex. It is equipped with functions.

Such data rearrangement circuit requires large capacity RAM.
(Random Access Memory) is used, but it is required to easily test all bit patterns and all addresses.

[Conventional technology]

A conventionally known data reordering circuit is shown in FIG. 3, in which a write address generation counter l receives a timing pulse at the beginning of a write period and receives a timing pulse at the beginning of a write period, so that the write address generation counter l receives a timing pulse at the beginning of a write period and receives a timing pulse corresponding to data in each time slot of time-divided input data. The count is incremented by the clock signal and sent to the ROM 2 as a write address. The ROM 2 converts the input write address into a write address for data rearrangement according to a predetermined relationship stored in advance.

Since the selector 6 is now switched to the write mode by the timing pulse, the converted address of the ROM2 is input to the RAM3. Therefore, the data of each time slot of the input data is sequentially stored in the conversion address input to the RAM 3.

Next, when the selector 6 is switched to the read mode by the timing pulse, the read address generation counter 3 starts counting by the timing pulse, and increments by the clock signal for each time slot to generate a read address. The data already stored in the RAM 4 is read out sequentially and the flip-flop 7
becomes the output data via.

A time chart of such data input and output is shown in FIG.

[Problem that the invention seeks to solve]

Conventional data rearranging circuits usually use large-capacity ROM, so in order to store the program for rearranging and test whether the ROM is in a normal state, it is necessary to use a complicated pattern. There was a problem in that a generator had to be prepared.

Therefore, the object of the present invention is to provide a counter 1 that generates a write address for input data as shown in FIG. 3, a ROM 2 that converts this write address and rearranges the input data, and a counter that generates a read address. 3
and a RAM 4 that stores input data at the converted address and outputs already written data using the read address, in order to easily test the ROM 4. exist.

[Means for solving problems]

FIG. 1 shows a conceptual diagram of a data rearrangement circuit according to the present invention for achieving the above object. In the present invention, normally, input data is written to RAM 4 at a converted address, and a test mode is set. In this case, a selector 5 is provided which switches the converted address to write the address itself in the RAM 4.

[For production]

In FIG. 1, when testing the ROM2, a test mode command signal etc. is applied to the selector 5, and the selector 5
R the translated write address output by R
Input it as the address of AM4 and write the write address itself to that address. Therefore, when reading data, you can test the ROM2 itself by sequentially reading from RAM4 and checking the time slot position and contents of the output data. .

(Example) Hereinafter, an example of the data rearrangement circuit according to the present invention will be described.

FIG. 2 shows an embodiment of the data rearrangement circuit of the present invention conceptually shown in FIG. 1, and in addition to that shown in FIG. The same reference numerals as those shown in FIGS. 1 and 3 indicate the same parts, so the explanation will be omitted.

In normal operation, as the write address generation counter 1 is incremented by a clock signal corresponding to each time slot of the input data, the converted write address output from the ROM 2 is applied to the RAM 4, and at the same time the input data is transferred to the RAM 4. is written to the specified address. When reading, the selector 6 is switched, and as the read address generation counter 3 increments based on the clock signal, the contents of the RAM 3 are sequentially read out by the output of the counter 4, and the positions of each time slot of the time-division multiplexed input data are rearranged. The output data is sent out via the flip-flop 7.

On the other hand, during testing, the address output converted by the ROM 2 is given to the RAM 4 via the selector 6, and the selector 5 is switched so that the output address of the ROM 2 itself is sent via the selector 5 to the RAM 4 instead of the input data. will be written to. As a result, the output address of the write address generation counter 1 becomes the write address of the RAM4, and the input data is stored in the RAM4.

At the time of reading, the selector 6 is switched by a timing pulse, and as the read address generation counter 3 increments in accordance with the clock signal, the output of the counter 3 sequentially changes the contents of the RAM 4, that is, in this case, the ROM.
2 conversion address is read and output.

Therefore, by inspecting the time slot position and contents of the data output from the RAM 4 via the flip-flop 7, it is possible to judge whether the translation address generated by the ROM 2, which is known in advance, is normal or abnormal. .

〔Effect of the invention〕

As described above, according to the data rearrangement circuit of the present invention,
The selector is configured to switch so that in test mode, the address itself is written to RAM using the address converted by the ROM, so testing of the ROM that provides data sorting operations does not require an external complex pattern generator. The effect is that it can be easily done without requiring it.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of a data reordering circuit according to the present invention. Fig. 2 is a block diagram showing an embodiment of a data reordering circuit according to the present invention. Fig. 3 is a diagram showing an example of a conventional data reordering circuit. , FIG. 4 is a time chart showing the relationship between data input and output of the data rearrangement circuit. In FIG. 1, ① is a write address generation counter, and 2 is a ROM. 3 is RAM. 4 represents a read address generation counter, and 5 represents a selector. In the drawings, the same or corresponding parts are indicated by the same reference numerals. Patent applicant Fujitsu Co., Ltd. Agent Patent Attorney
Mori 1) Hiroshi (1 other person) Ryoaki Moto's principle diagram of data parallelization circuit Mitsuaki Ki's example diagram b pi d) ii Katana

Claims (1)

[Claims] A counter (1
), a ROM (2) for converting the write address and rearranging input data, a counter (3) for generating a read address, and a ROM (3) for writing the input data to the converted address and using the read address. In a data rearrangement circuit composed of a RAM (4) that outputs the written data, the input data is normally sent to the RAM at the converted address.
A data rearrangement circuit characterized in that it is provided with a selector (5) for switching so that the address itself is written in the RAM (4) using the converted address in a test mode.