JPS63165932U - - Google Patents

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Publication number
JPS63165932U
JPS63165932U JP5829387U JP5829387U JPS63165932U JP S63165932 U JPS63165932 U JP S63165932U JP 5829387 U JP5829387 U JP 5829387U JP 5829387 U JP5829387 U JP 5829387U JP S63165932 U JPS63165932 U JP S63165932U
Authority
JP
Japan
Prior art keywords
converter
digit
voltage divider
resistive voltage
order
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5829387U
Other languages
English (en)
Other versions
JPH0528831Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987058293U priority Critical patent/JPH0528831Y2/ja
Publication of JPS63165932U publication Critical patent/JPS63165932U/ja
Application granted granted Critical
Publication of JPH0528831Y2 publication Critical patent/JPH0528831Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】
第１図は本考案の実施例を示す回路図、第２図
は本考案の他の実施例を示す回路図、第３図は従
来例を示す回路図である。 Ａ０〜Ａ１５；デジタルデータ入力端子、Ｂ１
；アナログデータの出力端子、１；上位側デコー
ダ、２；下位側デコーダ、３；上位側Ｄ／Ａ変換
器、４；下位側Ｄ／Ａ変換器、５；電源、Ｔ１，
Ｔ２；トランスミツシヨンゲート、Ｂ２，Ｂ３；
測定用端子。

Claims (1)

    【実用新案登録請求の範囲】
  1. 入力されたデジタルデータをデコードする上位
    桁デコーダ及び下位桁デコーダと、これら上位桁
    及び下位桁デコーダによつてデコードされたデー
    タに応じたアナログ値を複数の単位抵抗の直列回
    路からなる抵抗分圧器によつて生成する直列接続
    された上位桁Ｄ／Ａ変換器及び下位桁Ｄ／Ａ変換
    器と、これら上位桁Ｄ／Ａ変換器及び下位桁Ｄ／
    Ａ変換器の出力を加算する加算器と、を有するＤ
    ／Ａ変換装置において、前記下位桁Ｄ／Ａ変換器
    の抵抗分圧器に並列接続され上位桁Ｄ／Ａ変換器
    の抵抗分圧器の単位抵抗の少なくとも１つ分の抵
    抗値を有する抵抗と、前記下位桁Ｄ／Ａ変換器の
    抵抗分圧器の両端部に設けられた測定端子と、を
    有することを特徴とするＤ／Ａ変換装置。
JP1987058293U 1987-04-17 1987-04-17 Expired - Lifetime JPH0528831Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987058293U JPH0528831Y2 (ja) 1987-04-17 1987-04-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987058293U JPH0528831Y2 (ja) 1987-04-17 1987-04-17

Publications (2)

Publication Number Publication Date
JPS63165932U true JPS63165932U (ja) 1988-10-28
JPH0528831Y2 JPH0528831Y2 (ja) 1993-07-23

Family

ID=30888742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987058293U Expired - Lifetime JPH0528831Y2 (ja) 1987-04-17 1987-04-17

Country Status (1)

Country Link
JP (1) JPH0528831Y2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6879174B2 (en) 2000-09-29 2005-04-12 Sharp Kabushiki Kaisha Testing method and testing device for semiconductor integrated circuits

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11214183A (ja) * 1998-01-22 1999-08-06 Hochiki Corp 発光回路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5911025A (ja) * 1982-07-12 1984-01-20 Hitachi Ltd 半導体集積回路における抵抗回路
JPS5970313A (ja) * 1982-10-15 1984-04-20 Nec Corp デイジタルアナログ変換装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5911025A (ja) * 1982-07-12 1984-01-20 Hitachi Ltd 半導体集積回路における抵抗回路
JPS5970313A (ja) * 1982-10-15 1984-04-20 Nec Corp デイジタルアナログ変換装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6879174B2 (en) 2000-09-29 2005-04-12 Sharp Kabushiki Kaisha Testing method and testing device for semiconductor integrated circuits

Also Published As

Publication number Publication date
JPH0528831Y2 (ja) 1993-07-23

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