JPS63165846U - - Google Patents

Info

Publication number
JPS63165846U
JPS63165846U JP5838187U JP5838187U JPS63165846U JP S63165846 U JPS63165846 U JP S63165846U JP 5838187 U JP5838187 U JP 5838187U JP 5838187 U JP5838187 U JP 5838187U JP S63165846 U JPS63165846 U JP S63165846U
Authority
JP
Japan
Prior art keywords
chip
attached
lead frame
tab
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5838187U
Other languages
English (en)
Japanese (ja)
Other versions
JP2524967Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987058381U priority Critical patent/JP2524967Y2/ja
Publication of JPS63165846U publication Critical patent/JPS63165846U/ja
Application granted granted Critical
Publication of JP2524967Y2 publication Critical patent/JP2524967Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1987058381U 1987-04-17 1987-04-17 ワイヤボンデイング実装体 Expired - Lifetime JP2524967Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987058381U JP2524967Y2 (ja) 1987-04-17 1987-04-17 ワイヤボンデイング実装体

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987058381U JP2524967Y2 (ja) 1987-04-17 1987-04-17 ワイヤボンデイング実装体

Publications (2)

Publication Number Publication Date
JPS63165846U true JPS63165846U (cs) 1988-10-28
JP2524967Y2 JP2524967Y2 (ja) 1997-02-05

Family

ID=30888901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987058381U Expired - Lifetime JP2524967Y2 (ja) 1987-04-17 1987-04-17 ワイヤボンデイング実装体

Country Status (1)

Country Link
JP (1) JP2524967Y2 (cs)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105970A (en) * 1977-02-28 1978-09-14 Hitachi Ltd Assembling method for semiconductor device
JPS58143541A (ja) * 1982-02-22 1983-08-26 Hitachi Ltd 半導体装置
JPS622626A (ja) * 1985-06-28 1987-01-08 Nec Corp 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105970A (en) * 1977-02-28 1978-09-14 Hitachi Ltd Assembling method for semiconductor device
JPS58143541A (ja) * 1982-02-22 1983-08-26 Hitachi Ltd 半導体装置
JPS622626A (ja) * 1985-06-28 1987-01-08 Nec Corp 半導体装置

Also Published As

Publication number Publication date
JP2524967Y2 (ja) 1997-02-05

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