JPS63164621A - Reference voltage generator - Google Patents

Reference voltage generator

Info

Publication number
JPS63164621A
JPS63164621A JP31203486A JP31203486A JPS63164621A JP S63164621 A JPS63164621 A JP S63164621A JP 31203486 A JP31203486 A JP 31203486A JP 31203486 A JP31203486 A JP 31203486A JP S63164621 A JPS63164621 A JP S63164621A
Authority
JP
Japan
Prior art keywords
resistor
correction
chip
reference resistor
film thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31203486A
Other languages
Japanese (ja)
Inventor
Akihiro Kanda
神田 彰弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP31203486A priority Critical patent/JPS63164621A/en
Publication of JPS63164621A publication Critical patent/JPS63164621A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To improve the accuracy and resolution without increasing circuits by making a reference resistor and a correction resistor by the same material at the same time, directing the current flowing through the reference resistor and the correction resistor opposite to each other in a chip thereby compensating the nonlinear error between the reference resistor and the correction resistor due to the dispersion in the film thickness. CONSTITUTION:The reference resistor 1 and the correction resistor 2 are made of the same material, e.g., Al vapor-deposition film at the same time. Moreover, a voltage is applied in a way that the direction of the current flowing to the reference resistor 1 and the direction of the current flowing to the correction resistor 2 are made opposite to each other. For example, the left side of the chip in the reference resistor 1 is brought into a high potential to cause the current to flow from the left to the right of the chip. On the other hand, the right side of the chip in the correction resistor 2 is brought into a high potential to cause the current to flow from the right to the left of the chip. Thus, the tendency in the film thickness dispersion of the material used for the reference resistor 1 and the correction resistor 2 is identical in the chip and the error of the resistance due to the film thickness dispersion is correction to improve the accuracy.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は高精度、高分解能のアナログ−デジタル変換器
(以下ADC)等における基準電圧発生装置に関するも
のである。以下ADCについて説明する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a reference voltage generating device for a high-precision, high-resolution analog-to-digital converter (hereinafter referred to as ADC). The ADC will be explained below.

従来の技術 ADC,特にビデオ信号用のADCにおいては。Conventional technology In ADCs, especially ADCs for video signals.

高速性が要求されるために並列型ADCが主流となって
いる。この並列型ADCでは各々の比較器に基準電圧を
与えるためにAI等で基準抵抗を形成しているが、10
ビット以上のADCでは、高分解能、高精度を実現する
ために補正抵抗を設ける必要がある。従来の補正抵抗を
有する並列型ADCのブロック図を第4図に示す。基準
抵抗1(’1〜”1023)  はA4 、補正抵抗2
(R1−R9)はボロンをイオン注入した多結晶シリコ
ンで形成されている。10ピツ)ADCにおいては10
24個の比較器3(C1〜C1゜24) が必要とされ
るわけであるが、その各々に基準抵抗1から微小電流が
流れ込むため忙、第6図に示すように実際に比較器3に
与えられる電位が理想電位からずれ誤差が生じる。そこ
で基準抵抗1の任意の点、たとえば64個めあるいは1
28個めごとに補正抵抗2から電位を与え、第6図に示
すように補正をしている。ところが補正抵抗2自体にも
膜厚バラツキによる非線形誤差が生じ、実際には第7図
のようにトータルの非線形誤差が大きくなる場合がよく
Parallel type ADCs have become mainstream because high speed is required. In this parallel type ADC, a reference resistor is formed using AI or the like in order to provide a reference voltage to each comparator.
For ADCs of bits or more, it is necessary to provide a correction resistor in order to achieve high resolution and high precision. A block diagram of a conventional parallel ADC with correction resistors is shown in FIG. Reference resistance 1 ('1~''1023) is A4, correction resistance 2
(R1-R9) are formed of polycrystalline silicon into which boron ions are implanted. 10 points) 10 in ADC
24 comparators 3 (C1 to C1゜24) are required, but since a small current flows into each of them from the reference resistor 1, it is busy, and as shown in Fig. 6, the comparators 3 are actually The applied potential deviates from the ideal potential and an error occurs. Therefore, any point on the reference resistance 1, for example the 64th or 1st
A potential is applied from the correction resistor 2 to every 28th point, and correction is performed as shown in FIG. However, nonlinear errors occur in the correction resistor 2 itself due to variations in film thickness, and in reality, the total nonlinear error often becomes large as shown in FIG.

ある。be.

発明が解決しようとする問題点 このような従来の補正抵抗を有する並列型ADCにおい
ては、誤差を生じる要因として基準抵抗から比較器への
入力電流以外に、基準抵抗のAlの膜厚バラツキ、補正
抵抗の多結晶シリコンの膜厚バラツキ等があシ、それは
蒸着あるいはデボ装置に依存している。たとえばADC
の非線形誤差を十−!−LSBに抑えるためには、多結
晶シリコンの膜厚バラツキをチップ内で±0.4%に抑
える必要があるが非常に難しい。また基準抵抗と補正抵
抗がそれぞれ別の材料によ多形成されているために、膜
厚バラツキによる誤差をあらかじめ予測し、それを回路
的に補正することも困難:Cある。
Problems to be Solved by the Invention In such a conventional parallel type ADC with a correction resistor, factors that cause errors include, in addition to the input current from the reference resistor to the comparator, variations in the Al film thickness of the reference resistor and correction. There are variations in the thickness of the polycrystalline silicon resistor, which depends on the vapor deposition or debostation equipment. For example, ADC
The nonlinear error of 10−! - In order to suppress the LSB, it is necessary to suppress the variation in the polycrystalline silicon film thickness within the chip to ±0.4%, but this is extremely difficult. Further, since the reference resistor and the correction resistor are each made of different materials, it is difficult to predict errors due to film thickness variations in advance and correct them using a circuit.

本発明はかかる点に鑑みてなされたもので、装置の改良
あるいは補正の几めに回路を増やすことなく、非線形誤
差の小さい高分解能、高精度のADC等に用いる基準電
圧発生装置を提供することを目的としている。
The present invention has been made in view of the above, and an object of the present invention is to provide a reference voltage generating device for use in a high-resolution, high-precision ADC, etc., with small nonlinear errors, without increasing the number of circuits for device improvement or correction. It is an object.

問題点を解決するだめの手段 本発明は上記問題点を解決するために、基準抵抗と補正
抵抗を同一の材料たとえばAtで形成し、さらに基準抵
抗と補正抵抗の電流の向きが逆になるようにすることに
より、基準抵抗及び補正抵抗に使用している材料の膜薄
バラツキにより生じる非線形誤差を最小にしようとする
ものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention forms the reference resistor and the correction resistor from the same material, for example At, and furthermore, the direction of the current in the reference resistor and the correction resistor is reversed. This is intended to minimize nonlinear errors caused by variations in film thickness of materials used for the reference resistor and correction resistor.

作  用 本発明は上記のようK、基準抵抗と補正抵抗を同一の材
料で形成しているために、その膜厚バラツキの傾向がチ
ップ内で同一となり、さらに基準抵抗及び補正抵抗を流
れる電流の向きがチップ内で逆向きになるようにしてい
るために、たとえば、チップの左から右に向かって膜厚
が減少している場合、基準抵抗においては、左から右に
向かって抵抗が増加するが、補正抵抗では逆に右から左
に向かって抵抗が増加することになり、材料の膜厚バラ
ツキによる非線形誤差を最小にすることができる。
Function: As described above, in the present invention, since the reference resistor and the correction resistor are made of the same material, the tendency of the film thickness variation is the same within the chip, and furthermore, the current flowing through the reference resistance and the correction resistor is For example, if the film thickness decreases from the left to the right of the chip because the direction is reversed within the chip, the resistance increases from the left to the right in the standard resistance. However, in the case of a correction resistor, the resistance increases from right to left, and nonlinear errors due to variations in material thickness can be minimized.

実施例 第1図は本発明の補正抵抗を有する並列型ADCのブロ
ック図である。基準抵抗1と補正抵抗2を同一の材料比
とえばAl蒸着膜によシ同時に形成する。さらに基準抵
抗1に流れる電流の向きと、補正抵抗2に流れる電流の
向きが逆になるように電圧を印加する。たとえば第2図
に実際のチップ上での基準抵抗1と補正抵抗2のレイア
ウト及びそれらの接続の方法の模式図を示す。基準抵抗
1においてはチップの左側が高電位になるようにし、電
流がチップの左から右に流れるようにする。一方、補正
抵抗2においてはチップの右側が高電位になるようにし
、電流がチップの右から左に流れるようにする。当然の
ことながら基準抵抗1と補正抵抗2の最高電位同士及び
最低電位同士は同電位となるように接続する。補正抵抗
2を9ブロツクに分割し、8ケ所からタップ4t−取シ
出し、タップ4の番号を高電位側からTO,T1.T2
.T3゜T4.T、、T6.T7.T8.T9 とする
。R2−R7の抵抗値はR1左側R9及び右端R1の抵
抗値はiとなるようにする。10ビツトADCの場合、
基準抵抗1は1023個に等分割されるが、その各々の
抵抗の番号を高電位側からr、〜r、。23とする。タ
ップT、を基準抵抗1の”64  とT66の間に、タ
ップT2をT19゜とr、93の間に、タップT3をr
3□。とr3□、の間に、タップT4t−r448とT
449の間圧、タップ”5”T576と”577の間に
、タップ”6”T704とT7゜6の間に、夕・ンプT
 をr  とr  の間に、タップT8を”96゜とT
96.の間にそれぞれ第2Al配線等で接続する。
Embodiment FIG. 1 is a block diagram of a parallel type ADC having a correction resistor according to the present invention. The reference resistor 1 and the correction resistor 2 are formed at the same time using the same material ratio, for example, an Al vapor deposited film. Further, a voltage is applied so that the direction of the current flowing through the reference resistor 1 and the direction of the current flowing through the correction resistor 2 are opposite to each other. For example, FIG. 2 shows a schematic diagram of the layout of the reference resistor 1 and the correction resistor 2 on an actual chip and the method of connecting them. In the reference resistor 1, the left side of the chip is set to a high potential so that current flows from the left to the right of the chip. On the other hand, in the correction resistor 2, the right side of the chip is set to a high potential so that the current flows from the right to the left of the chip. Naturally, the reference resistor 1 and the correction resistor 2 are connected so that the highest potentials and the lowest potentials thereof are the same potential. Divide the correction resistor 2 into 9 blocks, take out taps 4t from 8 locations, and number the taps 4 from the high potential side as TO, T1, . T2
.. T3゜T4. T,,T6. T7. T8. Let it be T9. The resistance value of R2-R7 is set to be R1, the resistance value of R9 on the left side, and the resistance value of R1 on the right side is i. In the case of 10-bit ADC,
The reference resistor 1 is divided into 1023 equal parts, and the number of each resistor is r, ~r, from the high potential side. 23. Tap T is between 64 and T66 of reference resistor 1, tap T2 is between T19 and r, 93, and tap T3 is r.
3□. and r3□, taps T4t-r448 and T
449 pressure, tap "5" between T576 and "577," tap "6" between T704 and T7゜6,
between r and r, tap T8 to 96° and T
96. A second Al wiring or the like is connected between them.

抗の抵抗値をRn とすると、基準抵抗と補正抵抗は第
3図のような等何回路で表わすことができる抵抗はr 
、=r s =R、=Rs =、、 e”2= ra=
 ”4= rs= ’e= r7= r8=R2=R3
=R4=R5=R8=’7=”8=Rとなるように設計
されている。今Al膜の膜厚がチップの左側から右側に
向けて一様に増力口している場合を考えると、明らかに
r 、/Rs ” r 9/)l 、。
If the resistance value of the resistor is Rn, then the reference resistor and the correction resistor can be represented by a circuit like the one shown in Figure 3.The resistance is r.
,=rs=R,=Rs=,, e”2=ra=
``4=rs='e=r7=r8=R2=R3
It is designed so that =R4=R5=R8='7=”8=R. Now consider the case where the thickness of the Al film increases uniformly from the left side to the right side of the chip. , obviously r , /Rs ” r 9/)l ,.

r 2/R8= r 8/R2,r 3/R7= r 
7/Ra、 r4/R6=rt4である。また、Al膜
の増加によシ各タップ間の抵抗の抵抗値がaチ減少した
とすると、inm!H−1(’ −* 00 ) m 
R,=RB−1(’ −* oo )となる。
r 2/R8= r 8/R2, r 3/R7= r
7/Ra, r4/R6=rt4. Also, if the resistance value of the resistor between each tap decreases by a due to the increase in the Al film, then inm! H-1('-*00) m
R,=RB-1('-*oo).

T とT 間の抵抗値とT3と14間の抵抗値の差につ
いて考える。r 2=12”Rとするとr3””2(1
100”””’−100)R7=12(1−、H石)=
R(1−100)(1(ゐ(1鴎給)同様に r4=r2(1−1oo ) ”R(’ −100’R
6=R2(1−る) =R(1−函)■、■よシ隣り合
ったタップ間の抵抗値の変化分は、 となる。ここでa=1%とすると、 となシ、sb合ったタップ間の基準抵抗が膜厚バラツキ
により1チ変化した場合においても、上記の様な補正方
法をとることによシ、隣)合ったタッグ間の抵抗値の変
動を0.0151 におさえることができ、事実上補償
される。
Consider the difference in resistance between T and T and between T3 and 14. If r2=12"R, then r3""2(1
100"""'-100) R7=12(1-, H stone)=
R(1-100)(1(ゐ(1驎) Similarly, r4=r2(1-1oo) ``R('-100'R
6=R2(1-ru) =R(1-box) The change in resistance value between adjacent taps in ■ and ■ is as follows. Here, if a = 1%, then even if the reference resistance between taps that match sb changes by 1 inch due to film thickness variation, by using the above correction method, it will be possible to The variation in resistance value between tags can be suppressed to 0.0151, and is effectively compensated for.

このように基準抵抗1と補正抵抗2t−同一の材料で同
時に形成していることによシ、基準抵抗1と補正抵抗2
に用いた材料の膜厚バラツキの傾向がチップ内で同じと
なり、さらに上記のように基準抵抗1と補正抵抗2に流
れる電流の向きをチップ内で逆方向にすることによシ、
膜厚バラツキによる抵抗値の誤差を補正することができ
、高精度のADCが得られる。この効果は特に膜厚がチ
ップの左右方向に一様に変化する場合に大となる。
In this way, because the reference resistor 1 and the correction resistor 2t are made of the same material at the same time, the reference resistor 1 and the correction resistor 2t
By making the tendency of film thickness variation of the material used in
Errors in resistance values due to film thickness variations can be corrected, and a highly accurate ADC can be obtained. This effect becomes especially large when the film thickness changes uniformly in the left-right direction of the chip.

発明の効果 以上のように本発明は並列型ADC等における基準抵抗
と補正抵抗を同一の材料で同時に形成し、しかも基準抵
抗と補正抵抗とを流れる電流の向きがチップ内で逆方向
になるようにすることによシ、膜厚バラツキによる基準
抵抗と補正抵抗の非線形誤差がお互いに補償し合うよう
にしたものであり、回路を増やすことなく高分解能、高
精度の並列型ADC等圧用いる基準電圧発生装置を実現
できる方法であり、実用的にきわめて有用である。
Effects of the Invention As described above, the present invention allows the reference resistor and the correction resistor in a parallel type ADC etc. to be formed simultaneously from the same material, and furthermore, the direction of the current flowing through the reference resistor and the correction resistor is opposite within the chip. By doing so, nonlinear errors in the reference resistor and correction resistor due to film thickness variations are compensated for each other, and it is possible to use a high-resolution, high-precision parallel type ADC equal voltage standard without increasing the number of circuits. This is a method that can realize a voltage generator, and is extremely useful in practice.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のADCのプC1−)り図、
第2図は第1図のADCのチップ上でのレイアウト図、
第3図は第1図の抵抗部分の等価回路図、第4図は従来
のADCの一例のブロック図、第6図、第6図、第7図
はADCにおける電圧特性図である。 1・・・・・・基準抵抗(r、〜r、。23)、2・・
・・・・補正抵抗(R,〜R9)、3・・・・・・比較
器(C1〜C1024)’4・・・・・・タップ(T、
〜T8)。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第3図 +トドC坦ボ 5δ 第4図 第5図 入力亀5圧。 第6図 第7図
FIG. 1 is a diagram of an ADC according to an embodiment of the present invention;
Figure 2 is a layout diagram of the ADC shown in Figure 1 on the chip.
FIG. 3 is an equivalent circuit diagram of the resistor portion of FIG. 1, FIG. 4 is a block diagram of an example of a conventional ADC, and FIGS. 6, 6, and 7 are voltage characteristic diagrams in the ADC. 1...Reference resistance (r, ~r, .23), 2...
...Correction resistor (R, ~R9), 3...Comparator (C1-C1024)'4...Tap (T,
~T8). Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 + Todo C flat bottom 5δ Figure 4 Figure 5 Input turtle 5 pressure. Figure 6 Figure 7

Claims (1)

【特許請求の範囲】[Claims] 異る2つの電位間に接続され、複数の基準電圧を発生さ
せる複数個の抵抗体と、異る2つの電位間に接続され、
前記抵抗体と同一の材料で同時に形成された複数個の補
正抵抗体とを具備し、前記複数個の抵抗体と前記複数個
の補正抵抗体に流れる電流を配置される方向に対して逆
向きに流す手段を有することにより、前記抵抗体の抵抗
値がバラツキを有していた場合にも高精度の基準電圧が
得られるようにしたことを特徴とする基準電圧発生装置
a plurality of resistors connected between two different potentials and generating a plurality of reference voltages; and a plurality of resistors connected between two different potentials,
a plurality of correction resistors formed simultaneously of the same material as the resistor, and a current flowing through the plurality of resistors and the plurality of correction resistors is directed in a direction opposite to the direction in which they are arranged. 1. A reference voltage generating device characterized in that a highly accurate reference voltage can be obtained even when the resistance value of the resistor has variations by having a means for supplying a voltage to the reference voltage.
JP31203486A 1986-12-26 1986-12-26 Reference voltage generator Pending JPS63164621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31203486A JPS63164621A (en) 1986-12-26 1986-12-26 Reference voltage generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31203486A JPS63164621A (en) 1986-12-26 1986-12-26 Reference voltage generator

Publications (1)

Publication Number Publication Date
JPS63164621A true JPS63164621A (en) 1988-07-08

Family

ID=18024422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31203486A Pending JPS63164621A (en) 1986-12-26 1986-12-26 Reference voltage generator

Country Status (1)

Country Link
JP (1) JPS63164621A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06152425A (en) * 1992-06-12 1994-05-31 Yamaha Corp D/a converter
JPH0786940A (en) * 1993-09-09 1995-03-31 Nec Corp Serial/parallel a/d converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06152425A (en) * 1992-06-12 1994-05-31 Yamaha Corp D/a converter
JPH0786940A (en) * 1993-09-09 1995-03-31 Nec Corp Serial/parallel a/d converter

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