JPS59148914A - Current source arrangement - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides means for generating a plurality of currents with a current ratio of at least pairs approximately equal to a predetermined current ratio; The present invention relates to a current source arrangement comprising means for detecting deviations from the current value required to obtain the ratio and means for correcting said current to reduce the detected deviations.

In various fields of electronics, there is a need for circuits capable of supplying current values that are held in extremely precise proportions to each other. Such circuits are required, for example, in measuring devices in which different current proportions are required for the selection of the measuring range, and in digital-to-analog converters in which a plurality of currents are added together according to a digital code to form an analog signal. .

It is known to generate a binary weighted current in a digital-to-analog converter by supplying a reference voltage across a resistor with a binary weighted resistance value or across a so-called ladder network.B The accuracy of this type of digital-to-analog converter depends primarily on the resistance ratio. In order to obtain a resistance ratio with an accurate value, these resistors must be finely adjusted (trimmed) using, for example, a laser. However, in practice, trimming such resistors is time consuming and expensive.

Other known methods of generating accurate current proportions use dynamic element matching principles. This principle is described in U.S. Pat. No. 8,982,172 and U.S. Pat. No. 41,258.
It is known from the specification of No. 08. In these publications, a current source arrangement is used to provide multiple currents having approximately equal current values due to the limited accuracy of the integration process. These currents are transferred by a permutation circuit to its output according to a cyclic permutation. The currents on the output side each comprise a direct current of a value equal to the average value of the currents from the current source arrangement and a ripple superimposed on this direct current formed by the difference between the currents from the current source arrangement. This current ripple can be removed by placing a filter capacitor on each output side of the permutation circuit. However, such filter capacitors cannot be integrated due to their value being 1 greater and must be connected externally to the integrated circuit. This requires additional connection bins and therefore adds to the price. For example, a 16-bit 5-bit digital-to-analog converter using such a current source arrangement would require 16 additional connection pins.

This means that a method is needed that can easily generate currents with accurate mutual current ratios.

A current source arrangement of the type described above is a solid-state circuit eye, 1'.

E. E. Journal, Volume 5o-16, No. 6, 1
Article 6 Antrimmed D/A Converter with 1 published in December 1981, pages 616-620
This digital-to-analog converter comprises a ladder-shaped network of untuned resistances.The deviation of the current value corresponds to the current value of the digital-to-analog converter. It is detected by comparing the output voltage with an extremely precise sawtooth waveform.

Information regarding this shift is stored in a storage device. This information is then used to drive the secondary digital-to-analog converter, thereby allowing the current excursions of the digital-to-analog converter to be eliminated.

Such a circuit arrangement requires a sawtooth voltage with very high linearity over a wide range without requiring fine adjustment of the resistance, but such a sawtooth voltage is difficult to obtain.

It is an object of the invention to provide a current source arrangement which makes it possible to easily generate a plurality of currents with precise current ratios to each other.

The present invention provides means for generating a plurality of currents in which at least a pair of current ratios is approximately equal to a predetermined current ratio, and a deviation of at least a number of current values from a current value required to obtain the predetermined current ratio. and means for correcting said current to reduce the detected deviation;
The means for detecting the deviation of the current value comprises a precision current mirror circuit having one input terminal and at least one output terminal at which a current of a value appears in the correct proportion to the current of the input terminal; Use at least a pair of multiple currents!・.

a coupling network for cyclically coupling at least a number of currents 1 from the means for generating currents to an input terminal and at least one output terminal of said current mirror circuit; 5 currents from a plurality of current generating means provided and coupled to the output side and a detection circuit for detecting a difference current between the currents from the current mirror circuit appearing at the output side. do.

The invention is based on the fact that deviations in the current ratio can be detected by supplying current to a current mirror that can operate very accurately.

The number of outputs of the current mirror is limited and is at least one. A number of currents from a plurality of current generating means are coupled to a current mirror through a coupling network, one current being coupled to the input side of the current mirror, and the other several currents being coupled to the input side of the current mirror. Connect to the output side. The ratio of the current coupled to the output side and the current coupled to the input side is made approximately equal to a predetermined value. However, since a return current also appears on the output side of the current mirror, the ratio of these currents on the output side to the current on the input side is y.

It must be very precisely equal to a predetermined value. The difference between the inaccurate current from the plurality of current generating means and the accurate return current at the output of the current mirror is detected by a detection circuit. This detection circuit complements the associated currents from the plurality of current generating means.

The ratio of this current to the current on the input side is exactly equal to the current mirror ratio for this output of the current mirror. After correction of the currents, the remaining number of currents is coupled via a coupling network to the output of the current mirror, with eleven of the previously corrected currents being coupled to the input of the current mirror. In this way, the current mirror circuit processes all or at least a number of the currents from the plurality of current generating means through the coupling network, thus repeating the processing cycle described above. In this way, 1. with a small number of outputs.
A large number of currents can be obtained in precise proportions to each other by means of a current mirror.

In the practice of the present invention, a current mirror circuit includes a plurality of transistors having parallel connected main current paths and a common control electrode driven by an amplifier whose input side is coupled to the input side of the current mirror circuit. a current distribution circuit; and an eight permutation circuit for transferring current from the current distribution circuit to an input terminal and at least one output terminal of the current mirror circuit according to a cyclic permutation.

Precision current mirror circuits can be advantageously implemented using dynamic element matching principles. This dynamic element matching principle is described in US Pat. No. 898,217 as described above.
2 and 4125808. Therefore, the direct current ratio of the current on the output side of the current mirror circuit 1 becomes extremely accurate.

These ripple currents superimposed on the direct current can be filtered and removed by providing filter capacitors on the input and output sides of the current mirror circuit. Since the number of output terminals of the current mirror circuit is small (15), the number of external connections of the filter capacitor to the integrated circuit is limited. Due to the small number of output terminals, the permutation circuit can also operate at low frequencies, which also makes it possible to obtain high accuracy.

In a preferred embodiment of the invention, each detection circuit comprises a first current-to-voltage converter, and in particular each eleventh current-to-voltage converter has a first input terminal associated with the current mirror circuit. an amplifier having a second input terminal coupled to a reference voltage point and an output terminal coupled to the first input terminal via a feedback capacitor. This causes the amplifier to act as an integrator.

Also, in one embodiment of the invention, the means for correcting the currents comprises a second fi current-to-voltage converter associated with each current to be corrected;
The second current-to-voltage converter comprises an amplifier whose output terminal 1, . so that it can be joined to the side. This switching capacitor transfers the charge of the capacitor of the first current-voltage converter 1 to the capacitor of the second current-voltage converter. The capacitor of such a second current-to-voltage converter correcting the associated current makes it possible to maintain the corrected voltage at least until the associated interconnect of the next cycle of the coupling network. The output of the amplifier of the voltage converter is coupled to a first input terminal of a comparator 1 and a reference voltage is supplied to a second input terminal thereof.

This comparator converts the output signal of the amplifier into a logic signal.

In carrying out the invention, the means for correcting the currents comprises five counting circuits associated with each current to be corrected, the counting circuits being coupled via a switch to the output of the current-to-voltage converter. At the same time, this counting circuit generates a plurality of logic signals depending on the logic signals at the output of the comparator, and these logic signals are converted into analog output signals by ten digital-to-analog converters, and by this output signal the related Make it possible to correct the current. The count of the counting circuit does not change until the ink noggle associated with the next cycle of the coupling network, thus retaining this correction signal by the 15 digital-to-analog converter during this interval.

In a preferred embodiment of the invention, the means for generating the plurality of currents required for the digital-to-analog converter comprises means for generating a plurality of currents of at least one type and 20 classes whose values vary according to a binary weighted series. Sip until it tastes good. A precision current mirror circuit can correct the current from one or more, for example, 16-bit digital-to-analog converters. Also, as required in the integrated circuit, the means for generating a plurality of currents may include means for generating a plurality of currents having approximately -5 equal current values. In another embodiment of the invention, the means for generating a plurality of currents includes a main current path of a respective first transistor, each extending between first and second main terminals, and a first main current path of an associated first transistor. a plurality of parallel branches having a resistor coupled to a terminal, connecting at least one output terminal and an input terminal of said current mirror circuit to said second main terminal or said first terminal of said resistor through a coupling network; 1 transistor so that it can be coupled to the opposite end of the transistor. Here, 1) the first main terminal of a transistor means the emitter or source electrode of bipolar and unipolar transistors, and the second main terminal of a transistor means the collector or drain electrode of bipolar and unipolar transistors. Further, a main current path of the field effect transistor is disposed in at least one of the parallel branches at an end of the resistor opposite to the first transistor 2, and the main current path of the field effect transistor is extending between the respective first and second main terminals and connecting the terminals to at least one output terminal and an input of the current mirror circuit to the second main terminal of the field effect transistor. Preferably, they are bonded.

The advantage of using field effect transistors is that undesired switching transitions caused by switching the coupling network have little effect on the current from the current source arrangement. In this circuit arrangement, it is advantageous to couple the output of the correction means to the gate electrode of the field-effect transistor.

The voltage at the gate electrodes of the field effect transistors, and thus the voltage difference between these electrodes and the common control electrode of the first transistor, is increased 15 or decreased so that the main currents of these transistors are corrected.

,! to The invention will be explained with reference to the drawings.

FIG. 1 shows a first example of an inventive current source arrangement in the form of a digital-to-analog converter. Generally, this current source arrangement consists of an actual digital-to-analog converter 1 (hereinafter referred to as D/A converter) which generates a plurality of binary weighted currents with precise mutual current ratios; a coupling network 15 capable of coupling a plurality of currents from the D/A converter 1 to a precise current mirror circuit 23 according to a periodic pattern, by means of which current mirror circuit detects a deviation in the ratio of the currents from the D/A converter 1. The detection means 80 controls the correction means 18.2 to 18.16 so that D
The associated current from the /A converter 1 can be corrected to reduce the deviation.

In this example, the D/A converter 1 is composed of 16 transistors 15 and 2.
．． 1-2.16. For a D/A converter that processes less than 10 bits, the current density of the entire emitter area of the transistor can be made equal using the binary method. In this example, each of these transistors 2.1 to 2.16 is 81
Equal current densities are obtained by arranging the transistors in two identical sections, and in this case, the emitter area of one transistor in each section is set as 5% of the emitter area of the transistor in the preceding stage. The division is a voltage source (not shown) placed at the baseline between them.
power is supplied to each other. The unfine-adjusted resistors 8.1 to 8.16 are arranged on the emitter lines of the transistors 2.1 to 2.16, and the resistance value of each resistor is approximately twice the resistance value of the preceding resistor. The common bases of the transistors 2.1 to 2.16 are coupled to the output side of the operational amplifier 4, and the input side of the operational amplifier 4 is connected. is coupled to a current source 5 which generates a current of .

The bases of these transistors are driven by the operational amplifier 4 and the collector current of the transistor 2.1, which is used as a reference current, is the current source of the current source 5. be exactly equal to . For this collector current of the reference transistor 2.1, if we ignore the precise identity of the resistor and the transistor, the collector current 2° of each of the transistors 2.2 to 2.16 is equal to the collector current of the preceding transistor. The value is approximately %. The reason for this is that the emitter voltages of all transistors are approximately equal. Therefore, the values of the currents from transistors 2.1 to 2.16 are, respectively.

. Engineering. /2. Engineering. /4　,---　I. /21δ.

Transistor.

A collector current of 2.1 to 2.16 can be supplied to the ground side or to the input of the amplifier 7 by means of switches 6.1 to 6.16 controlled by a digital input sign. The amplifier 7 has at its output terminal 9 an analog output signal 1·i which is associated with the digital input symbol and couples this output terminal 9 to the inverting input terminal via a feedback resistor 8 . A resistor 8°1 to 3.16 is connected to the source electrode of an n-channel field effect transistor 12.1 to 12.16, and the length-to-width ratio of its channel, optionally the channel length to channel length for each section, is The width ratio is measured according to the associated current values to keep the current densities equal and therefore the voltages between the gate and source electrodes of the transistors equal. In normal conditions, these drain electrodes are connected to the switches 16 , 120 , which form part of the coupling network 15 .
16. Connect to the constant potential point via 16. In this example, 1. This constant potential point is Ov. The gate electrode M1B,x of the transistor 12.1 is directly connected to a constant potential point, in this example, a zero volt point, and the gate electrodes 18.2 to 18.16 of the transistors 12.2 to 12.16 are connected to the correction circuit 18.1. 2~.

18 and 16 so that it can be connected to the constant potential point. In this example, for convenience of explanation, correction circuits 18.2 and 18.8 are used.
Only the other correction circuits 18.4 to 18.1 are shown in detail.
6 is shown diagrammatically only. The correction circuit 18.2 is an amplifier 19
．． 2, and a transistor on the output side.

It is coupled to the gate electrode IL2 of the gate electrode 12.2 and to the inverting input terminal via the capacitor 20.2.

The non-inverting input terminal of amplifier 19.2 is grounded. The capacitor 21.2 is shorted to ground or can be connected between the inverting input terminal of the amplifier 19.2 and the input terminal 24.2 by means of fifteen simultaneous control switches 22.2 and 28.2. The other correction circuits are also constructed in the same manner as described above.

Switch f-1 of the coupling network 15 is controlled by the control circuit 17.
By appropriately controlling transistors 6,1 to 16.16, the corctor emitter currents of eight consecutive transistors 2.1 to 2.16 are connected to the input terminal 26 of the precise current mirror circuit 25 and the output. The terminals 27 and 28 are coupled to each other according to a periodic pattern. Due to the high output resistance of the drain electrode and the low input resistance of the source electrode of each of the field effect transistors 12.1 to 12.16, the collector-emitter current of the transistors 2.1 to 2.16 during switching is reduced due to undesired switching transitions. Avoid being influenced. The figure shows reference transistor 2.1 coupled to input terminal 1026 and transistors 2.2 and 2.1 coupled to input terminal 1026.
8 to the respective output terminals 27 and 28 of the current mirror circuit 25
2 shows the state of the control circuit 17 coupled to the control circuit 17 during the first period of the cycle. The current mirror circuit 25 causes the reference current at the input terminal 26 to be reflected at the output terminals 27 and 28 at a precisely defined ratio. The current mirror circuit 25 includes transistors 80 to 86 connected in parallel, the emitters of which are connected to a common terminal 47 via the same resistors 40 to 46, and this common terminal 47 is used as a constant potential point, in this example, a power supply negative terminal. The common base of the transistors 80 to 3B is driven by an amplifier 49, and the input side of this amplifier is coupled to the input terminal 26 of the current mirror circuit 25. The common base voltage of these transistors is appropriately controlled by the amplifier 40 so that the sum of the currents at the output terminals 61, 62, 685 and 64 of the permutation circuit 50 becomes the collector-emitter current of the reference transistor 2.1. be equal to . The collector currents of the transistors 80-86 are made approximately equal to each other by a properly defined integration process, and in this example these collector currents are equal to the current factor from the reference transistor 2.1. By dividing. /, so that it is approximately equal to . These currents are supplied to the input terminals 51 to 57 of the permutation circuit 50.

The permutation circuit 50 is connected to a circuit 70 sequentially controlled by a clock signal generator 71, e.g.
■To control. The operation of this permutation circuit 5o is comprehensively described in the aforementioned US Pat. Nos. 8,982,172 and 4,125,808. Therefore, the permutation circuit 5o divides each of the collector currents of the transistors 51-57 according to the cyclic permutation so that it can be transferred to each of the output terminals 61-67. This causes each of the collector currents of transistors 80-86 to be generated at each of the output terminals 61-67. The direct current of each of the output terminals 61-67 is made equal to the average layer thickness of these collector currents by 50/4. These output currents have a ripple component due to the inequalities of the collector currents, which are averaged over the above average layer. /4 above and below. This ripple component is P
Wave and remove. The direct current, whose value is related to the direct current at the input terminal 26, will appear at the output terminals 27 and 28 of the precise current mirror circuit 25 in proportion exactly in the ratio 1:2:4. That is, the current flow from the reference transistor at input terminal 26. The value for /2 and reference work. A current exactly equal to / appears at the output terminals 27 and 28, respectively. Also, the value is important. /2 and engineering. Currents from transistors 2.2 and 2.8 approximately equal to /4 respectively also appear at output terminals 27 and 28. The difference between the current inaccurately applied to input terminal 26 and the current accurately reflected at output terminal 27 is a current-to-voltage conversion.

The difference between the current supplied to the input terminal 26 and the current reflected at the output terminal 28 is detected by the current-to-voltage converter 82. By both of these current-voltage converters 81 and 82.

Detection means 80 is configured. Output terminal 27 is connected to operational amplifier 8
8, and its non-inverting input terminal is connected to a constant potential point, in this example, a point Ov.

The output side of the amplification Wi8B is connected to the feedback capacitor 84.
and then connect to its inverting input terminal.

The output terminal 85 of the amplifier 88 is coupled to the input terminal 24.2 of the correction circuit 18.2 via a switching network (not shown for convenience of explanation). A capacitor 84 is charged with one current difference between the supplied inaccurate current and the accurate current value 0/2 reflected on the output terminal 27. 15 current-voltage converter 82
is constructed similarly to the current-voltage converter 81 and includes an amplifier 86 and a capacitor 87. An output terminal 88 of amplifier 86 is coupled to an input terminal 24.8 of correction circuit 18.8. The difference between the inaccurate current supplied and the accurately reflected current charges the capacitor 87 with a 2° (28) current.

After charging the capacitor 84, the capacitor 21.2 is switched between the input terminal 24.2 of the detection circuit 18.2 and the inverting input terminal of the amplifier 19.2 by switches 22.2 and 28.2. The charge on capacitor 84 is therefore transferred to capacitor 20.2 and charges this capacitor.

Similarly, since the capacitor 21.8 is switched between the input terminal 24.8 of the correction circuit 18.8 and the inverting input terminal of the amplifier 19.8 by switches 22.8 and 28.8, the charge on the capacitor 87 is It will now be transferred to 20°8. After capacitors 20.2 and 20.8 have been charged, capacitors 21.2 and 21.8 are shorted to ground by switches 22-8i 28-2 and 22.8i 28.8, respectively. At the same time, reset 15 switches 89 and 90 are closed to short-circuit capacitors 84 and 87, respectively.

Since the capacitors 20°2 and 20.8 are charged, the gate electrodes 18.2 of the transistors 12°2 and 12.8
and 18.8 increases or decreases to increase or decrease the voltage of transistor 21.
1 (24) 2.2 and 2.8 base and transistor 12゜2
and 12.8 with their respective gate electrodes 18.2 and 18.8, and thus the emitter currents of transistors 2.2 and 2.8 increase or decrease, which causes these currents to overlap more, respectively. . /2 and engineering. / is exactly equal to 5. Capacitors 20.2 and 20.8 hold the KO positive voltage. During the relevant period of the next cycle of the control circuit 17 the emitter currents of the transistors 2.2 and 2.8 are again correctly reflected by the current mirror circuit 25. /2 and engineering. /, compared with. The difference current between the currents compared by 1° is again detected by the detection circuits 81 and 82, and the charges are transferred to the capacitors 20.2 and 20.8 by the capacitors 21.2 and 21.8. Therefore, the emitter currents of transistors 2.2 and 2.8 are

/2 and engineering. /, more precisely equal to 15. In this way, these currents control the emitter currents of transistors 2.2 and 2.8. /2 and engineering. /4 in successive cycles until it is very precisely equal to /4. capacitor 20
-2 +20.8 and capacitor 21-2 + 21-
8 and 2° capacitors 84 and 87 are switched to switches IL8, 16.4 and 16.4 during the second period of the cycle of control circuit 17 whose value is set to a suitably small value so that these capacitors can be integrated. The emitter currents of transistors 2.8, 2°4 and 2°5 are controlled by precision currents by 5.

The current mirror circuit 25 is coupled to an input terminal 26 and output terminals 27 and 28, respectively. In this case the emitter current of the transistor 2.8 corrected in the previous period. /4 is used as the accurate input current of the current mirror circuit 25. Therefore, at the output terminals 27 and 28, exactly 1 (accurately reflected current ./8 and ./, 6 appear.

The incorrect emitter current difference of transistors 2.4 and 2.5 is also detected by detection circuits 81 and 82.

A correction circuit 1518 connects the output terminals 85 and 88 of the amplifiers 88 and 86 to the transistors 12.4 and 12.5.
．． 4 and 18.5, thereby correcting the emitter currents of transistors 2.4 and 2.5 so that these currents are corrected. /8 and engineering. /,
be very precisely equal to 6. In subsequent periods, the currents of transistors 2.6 to 2.16 are corrected in the same way as 211, and the minimum current of the eight currents corrected in the previous period is used as the accurate input current to the current mirror circuit 25 each time. make it available for use. After all currents have been corrected, the entire cycle should be repeated.

In this example, the collector emitter currents of all transistors 2.2 to 2.16 are corrected. In principle, it is necessary to correct only those currents whose values indicate an error greater than a predetermined fraction of the minimum current.

In this example, the current is corrected by controlling the voltage at the gate electrode of the field effect transistor. However, the current can also be corrected by controlling the voltage at the individual bases of the current source transistors.

A second example of an I5 source arrangement according to the invention in the form of a digital-to-analog converter will now be described with reference to FIG. In FIG. 2, the same elements as those shown in FIG. 1 are designated by the same reference numerals. The actual D/A converter 1 has 16 transistors 2.1
~2. '16 and untuned resistors 8.1 to 8.16 with binary weighted resistance values 8(27) In this example, the reference current is the maximum current, or the most significant bit.

Not equal to the associated current, but equal to the minimum current, ie, the current associated with the least significant bit. This reference current is generated by a transistor 2.17 whose emitter area is equal to that of the transistor 2.16, and a resistor 8.16 with a resistance value connected to the emitter line of the transistor 2.16.
A resistor 8.17 equal to the value of is placed. transistor 2
The base of ゜17 is driven by an operational amplifier 4, and the input side of the operational amplifier 4 is connected to a current. is coupled to the output side of the current source that generates the current. Immediately.

The bases of these transistors are driven by the operational amplifier 4, and the collector current of the reference transistor 2.17 is controlled. be exactly equal to .

Therefore, the collector current of transistors 2.16 to 2.1 is layered. , 2I. , 4I. ,---2I. becomes.

1° Switch controlled by digital input code 6.
1-6° 16 transfers the current to ground or to the input side of the amplifier 7, at the output of which an analog output signal appears. Emitter resistors 8.1 to 8.17 are connected via field effect transistors 12.1 to 12.17 21: (28
) Now connect to the switches 16.1 to 16.17 of the network 15, respectively. Field effect transistors 12.1-12.17
Of the gate electrodes, gate electrode 18.17 is grounded, and a correction circuit is connected to gate electrodes i18.1 to i18.16. Each correction circuit 14 has input terminals 14.41 to 5, respectively.
14.56, the output terminals of which are coupled to the input terminals of digital-to-analog converters 14.21 to 14.86, respectively, and the output terminals of these converters connected to the gate electrodes. 18.1 to 18.16, respectively. Depends on the desired control range and desired accuracy.

Counting circuits 14.1 to 14.16 include, for example, 6-bit counters with one sign bit, which sign bit determines the voltage at the output of 6-bit D/A converters 1.4.21 to 14.86. Specify the sign of D/A converter 14.2
1 to 14.86 generates an output voltage 15 when the count value is zero. The drawing shows reference transistor 2.17 coupled to input terminal 26 of precision current mirror circuit 25, and transistor 2.17 coupled to input terminal 26 of precision current mirror circuit 25.
16 and 2.15 to output terminals 27 and 28 during the first period of the cycle. The control circuit 17 controls the switch 2 (・chi 16.17~16°■
With appropriate control, two continuous emitter currents are coupled each time to the output terminals 27 and 28 of the current mirror circuit 25, so that the current at the input terminal 26 is connected to the parallel connected transistor 1o.
o~108, whose emitters are respectively connected to the same resistor 104
~107 to connect to the common terminal. The common bases of these transistors 100-108 are driven by an amplifier 49 whose input terminals are coupled to the input terminal 26 of a current mirror circuit 1.25. That is, the pace of these transistors is controlled by the amplifier 49 to output the output terminal 1 of the permutation circuit 50.
15 is made equal to the current at input terminal 26. The collector currents of the traton transistors 100 to 108 supplied to the input terminals 110 to 118 of the permutation circuit 50 are transmitted to the output terminals 115 to 108 according to a cyclic permutation by the permutation circuit 50.
Transfer to 118. The currents at output terminals 117 and 118 are both supplied to output terminal 28. Next, the ratio of the current at input terminal 26 to the current at output terminals 27 and 28 is set to 1:1.
:d Ripple components at these input terminals and output terminals are removed as P waves by externally connected filter capacitors 72, 78 and 74.

The current at input terminal 26 is controlled during the first period of the control circuit cycle. Make it equal to 5. Next, calculate the reflected currents at output terminals 27 and 28. and 2nd construction. be exactly equal to . Construction of transistors 2.16 and 2.15. and 2nd construction. Also coupled to output terminals 27 and 28 is an emitter current approximately equal to .

The detection circuits 81 and 8 detect the difference current between the accurately reflected currents of the output terminals 27 and 28 and the 1° and inaccurate emitter currents.
Detected by 2. The configuration of the detection circuit 81 is almost the same as in the first example, but the output terminal of the amplifier 88 is connected to the comparator 1.
The difference is that it is connected to the inverting input side of Q20, and its non-inverting input side is connected to a constant voltage point, in this example Q1.

Depending on whether the output voltage of the amplifier 88 is higher or lower than the zero value, the voltage at the output side of the comparator 120 is higher or lower and is used as a logic signal of value "l" or "0". The output side is connected to the counter 20 (
81) so that it can be coupled to the input terminal 14.56 of 14.16.

The counters 14, 16 step up or down depending on the value of the logic signal at the output of the comparator 120. The final count value of this counter is converted into 6 logic signals at the output side of the counter 14゜16, and this signal is converted into 6 bits) D/A converter 14.861
Convert this voltage to an analog output voltage at gate electrode 1.
Make it occur on 8.16. Similarly, the detection circuit 82
The output of comparator 121 is coupled via switch 92 to input terminal 14.55 of counting circuit 14.15 so that an analog output voltage appears at gate electrode 18.15 of transistor 12.15. Gate electrode 18.16
and 18.15 to reduce or increase the emitter currents of transistors 2.16 and 2.15, respectively. and 2nd construction. to be more precisely equal to . Counters 14, 1116 and 14
．． 15, and therefore the voltage at the gate electrodes 18, 16 and 18, 15 of the transistors remains unchanged until the relevant period of the next cycle. Because of this, during successive cycles transistors 12, 16 and 12
The emitter current of ゜15 is 2 mm and 2 mm with high precision, respectively. Complement 1 until equal to
It will be corrected. Control circuit 1 during the second period of the cycle
The emitter currents of transistors 2.17, 2.16 and 2.15 are coupled to the input terminal 26 of the current mirror circuit 25 by appropriately controlling the switches 16.1 to 16. 2.18 emitter currents are coupled to output terminals 27 and 28, respectively.

The sum of the emitter currents of transistors 2.17, 2.16 and 2.15 is made to be exactly equal to 41°.

This is why the current is reflected correctly. and 8th construction. appears at the output terminals I11 and 27 and 28. These correctly reflected currents also result in incorrect currents and transmitter currents for transistors 2.14 and 2.18. and 8th construction.

Compare with. The difference current between these currents is also detected by the detection circuits 81 and 8.
2 into logic signals, and these logic signals are input to the 15 input terminals 14.54 of the counting circuits 14, 14 and 14.18.
and 14.58. The analog output voltages of D/A converters 14.84 and 14.88 are transferred to transistors 12.
14 and 12.18 gate electrode 18°14 and 18.
18. The sum of the similarly corrected currents constitutes the input current of the current mirror circuit 25 in the next subsequent period. 1. Once all currents have been corrected, a new cycle begins again.

In the same way as described for the first example, it is not necessary to correct all currents in the second example. The reference transistor allows a current equal to a greater current than that corresponding to the least significant bit to be generated. Therefore, in this case only currents that are greater than or equal to this reference current can be corrected.

An eighth example of the current source arrangement according to the present invention will be explained with reference to FIG. In FIG. 8, the same parts as the elements shown in FIG. 2 are designated by the same reference numerals. In this example, the D/A converter 1...converter has 16 transistors 2.1-2.16 with untuned binary weights, example resistances 8.1-8.16, and a resistor 8.17. and a reference transistor 2°17. The common base of these transistors is driven by an amplifier 4 to generate a current at the collector 1' of the transistor 2.17. Make it so that Emitter resistors 8.1 to 8.17 are connected to ground via field effect transistors 12.1 to 12.11. Also, the correction currents supplied to the input terminals 14.41-14.56 are coupled to the gate electrodes 18.1-18.16. Additionally, a switch 6 controlled by a digital person 4'□ power code.
1 to 6.1 to 16 to connect these currents to the ground point or increase S
is supplied to either of the input sides of the device 7. Switch 6.1~6
．． 17 into a current mirror circuit 25 under the control of the control circuit 17.
5 is also coupled to the input terminal 26 and the output terminals 27 and 28 of the transistors 2.1 to 2.1, and in this example these input and output terminals are not coupled to the emitter lines but to the collector lines of the transistors 2.1 to 2.17. When the current mirror circuit 25 is coupled to these collector lines, the operation of the D/A converter 1 is interrupted.In this example, the current mirror circuit 25 is NPN as shown in FIG. Parallel connected PNP) transistors 150-158 instead of transistors
Equipped with. The emitters of these transistors are connected to a common terminal 160 through the same resistors 15rx to 158, respectively, and the +5 front terminals of these transistors are used as positive terminals for power supply. The common bases of transistors 150-158 are coupled to the output side of amplifier 49, and the input side thereof is connected to input terminal 2 of current mirror circuit 25.
Combine with 6. The common base voltage is appropriately controlled by amplifier 49 so that the current at output terminal 115 of permutation circuit 50 is equal to the current at input terminal 26. This permutation circuit 50 transfers the currents at the input terminals 110 to 118 to the output terminals 115 to 118 in accordance with the permutation, so that the currents at the input terminal 26 and output terminals 27 and 28 are correctly adjusted in the ratio l:'・1:2. Make it proportional.

The same ripple components as mentioned above generated at this time can also be removed as p-waves by the capacitors 72, 78 and 74. During the first period of the cycle of the control circuit 17, the input terminal 2 of the current mirror circuit 125 is connected as shown in the drawing.
The current of B is ■. shall be. The difference current between the correct and incorrect collector currents of transistors 2.16 and 2.15 coupled to output terminals 27 and 28 is detected by detection circuits 81 and 82. The outputs of these detection circuits 81, 1-' and 82 are coupled to input terminals 14.56 and 14.55 of a correction circuit, thereby correcting the collector currents of transistors 2.16 and 2.15.

In the next period of the cycle of the control circuit 18, the transistor L
The collector currents 2゛1 (86) of X 7 , 2.16 and 2.15 are coupled together to input terminal 26 and the collector currents of transistors 12゜■4 and 2.18 are coupled to output terminals 2W and 28 respectively. To do this, the collector currents of transistors 2.14 and 2.18 are 4 IO and 8 IO. can be exactly equal to . The input current of the current mirror circuit 25 in the next subsequent period can be configured by the sum of the corrected currents in the same manner. After correcting the collector currents of the transistors 2.1 to 2.16 over a number of cycles, the current mirror circuit 25 is periodically coupled to the D/A converter layer 10 so that the collector currents can be corrected again. The frequency for this purpose is made to depend on the variation of the collector current as a function of time. As described for the first and second examples, it is not necessary to correct all of the currents in this example, but the reference current 15 can be larger than the current corresponding to the least significant bit. 8th
In the example, the resistors 8.1 to 8.17 can also be connected directly to the ground point without intervening the field effect transistors 12.1 to I Ll 6. In this case, the voltage detection D/A converters 14.21 to 14.86'' are provided with current output terminals instead of voltage output terminals, and these output terminals are connected to the emitters of the transistors 2゜1 to 2゜16. The voltage across the associated resistor 8.1-8.16 is therefore increased or decreased by the addition of a correction current, so that the collector current of the associated transistor 2.1-2.16 In addition, when a holding capacitor is provided in place of the correction D/A converter in this eighth example as shown in FIG. 1, the correction circuit 18°2 to 18°1
The output side of 6 is a field effect transistor 12.1.1-12
．． It can be directly connected to the resistors 8.1 to 8.16 without going through the resistor 17.

In the several examples mentioned above, the precision current mirror circuit 25 includes one
If two input terminals and two output terminals are always provided, the two currents are corrected by the control circuit). All currents are corrected in a relatively short time by correcting each period of the cycle. be able to. However, instead of two output terminals, only one output terminal can be provided in the current mirror circuit.

In addition, in the several examples mentioned above, the number of output terminals of the permutation circuit is '□.

is always equal to the number of its input terminals. Zarani I@.

The ratio between the currents at the output terminals of the column circuit was always approximately equal to unity. By adding the currents at the output terminals of this permutation circuit, a current mirror ratio other than 1 can be obtained. In the current mirror circuit according to the present invention, the number of output terminals of the permutation circuit is different from the number of its input terminals, and the number of currents transferred to the output side during one period of the cycle time of the permutation circuit is set to a number other than 1. , the number of currents flowing through each output terminal during one period of cycle time can be made different. Furthermore, the current mirror times 1
(One path of transistors can also be selectively activated.

A fourth example of the current source arrangement according to the invention will be explained with reference to FIG. The current source arrangement of this example comprises eight 16-bit D/A converters 210, 220 and 280'' shown diagrammatically, and these D/A
The A converter is constructed in the same manner as the D/A converter 1 shown in FIG. 2, for example. A precision current mirror constituted by a 1:1:2 current mirror circuit, for example as shown in FIG. 2, by a coupling network 240 controlled by a control circuit 250.

- together with the circuit 260 and the detection circuit 270, the lD/
Allows the currents from A converters 210, 220 and 280 to be corrected. In this example, the current mirror circuit 260 allows the D/A converters 210, 220, and 280 to be corrected at low frequencies.
D/A converter 210,2 in one cycle time of 60
This is because the current fluctuations from 20 and 280 are slight.

The invention described above has been described for use with a D/A converter. However, the invention is not limited to such D/A converters, but can be used in any circuit arrangement requiring multiple currents in precise mutual ratios. An example of obtaining a large number of identical currents will be explained with reference to FIG. In FIG. 5, the same parts as the elements shown in FIG. 1 are denoted by the same reference numerals. In this example, section 1 is constructed in the same manner as described with respect to FIG. 1, but with transistors 2.1
~2.16 emitter area and emitter resistance 8.1~
The only difference is that 8.16 are not constructed in binary form, but are approximately equal to each other. Also, the co-lefter lines of the transistors are coupled to other circuits (not shown) included in the integrated circuit at 1 that are not coupled to the input side of the summing amplifier.The emitter currents of transistors 2.1 to 2.16 are current mirrored The current mirror 5 is coupled to the input terminal 26 of the circuit 25 and in this example via the coupling network 15 to one output terminal 2 of the circuit 25.
Combine with 7. During the following period, the control circuit 17 controls the switches 16.1 to 16.16 accordingly so that one emitter current can be compared in each case with the reference emitter current of the transistor 2.1. This current mirror circuit 2510 has two emitter resistors 802 and 808.
transistors 800 and 801. The common base of these transistors is driven by an amplifier 49,
The input terminal of this amplifier 49 is connected to the input terminal 26 of the current circuit. The permutation circuit 50'' has its input terminal 80.
5 and 806 are transferred to output terminals 807 and 808 according to a cyclic permutation so that exactly equal currents appear at input terminal 26 and output terminal 27. The current difference between the accurately reflected current of the transistor 2.2 and the inaccurate emitter 2° current is detected by the detection circuit 81, and this charges the capacitor 20 so that the emitter current is corrected. do. In the next subsequent period, each of the currents from transistors 2.8 to 2.16 is transferred to transistor 2.
Compare and supplement with the reference current from ゜1.

Make it correct.

The present invention is not limited only to the examples described above, but can be modified in many ways. For example, in the above-described step, the P-channel junction field effect transistor 12
P-111MOS transistors can be used instead of ゜1-1117, and NPN transistors 2.1-2
．． 16 can be replaced by an N-channel junction field effect transistor or an N-MOS transistor. In addition, complementary PN transistors are used as transistors 2.1 to 2.16.
P-channel junction field effect transistors and P-MOS transistors can be used as P transistors 15, and N as transistors 12.1 to 12.17.
Channel junction field effect transistor and N-MO
An S transistor can be used. Similar thing 2υ
can be applied to other transistors in the circuit. For example, in the above-described step, a field effect transistor can be used as a current source transistor, and a bipolar transistor can be used to control the current from the current source transistor, and various changes can also be made to the detection circuit and correction circuit. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first example of the current source arrangement according to the invention in the form of a digital-to-analog converter, and FIG. 2 is a circuit diagram showing a second example of the current source arrangement according to the invention in the form of a digital-to-analog converter. 8 is a circuit diagram showing an eighth example of the current source arrangement of the present invention in the form of a digital-to-analog converter, and FIG. 4 is a circuit diagram showing the fourth example of the current source arrangement of the present invention in the form of a digital-to-analog converter. The block diagram shown in FIG. 5 is a circuit diagram showing a fifth example of the current source arrangement of the present invention. 1, 210.220.280...D/A converter 2.1
~2.17th...Transistor 2
08.1~8.17...Unfine adjustment resistor 4...Operation amplifier 5...Current source 6.1~6
．． 16...Switch? ...Amplifier 8...Feedback resistor 9...Output terminal 12°1-12°17...N-channel field effect transistor 18.1-18°17...Gate electrode 14.
1 to 14.16... Counting circuit 14.21 to 14.86... D/A converter 14.41
~14.56...Input terminal 15, C0...Coupling circuit network 16.1-16.17...Switch 1F, 250...Control circuit 18.2-18.16...Correction Circuit 19.2. io, a...Amplifier 20・ノ2.2
0.8...Capacitor 15B1.2.21.8...
Capacitor 22.1! ! , 2B, 8...Switch 28.2.
28.8・IQ switch, 2~24°16...Input terminal 25...Current mirror circuit 26...Input terminal (2
6) i117.28...output terminal (gs)
l1l(44) 8ON88,100~108,150~158. 80
0. 801... 1 parallel connected transistors 40 to 46. 104 ~ lOfu, 155 ~ 158
．． 81. 808...Resistor 4F, 108.160...Common terminal 49...Amplifier 50...Permutation circuit 51-57.110
~118.805.806...Input terminal (50) 61
~67, 115~118180? ', 808Φ...Output terminal (50) 70, 2flO...Control circuit 71...Clock signal generator 72, F8, 74...Filter capacitor 80, 27
0...Detection circuit 81.82...Current-voltage converter 88, 86...Operation amplifier 84, 87...Feedback capacitor 85, 88
...Output terminal (80) 89, 90...Reset switch 91, 92...Switch 120, IJI...Comparator.

Claims (1)

[Scope of Claims] L Means for generating a plurality of currents in which at least a pair of current ratios is approximately equal to a predetermined current ratio, and at least a plurality of current values for obtaining the predetermined current ratio. In a current source arrangement comprising means for detecting a deviation from a required current value and means for correcting said current to reduce the detected deviation, the means for detecting a deviation in said current value comprises: a precision current mirror circuit having 10 input terminals and at least one output terminal at which a current of a value appears in the correct proportion to the current of the input terminal; a coupling network for cyclically coupling at least a number of the currents from the means for cyclically coupling to an input terminal and at least one output terminal of said 15 current mirror circuit; a plurality of currents from means for generating a plurality of currents provided and coupled to said output side and said two currents appearing at said output side;
- A current source arrangement characterized in that it comprises a detection circuit for detecting a difference current between the currents from the current mirror circuit. A current mirror circuit comprises a current distribution circuit comprising a plurality of transistors having parallel connected main current paths and a common control electrode driven by an amplifier whose input side is coupled to the input side of the current mirror circuit; 1.) A circuit for transferring current from a circuit to an input terminal and at least one output terminal of the current mirror circuit according to a cyclic permutation. Source placement. & Current source arrangement according to claim 1 or 2, characterized in that each detection circuit comprises a first current-to-voltage converter. Table Each first current-to-voltage converter has a first input terminal coupled to an associated output terminal of the current mirror circuit, a second input terminal coupled to a reference voltage point, and an output terminal connected to said first current-to-voltage converter via a feedback capacitor. Claim 8, item 1, characterized in that it comprises an amplifier coupled to the input terminal.
Current source arrangement shown. 5. A patent & means for correcting predistribution current characterized in that the output terminal of the amplifier is coupled to the first input terminal of the comparator, and the second input terminal of the comparator is coupled to the reference voltage point. , a second current-to-voltage converter associated with each current to be corrected, the second current-to-voltage converter including an amplifier having an output terminal coupled to the first input terminal via a feedback capacitor. 5. A current source arrangement according to claim 8, characterized in that the first power terminal can be coupled to the output side of the first current-to-voltage converter via a switching capacitor. 7. The means for correcting the currents comprises a counting circuit associated with each current to be corrected, said counting circuit being able to be coupled via a switch to the output of said current-to-voltage converter and by means of said counting circuit. A plurality of logic signals are generated depending on the logic signal at the output side of the comparator, and these logic signals are converted into an analog output signal by a digital-to-analog converter, and the associated current is controlled by this output signal. Claim 5 characterized in that it is amended.
・Current single source arrangement as described in section. & The means for generating the plurality of currents comprises means for generating at least one type of plurality of currents whose values vary according to a binary weighted series.
The current source arrangement according to any one of Items to Item 7, Item 1.}. 9. A current source arrangement according to any one of claims 1 to 7, characterized in that the means for generating a plurality of currents comprises means for generating a plurality of currents of approximately equal current values. 10. means for generating a plurality of currents each coupled to a main current path of a respective first transistor extending between the first and second main terminals and to the first main terminal of the associated first transistor; a plurality of parallel branches having a resistor, connecting at least one output terminal and one input terminal of the current mirror 2'1(8) one circuit to the second main terminal or one of the resistors through a coupling network; The first transistor of the current source section/resistor according to claim 8 or 9, wherein the first transistor is coupled to an end portion on the opposite side of the first transistor. At the opposite end, at least a number of the parallel branches are arranged with main current paths of field-effect transistors, and the main current paths are arranged between the respective first and first (z main terminals). 10. A current source arrangement according to claim 10, characterized in that the current source arrangement is configured such that at least one output terminal and an input terminal of the current mirror circuit are connected to a field effect transistor via a coupling circuit network. 12. A current source arrangement according to claim 11, characterized in that the current source is coupled to the second main terminal of the I transistor. 1& The output terminal of the correction means is coupled to the gate electrode of the field effect transistor. A current source arrangement according to claim 11 or claim 121, characterized in that...