JPS63163657A - Dma transfer system - Google Patents

Abstract

PURPOSE:To prevent the performance of a system from being lowered by evading the occupancy of a system bus by a DMA controller at the time of transferring a data to a laser beam printer, by using a dual port memory as a printer image buffer. CONSTITUTION:An interface circuit is constituted of the dual port memory 15, and a function as the buffer memory of the laser beam printer is provided. In such a way, by operating the circuit asynchronously with the transfer rate of the laser beam printer, and also, enabling the content of the dual port memory 15 to be updated even during a time of outputting the data to the laser beam printer, the occupancy of the system bus 6 by the DMA controller 14 for a long time can be evaded at the time of transferring a DMA data from an image memory 3 to the dual port memory 15.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention relates to a DMA (direct memory access) transfer system, and more specifically, the present invention relates to a DMA (direct memory access) transfer system, and more specifically, a method for storing an image to be output to a laser beam printer (hereinafter abbreviated as LBP) in an image memory in bitmap format. Regarding the system in which the image data is DMA transferred to the LBP using the direct memory access controller after creating the above, especially the L
The aim is to improve the BP interface circuit and improve system performance.

[Prior Art] An example of a conventional system having an LBP interface circuit is shown in FIG. In the figure, 1 is a central processing unit (CPU) that manages the entire system, 2 is a DMA controller, 3 is an image memory, 4 is an LBP interface circuit, 5 is an LBP, and 6 is a system bus. C
PU1. The DMA controller 2, image memory 3, and LBP interface circuit 4 are connected to a system bus 6 so that commands and data can be exchanged.

In such a system, when outputting an image to the LBP 5, the image to be output is first created in bitmap format on the image memory, the 9DMA controller 2 is activated, and the image data is transferred to the interface circuit 4 of the LBP.

The interface circuit 4 is equipped with a parallel/serial conversion circuit, which converts the image data received from the image memory 3 into serial data and serializes it.
, and is transferred to LBP5 at a constant rate defined by LBP.

[Problems to be Solved by the Invention] However, in such an MA transfer system, the transfer rate increases dramatically when a high-resolution, high-speed output LBP is used, so the DMA controller 2 is unable to transfer image data. The system bus 6 will be exclusively used for this purpose. In other words, the transfer speed of the DMA controller 2 has a capacity of about 2 to 3 times the output speed of the LBP, but in order to always maintain a constant transfer rate for the LBP 6, the DMA controller 2 needs to control the system bus 6. It has to be exclusive.

In other words, during the period of output to the LBP, the functions of devices other than the DMA controller (such as the CPU) are completely stopped, resulting in a disadvantage that system performance deteriorates.

The present invention has been made in view of the above points, and is based on the LB
A DMA controller that prevents the DMA controller from monopolizing the system bus when transferring data to the P, thereby preventing deterioration in system performance.
Ii is to provide an infeed system.

[Means for Solving the Problems] In order to achieve such an object, the present invention transfers image data created on an image memory to an interface circuit of a laser beam printer by DMA, and transfers the image data in the interface circuit. In a DMA transfer system that converts data from parallel to serial and outputs it to a laser beam printer at a specified constant rate, the interface circuit is configured with dual port memory and has the function of a buffer memory for the laser beam printer. It is characterized by

[Function] In the present invention, by implementing the interface circuit with a dual port memory, the interface circuit can be operated asynchronously with the transfer rate of the laser beam printer, and the contents of the dual port memory can be updated even while data is being output to the laser beam printer. When performing DMA data transfer from image memory to dual-port memory, the DMA
The controller was prevented from monopolizing the system bus for a long time.

[Example code] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of main parts showing an embodiment of a DMA 112 transmission system according to the present invention. In the figure, the same parts as in FIG. 8 are given the same reference numerals, and their explanation will be omitted. The system bus 6 is composed of an address bus 61 and a data bus 62. 10 is LB with dual port memory
This is a P interface circuit, the details of which are shown in FIG.

In FIG. 2, 11 is an interface controller that communicates the operating status of each part in the interface circuit to the CPU via the system bus 6 and controls each part according to instructions from the CPUI, and 12 reads data from the dual port memory. 13 is a multiplexer for switching the bus connecting the dynamic random access memory controller 1 to the controller 14 (hereinafter dynamic random access memory is abbreviated as DRAM), which is under the control of the interface controller 11. It is switched to either the address bus 61 of the system bus or the output bus of the address counter 12.

DRAM controller 14 is dual port memory 15
control. Control signals include RAS and CAS signals as memory addresses, and a WR multiplication signal that instructs writing or reading.

Write data to the dual port memory 15 is given from the data bus 62 of the system bus, and read data is given as parallel data (16 bits) from a serial port (not shown) in the dual port memory to the parallel/serial converter 1.
6 is output.

Dual port memory functions as a buffer memory for LBP and has a storage capacity of typically 128 to 409 bytes.
Image data of 6 dots x 256 dots can be stored. For example, when outputting to A4 size BP paper, the width of the paper is 8°2 inches, so the width is 4096/8.
．． This means that any LBP with a resolution of 2=500 dots/inch or less can be handled.

Data (16 bits) from the serial port of the dual port memory in the interface circuit 10 is converted into serial data by the parallel/serial converter 16 and sent to the LBP 5.

A timing controller 17 is controlled by the interface controller 11 and generates timing for reading LBP output data from the dual port memory 15 based on a synchronization signal from the LBP 5.

The operation in such a configuration will be explained next.

The entire system is managed by CPUI. As shown in FIG. 3, after creating a one-page LBP image 31 on the image memory 3, the DMA controller 2 is started and the LBP image 31 is transferred to the dual port memory 15 via the system bus 6.
line (the width is the width when outputting LBP, but
(depending on the resolution) is transferred by DMA.

Data transfer is based on the following operations. DMA controller 1-roller 2
A command is given to the interface controller 11 to operate the multiplexer 13.

A DRAM controller 14 is connected to the system bus side. DRAM controller 14 is dual port memory 1
Address and write signals are given to 5. Write data is provided from the image memory 3 to the dual port memory 15 via the data bus 62.

After the data is transferred in this way, CPU1
Pprint DR start command is generated (printer start). As a result, the multiplexer 13 switches the bus connection,
The output of the address counter 12 is transferred to the DRAM controller 1.
Connect to 4.

In the mode of reading LBP output data, LB
The address counter 12 counts up due to the horizontal synchronization signal from P6, and the data for one line pointed to by that address is stored in the dual port memory 15 as shown in figure fJ4.
is transferred to the built-in serial port inside the . The serial board has 16 ports of 256Xl bits, and the clock given by the timing controller 17 (the dot clock required to send one dot at a time to the LBP divided by 1/16) is used to control the clock from each port. Data is read out bit by bit.

The 16-bit data read from each port is processed in parallel.
The serial converter 16 converts the data into serial data (print data) bit by bit, and sends it to the LBP 6.

When the data output for 1128 lines (the upper half of the data in the dual port memory) is finished, the timing controller 17 starts address counter 1.
2 and CP via interface controller 11
Outputs a printer image transfer request to the UI. C.P.
When the UI receives the request, it issues a transfer command to the DMA controller 2. The area to be transferred at this time is a continuation of 5 printer images, that is, 257 areas as shown in Figure 5.
128 lines from line to 1 part of dual port memory
Transfer to the upper half of 5.

In addition, even during transfer, the lower half of the dual port memory 15 continues to be output to the LBP 6, and when the data is output after &, the address counter 12 is configured so that the output data to the next LBP becomes the start address of the dual port memory again. Specify the address.

At this time, a transfer request is issued to the CPUI.

As a result, the DMA controller 2 transfers the continuation of the printer image, that is, 385 lines to 128 lines, to the lower half of the dual port memory. Note that the DMA controller 2 transfers data to the dual port memory via DMA.
When transferring, the multiplexer switches the bus connection to the system bus side.

Thereafter, by repeating the transfer and output of each 128 lines in the same manner, the entire page is output to the printer.

If there are two or more pages to be output to the LBP, the operations described above are repeated.

[Effects of the Invention] As described above in detail, the present invention has the following effects.

By using a dual port memory as a printer image buffer, the DMA controller can almost freely access the memory even during data transfer to the LBP. Reading the LBP output data requires only one access per line, and the time required for this is less than 0.1% of the total output time. Therefore, the DMA controller can access image data without being subject to memory access restrictions due to LBP output.

In addition, since the transfer speed of the DMA controller generally exceeds the LBP output speed, the difference in speed can be used by other devices (
This is provided as time when the CPU (such as the CPU) can work, contributing to improving the performance of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts showing an embodiment of a DMA transfer system according to the present invention, FIG. 2 is a specific block diagram of an interface circuit, and FIG. 3 explains the data area of each memory and the state of transfer. Explanatory diagram: Figure 4 is an explanatory diagram explaining how data is transferred in the dual port memory, Figure 5 is a diagram showing a ladder of data transfer from image memory to dual port memory, and Figure 6 is a conventional DMA transfer. FIG. 1 is a configuration diagram showing an example of a system. 1...CPU, 2...DMA controller, 3...
- Image memory, 5... LBP, 6... System bus, 61... Address bus, 62... Data bus, 1o... Interface circuit, 11... Interface controller, 12... Address Counter, 13... Multiplexer, 14... DRAM controller, 15... Dual port memory, 16...
- Parallel/serial converter, 17... timing controller. Figure 1 A'Z -11,-''

Claims (1)

[Claims] The image data created on the image memory is transferred by DMA to the interface circuit of the laser beam printer, and the interface circuit converts the image data from parallel to serial and outputs it to the laser beam printer at a specified constant rate. In the DMA transfer system, the interface circuit is configured with a dual port memory, has a function as a buffer memory of the laser beam printer, operates asynchronously with the transfer rate of the laser beam printer, and has a dual port memory function. 1. A DMA transfer system characterized in that the content of a dual port memory can be updated even while data is being output to a DMA transfer system.