JPS63163519A - Constant current circuit with starting circuit - Google Patents

Abstract

PURPOSE:To quickly reach a stable operation state by connecting a starting MOS transistor TR between the gate of a MOS TR for constant current circuit operated in a weak inversion area and a prescribed power supply node. CONSTITUTION:In case of switching from the stand-by state to the operation state, a reset signal is inputted after switching from '1' to '0'. When kick pulse signal input K1 goes to active level '1', an N-channel TR TN4 is turned on connected as a starting circuit and the level of a node N1 falls and P-channel TRs TP1 and TP2 are turned on. Then, the level of the drain (a node N3) of the P-channel TR TP1 goes to '1' and N-channel TRs TN1 and TN2 are turned on. Though the kick signal input goes to non-active level '0' in this state, the circuit surely and quickly reaches the stable state of circuit operation from turning-on states of TRs TP1, TP2, TN1, and TN2.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention relates to a constant current circuit provided in a semiconductor integrated circuit, and in particular to a constant current circuit using complementary MO8 (insulated dart type) transistors. Regarding a constant current circuit with a starting circuit.

(Prior Art) An example of a constant current circuit that has been widely used as a basic circuit for constant voltage generation circuits, high gain buffer circuits, etc. in integrated circuits is described in Japanese Patent Laid-Open No. 56-2017. An example of using the weak-in-purge W/area is shown in FIG. Here, T and TP2 are P-channel transistors operating in the weak inversion (strong inversion) region, T and T9 are N-channel transistors, R is a resistor, and LD is a load. , a mirror circuit NI consisting of transistors T , T , T
N2 N.

A constant current is passed through the load LD through the circuit.

When the above constant current circuit is actually used, a circuit is often added to control the current flow (through current path) during standby, and an example of this is shown in Figure 8. There is. Here, "P5 is a P-channel transistor connected between the VDD' BL source node and the dirt (node N, ) of the P-channel transistor TP2, and T93 is the dirt (node N2) of the N-channel transistor TN2 and the vslI The control input (reset input) is applied to the gate of the N-channel transistor TN3, and is inverted by the CMOS inverter INV to the P-channel transistor Tps. is given to the dart.

In FIG. 8, the same parts as in FIG. 7 are given the same reference numerals.

In the circuit shown in FIG. 8 above, during standby, the control input is at the 11# (high) level, the P-channel transistor TP3 and the N-channel transistor TEN3 are turned on, and the node N, Vi'''1# level, and the node Since N2 becomes 10 Level, the transistors TPI I TP21 TNl 1 TN2 of the constant current circuit are turned off.When the constant current operation starts, each of the above transistors Tp1
Since m Tp2 * TNt * TN2 is in the off state, even if the control input goes from "11" to "10" level, leakage current initially flows through the nodes N, , N2.
The parasitic capacitance of is discharged or charged and moves toward a stable point, and when the voltage at each node N11 N2 reaches a certain level, the operating point is in the weak inversion region.
The circuit condition becomes stable.

However, at the start of the above operation, the voltage at each node N, , N2 changes only gradually due to a weak leakage current, so it takes a long time for the circuit operation to reach a stable state (
For example, the threshold voltage of the transistor or V. Since variations in kana occur depending on the D power supply voltage, there is a problem in actual use.

(Problems to be Solved by the Invention) The present invention has been made in order to solve the above-mentioned problem that the time required to reach a stable operating state from a standby state becomes long and varies. It is an object of the present invention to provide a constant current circuit with a starting circuit that can quickly reach a certain state.

[Configuration of the Invention (Means for Solving the Problems)] The constant current circuit with a starting circuit of the present invention connects the r-t of an MO8 transistor for a constant current circuit operating in a weak inversion region and a predetermined power supply node. When starting the constant current circuit, connect the starting MO8 transistor between
The present invention is characterized in that a pulse-like starting signal is applied to the r-gate of the O8 transistor to turn it on, and the above-mentioned constant is used to temporarily turn on the flow circuit MOS transistor.

(Function) Even if the constant current circuit is once turned on by the starting transistor and then turned off, the constant current circuit will reliably and quickly reach the stable operating state from the above-mentioned on state. become.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In the constant current circuit with starting circuit shown in Figure 8g1, vD
D power supply node and V. A P-channel transistor T'p, a resistive element R, and an N-channel transistor TN are connected in series between the power supply node and a nine P-channel transistor TP2 with the dirt and drain connected together.
and an N-channel transistor TN2 are connected in series. The drain of the P-channel transistor TP and the dart of the N-channel transistor TN1 are connected,
The darts of P-channel transistors T and T,2 are connected together, and the drain of N-channel transistor TN1 and the gate of N-channel transistor TN2 are connected.
ing. These form a constant current circuit body.

A P-channel transistor TP5 and an N-channel transistor TN5 serve as a standby/operating state control circuit.
and a CMOS inverter INV are added. That is, vDD\IL source node and P channel controller/distor TP
P-channel transistor TP5 is connected between fl and N-channel transistor T (node N1) of No. 2 (node N1).
An Nf channel transistor TN3 is connected between the gate of N2 (node N2) and the Vast source node, and a control signal (reset signal) input node is connected to the r-to of the N-channel transistor TN3, and the CMOS inverter INV. via the P-channel transistor T,2
It is connected to the dart.

Furthermore, as a starting circuit, the P channel of the constant current circuit main body, the pace C node N of the 7-noister TP2, ) and v
l! , 'rt source node, and an N-channel transistor TN4 is connected between the N-channel transistor TN4 and the starting signal (kick signal) input node. Note that each of the transistors described above is an enhancement type Mos transistor, and the resistance element R uses a diffused resistance or a polysilicon resistance.

Next, the operation of the above circuit will be explained with reference to FIG. The steady operation and standby state in this circuit are the same as in the conventional example, but when moving from the standby state to the operating state, after the reset signal input changes from 11" to θ", 1 is given to the pulsed kick signal input. . However, when the kick signal input becomes active level 11'', N
Channel 2 transistor TN4 is turned off and node N1
When the level of υ is lower, P channel transnostar Tp, +T
p□ turns on. Then, P channel tra/sosta T
The level of the drain of P1 (node N3) is 11#)
, N-channel transistors T , T turn on NI
N2 becomes. In this way, the basic transistor T□.

Even if the key pin signal input becomes inactive level ("o" level) with T, T, and T all turned on, the circuit operation will not start from the on state of the transistor Tl"P21TN1'N2. Reliably reach a stable state.

And it quickly reaches this point (in several tens of microseconds, as a result of 5PICE simulation). Moreover, the time required to reach the above-mentioned stable state hardly depends on the vDD power supply voltage or the threshold voltage of the transistor, and the variation is very small.

FIG. 2 shows another embodiment, in which two N-channel transistors T are used as a starting circuit, compared to the circuit shown in FIG.
, T are connected in parallel and each N4
NS: 2 and Kj are input to different kick signals for each dart, and the runner-up is different, but other parts are the same and are given the same reference numerals as in FIG. 1.

Here, the dimension (channel@/channel ratio) W, /L of the transistor T84 and the transistor TN
5 dimension W2/L2, i.e. W1/L, <W2/L2 or W,/L.

) W2/L, 2. Now, if W1/L1 (W2/L2, transistor TN4
2 and transistor T8 for the kick signal input to the dirt of
The kick signal input to the dart of 3 becomes active level @ 1''' at the same timing as shown in Figure 5. Alternatively, as shown in Figure 6, the kick signal of 3 becomes the active level @1''' than the kick signal of 2 as shown in Figure 6. Yoshi also becomes @1'' first, but the kick signal of 3 returns to the inactive level (i) the kick signal returns to the inactive level (in other words, the kick signal of 2 is faster than the kick signal of 3). The screen is also set so that the width of the screen is long).

In addition, the transistor T85 with a larger dimension
are 1cP channel transnostars T and T when they are on.
Its W2/L7E is set so that it has sufficient driving capability to lower the level of node N until pl p2 turns on. On the other hand, the transistor TN4, which has a smaller dimension, has a relatively small value W, /L, so that a small current flows for a certain period of time even after the other transistor TN5 turns off first. is set to .

Next, FIG. 5 shows the startup operation of the circuit shown in FIG. 2 above.

This will be explained with reference to FIG. When transitioning from the standby state to the operating state, the reset signal input changes to the "1" level or the "O" level.2. 3 becomes active level 11". This causes N-channel transistors TN4 and TN5 to turn on simultaneously or sequentially, and the level of node N is forcibly lowered, turning on P-channel transistors T and T. Then, a large current n flows through the PI F2 resistance element R, and the voltage drop [j#
) Node N3 is at @11 level, and N-channel transistor TN1 is turned on, so node N2 becomes "O" level. Next, temporarily set the kick signal input to 2. 3 become inactive level 10'', the above node N2
N-channel transistor TN
2 is turned off, the node N is instantaneously at the ``1'' level, the P-channel transistors T and T are turned off, current no longer flows through the resistor R, and the node N3 is @ 0″, Note N2 is also IlO
″), in the end, all transistors Tp 1 * T
p 21 TN 1 'TN2 is turned off.

Next, avoid this.

First of all, after the kick signal became 3 @0”.

For a certain period of time, leave '2' to 1'' in the kick signal manually.N
A small current is passed through the channel transistor TEN4,
The process waits until the level of each of the nodes N, , N, , N2 becomes relatively close to a stable point.

In this state, only a small current flows through the resistance element R, and the nodes N and N2 are connected to the intermediate V
1ll (7i) transistor T, T
.

PI F2 TN4. TN2 is in the on state. And even if the kick signal becomes @0'' at the point when each node N, , N, , N1 reaches a level relatively close to the stable point.

The transistors T 1 , T 2 , T 2 , and T 2 can reach a stable state of circuit operation from the ON PIF2 1 N2 state reliably and quickly.

Note that in the circuit shown in FIG. 2 above, W, /L, )N2
/ In the case of L2, the same operation as in the above embodiment can be achieved by inputting 3 as the kick signal to the dart of the N-channel transistor TN4 and inputting 2 as the kick signal to the dart of the N-channel transistor TN5. is obtained.

FIG. 3 shows yet another embodiment, in which, compared to the circuit shown in FIG. However, since the other parts are the same, they are given the same reference numerals as in Fig. 1.The capacitors C1 and C2 are
A semiconductor substrate, a gate insulating film, and a first layer Al (such as silicon) are used.

It can be formed by using a first layer wiring (polysilicon or the like), an interlayer insulating film, and a second layer wiring (polysilicon or the like) on a semiconductor substrate. The circuit shown in Figure 3 above includes a fourth
1 is given to the kick signal at the timing shown in the figure. Even if the kick signal is changed from 1" to "0" and the N-channel transistor N4 changes from on to off at the same time, no 1 is given. 'N, N2 level is capacitor C1,
The action of C2 prevents it from passing through the stable point.

Note that the P-channel transistor in each of the above embodiments,
The N-channel transistors are changed to N-channel transistors and P-channel transistors of opposite conductivity type, respectively, and v
DD'IL source node and V8. *If the constant current circuit with a starting circuit is configured by changing the source node to be reversed, the same effect as in the above embodiment can be obtained.

[Effects of the Invention] As described above, the constant current circuit with a starting circuit of the present invention can quickly reach a stable operating state upon starting, and is therefore extremely effective in actual use.

[Brief explanation of the drawing]

1 to 3 are circuit diagrams showing different embodiments of a constant current circuit with a starting circuit according to the present invention. 4 is a timing signal diagram showing an example of the operation of the circuit in FIG. 1 and the circuit in FIG. 3, and FIGS. 5 and 6 are timing signal diagrams showing different operation examples of the circuit in FIG. 2, respectively. ,
Fig. 7 is a circuit diagram showing an example of a constant current circuit using a weak impurge four region, and Fig. 8 is a circuit diagram showing a standby/operating state control circuit added to the circuit of Fig. 7. . T, T...P channel transistor, TNl
DPI F2 TN21 TN5' TN41 TN5...N channel transistor, R...resistance element. Patent attorney Takehiko Suzu

Claims (1)

[Claims] A first MOS transistor and a resistance element of a first conductivity type are connected between the first power supply node and the second power supply node, and a second MOS transistor of a second conductivity type which is a conductivity type opposite to the first conductivity type is provided.
S transistors are connected in series, the gate of the second MOS transistor and the drain of the first MOS transistor are connected, and a first conductivity type transistor is connected between the first power supply node and the second power supply node. A third MOS transistor and a fourth MOS transistor of the second conductivity type are connected in series, the gate and drain of the third MOS transistor are connected to the gate of the first MOS transistor, and the fourth MOS transistor is connected in series. a gate of the MOS transistor is connected to the gate of the second MOS transistor; a fifth MOS transistor of the first conductivity type is connected between the first power supply node and the gate of the third MOS transistor; A sixth MOS transistor of a second conductivity type is connected between the gate of the fourth MOS transistor and the second power supply node, and is complementary to the gate of the sixth MOS transistor and the gate of the fifth MOS transistor. to provide a standby/operating state control signal,
A seventh MOS transistor of a second conductivity type is connected between the gate of the third MOS transistor and the second power supply node, and a pulse-like activation is applied to the gate of the seventh MOS transistor when the constant current circuit is activated. A constant current circuit with a starting circuit, which is configured to give a signal.