JPS63163502A - Multiplexer - Google Patents

Abstract

PURPOSE:To reduce the number of modules required for multiplexing switching by storing a signal line group for multiplexing switching in a connection cable to a line terminating set and independently controlling switching by each line interface module in accordance with signal states of this signal line group. CONSTITUTION:Transmission/reception signal lines to a DSU (line terminating set) 3 are connected in parallel to multiplexed LIFs (line interface modules) 10a and 10b and switching control signal line groups with which states of LIFs 10a and 10b are monitored by each other are stored in a cable 11, and the non-operating LIF is the reception side to execute acquisition of synchronism, detection of reception signal break, or the like, and the transmission signal is checked even in the transmission side. In this case, terminating resistances of transmission/reception signal lines to the DSU 3 are switched by signal states on switching control signal line groups so that the transmission signal and the reception signal are not outputted to busses in the DSU 3 and a multiplexer. Thus, the number of modules required for switching is reduced to shorten the time required for the stable operation after switching, and automatic switching is possible to facilitate the control.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to automatic switching from a failed module to a normal module in a multiplexing device configured redundantly with a plurality of modules.

[Conventional technology]

FIG. 5 is a configuration diagram showing a conventional multiplexing device. In the figure, 1 is a multiplexing device, 2a and 2b are line interface modules (hereinafter referred to as LIF), and 3 is a line termination unit (hereinafter referred to as DSU). , 4a+4b are cables, 5 is a changeover switch module connected to the LIFs 2a and 2b by these cables 4B and 4blC, 6 is a connection cable that connects this changeover switch module 5 and the DSU 3, 7 is a control module, and 101 is this control The signal line 102 is for the module 7 to control the changeover switch module 5, and the signal line 102 is for the control module 7 to control the LIF.
Signal line for controlling 2a and 2b, 103 is DSU
This is a bus for transferring input/output signals with 3 and for supplying internal clocks.

Next, the operation will be explained. Changeover switch module 5
Depending on the connection direction of the switch SW in the LIF 2, signals sent and received from the DSU 3 are sent to and received from either the LIF 2al or the LIF 2b.

The figure shows a state where it is connected to LIF2a. The control module 7 controls switching of the switch SW of the changeover switch module 5 and which of the LIFs 2a and lb is in operation, and the signal line 1
Alarm information (for example, D
The above-mentioned switching is controlled while monitoring the reception signal disconnection from SU3, transmission signal disconnection from LIF 2a or 2b, loss of frame synchronization, input disconnection from changeover switch module 5, etc.

In FIG. 5, the received signal from the DSU 3 is sent to the LIF 2a via the connection cable 6, changeover switch module 5, and cable 4a, and output to the bus 103. Further, the transmission signal from the bus 103 is sent to the DSU 3 through the reverse route. The LIF 2b receives the transmission signal from the bus 103 during non-operation, but does not output it to the bus 103.

In the above state, the control module 1 at the LIF 2a,
When it is detected that the input from the changeover switch module 5 has been disconnected, the alarm information of the changeover switch 7 joule 5 is monitored via the signal line 101, and it is checked whether the input from the DSU 3 has been disconnected. If not, LIF2
A is brought into a non-operating state, switch SW in the selector switch 7 Joule 5 is switched to connect it to LIF2b, and LIF2b is brought into an operating state.

[Problem that the invention seeks to solve]

Since the conventional multiplexing device is configured as described above,
There are many connection points for modules for switching control, and failures such as breakdowns, unexpected cable disconnections, and poor connection of cable connectors are likely to occur.Also, the amount of hardware is large, which not only increases costs, but also increases the risk of failures such as failures, unexpected cable disconnections, and poor connection of cable connectors. Since all the signal lines connected to the DSU are disconnected from the LIF, the reception signal from the DSU is not input, and after the LIF is switched to the operating state, it performs synchronous pull-in, and then returns to normal operation, so there is no need for switching. It takes a long time, and it is difficult to synchronize because switching of the switch SW in the changeover switch module and switching of the LIF are performed at the same time.This switching is centrally controlled by the control module, so if the control module fails, the switching will not occur. Control becomes impossible, and even if there is an abnormality only on the receiving or transmitting side, both transmitting and receiving will be switched, so the switching may cause loss of bit information even on the normal side. One LIF
If an abnormality occurs only in the transmitting system in one LIF and only in the receiving system in the other LIF, there are various problems in the duplex system, such as communication being cut off.

This invention was made to solve the above-mentioned problems, and it reduces the number of modules required for switching as much as possible, shortens the time from switching to stable operation, and enables automatic switching and control. In the multiplexing device according to the present invention, transmission/reception signal lines to and from the DSU are connected in parallel to each multiplexed LIF, and each LIF is connected to another LIF.
A switching control signal line group for monitoring the status of the IF is housed in the above cable, and when the LIF is not in operation, the reception side executes synchronization pull-in and reception signal disconnection detection, and the transmission side also performs the transmission signal line group. However, do not output transmit signals or receive signals to the bus in the DSU or multiplexer, and set the terminal resistance of the transmit/receive signal lines to and from the DSU according to the signal state on the switching control signal line group. For each of the multiplexed LIF's transmitting system and receiving system, when the other LIF's is not operating or in an abnormal state, the own LIF's own LIF is switched to operating if it is normal. with each LI
When both the transmitting and receiving systems of F are in a normal state, prevent the same system from being in operation at the same time, and if an abnormality occurs in the transmitting system or receiving system of the own LIF such as receiving signal disconnection or loss of synchronization, that system is not in operation, and each LI
The status of each group of F is always output on the switching control signal line.

[For production]

In the multiplexing device of the present invention, the received signal from the DSU and the transmitted signal and clock from the internal bus are constantly input to the LIF, so even when it is not in operation, synchronization such as 7-rem synchronization is in operation. This is the same as the LIF of the DSU, and when switching from non-operation to operation, the system is in a state where the received signal from the DSU can be immediately output to the internal bus, and the transmission signal from the internal bus can be output to the DSU. , the switching control signal line housed in the cable that connects the DSU and LIF monitors each other's status, and detects whether the other LIF is not operating or is in an abnormal state (out of synchronization, non-mounting, cable disconnection, etc.). Since the local LIF switches autonomously when it is in a normal state, there is no need for a control module, and when the other party's status cannot be monitored due to a cable disconnection, the DS can be switched at the same time.
Since the connection with U is also disconnected, both LIFs will not be in operation at the same time.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 10a and 1Qb are duplicated LIFs,
11 is a cable connecting the DSU 3, LIFlQa, and LIFJ Qb, and 12 is a clock generation module that generates a clock that serves as an operating reference for LIFloa and 10b. 200 is the transmission line from LIFlQa, 1Qb to DSU3, 201 is LIFloa from DSU3,
The reception lines 202 to 207 to 10b are signal lines forming a switching control signal line group, and these are accommodated within the cable 11, and the arrows indicate the signal transmission direction. Signal line 202
~204 are for signals from LIFIQa to L engineering F10b, and signal lines 205 to 207 are from LIFlob to LIFlQ
This is for the signal to a. Signal lines 202 and 203 are LIFl
A signal indicating whether Qa is in operation (hereinafter referred to as 5OPftAL)
During operation, the signal line 204 becomes LI.
A signal indicating whether FIQa is implemented (hereinafter referred to as E
XISTAL) and becomes LO/W when implemented. Signal lines 205 and 206 are for signals indicating whether or not LIF'lQb is in operation (hereinafter referred to as sop BL, sop BL).
During operation, it becomes LO, W, and the signal line 207 is LIF.
A signal indicating whether or not IQb is implemented (hereinafter referred to as E
XI8TBL), and is I,ow when installed.

FIG. 2 is a diagram showing an example of the configuration of the LIF according to the present invention, and this example shows the case of the LIF 19a. In the figure, 20
is a termination resistor switching circuit, 21 is a code/decoder, and 22 is a DS
A receiver receives signals from U3, 23.24 is an elastic memory that absorbs the difference between the internal transfer rate of transmitted and received signals and the transfer rate of DSU3, and 25.44 is used for synchronization control of bits and frames and for receiving signals from the signal line 201. A synchronization/alarm detection circuit that detects alarm conditions such as receiving signal disconnection and frame synchronization loss, 26 indicates whether LIF is LIFloa or L
27.31 is a clip flop, 28.32 is an anti-game), 29 is an exclusive or gate (hereinafter referred to as an EXOR gate).
, 30.43 is or game, 33.34.35 is inverter, 36.37 is driver, 38.39, 40.4
1.42 is the receiver, 50 to 54 are resistors, 60 is the power supply,
300 is a transmission signal, 301 is a reception signal, and 302 is a clock from the clock generation module 12.

Next, the operation will be explained. A transmission signal 300 input from the bus 103 is output onto the signal line 200 via the receiver 38, the elastic memory 23, the encoder/decoder 21, the driver 36, and the terminating resistor switching circuit 20. An input signal from the DSU 3 on the signal line 201 is output to the bus 103 as a received signal 301 via the terminating resistor switching circuit 20, the receiver 22, the code contention decoder 21, the elastic memory 24, and the driver 37. driver 36
and 37 are activated when the outputs of flip-flops 27 and 31 are at logic "L" (hereinafter referred to as "High"). Further, the output of the 7-rip 70-tube 21 is routed through the inverter 35 onto the signal line 203, and the output of the flip-flop 31 is routed through the inverter 33 onto the signal line 203.
2.

When the state of the signal EXISTBL on the signal 1fJ207 input via the receiver 40 is LowO, the terminating resistor switching circuit 20 becomes a terminating resistor that is connected in parallel with the partner LIF 1Qb and satisfies the specified impedance between the DSUs. Signal E
When the logic of XISTBL is undefined (the partner LI of cable 6
If the FI Qb side or the own LIFIQa side is missing or the partner LIFIQb is not mounted), the letter 2400 Å power side is connected to the power supply 60 via the resistor 50, so it is in a high potential state, and the output of the receiver 40 becomes High. ,
The terminating resistor switching circuit 20 switches to a single terminating resistor that satisfies the specified impedance between the DSUs.

The synchronization/alarm detection circuit 25 outputs a signal 3 that is LOW when synchronization is lost or a received signal is interrupted, and is HIGH during normal operation.
Outputs 03. This signal 303 is input to AND gate 28. Further, the synchronization/alarm detection circuit 44 also inputs a signal similar to that described above to the AND gate 32.

The clock 302 is input to the synchronization alarm detection circuit 25.44 via the receiver 39, and is also input to the BXO gate 29. In the LIFI Qa, the switch 26 is connected to the A side in the figure, and the input signal 308 to the BXOR gate 29 is set to High (in the LIFjQb, it is connected to the B side in the figure, and the EXO gate 290 input signal 308 is Low ) K. The clock 302 input to the EXOR gate 29 via the receiver 39 is EXO
When the input signal 308 of the gate 29 is High, the mother phase is applied to the output of the EXO gate 29, and when the input signal 308 is Lovy, the phase is reversed and the EXO
It appears at the output of the gate 29.

The OR gate 30 is connected to the signal line 0PRBL on the signal line 206.
When the logic of the signal EXISTBL on the signal line 207 is undefined or high, the outputs of the receivers 40 and 42 become high, so the output is high.
igh1 issue 304 total 304 Ru. The AND gate 28 outputs a high signal 305 when both the signal 303 and the signal 304 are high. Therefore, 7 lip flops 27
When the signal 303 is Low or the signal 304 is Low, and the output signal 301 of EXO & gate 29 transitions from Low to High, the signal 306 is Low.
and both signal 303 and signal 304 are High.
, and the output signal 307 of BXO gamer and 29 is Low.
The signal 306 goes High in synchronization with the transition from
Make it gh.

Since the OR gate 43 can be explained in the same manner as described above, it will not be described here.

The configuration of the other duplicated LIFlQb is as follows:
In the configuration of FIG. 2, the switch 26 is connected to the B side,
Signal line 202 and signal line 205, signal line 203 and signal line 2
06, it is the same as if the connection between the signal line 204 and the signal line 207 was reversed, so illustration is omitted.

FIG. 3 shows the switching timing operation. In the figure, a and b appended to the end of the signal name indicate that the signal is on LIF'10a or LIFlob, respectively. In section "A", both LIF1Qa and i are connected immediately after the power is turned on.
Qb is still in an abnormal state such as out of synchronization and both are not operating, and in section 1B'' both the transmitting and receiving systems of both LIF1Qa and 1Qb are in a normal state, but the transmitting and receiving system of LIFIQa is in operation and those of LIFlob are νμ Driving status, section'
"C" indicates that the LIFiQa reception system has lost synchronization, and the LIFiQa reception system is in an abnormal state and is not operating.
The receiving system of lQb is in operation, section "D" is LIFl
Although Qa's receiving system has recovered to normal state, LIFlQ continues.
This shows that the receiving system b is in operation. L
The output signal 307a of the EXOR gate 29 of IFlQa is high when one input signal 308a of the EXO gate 29 is high.
Since the signal 302 from the bus 103 is a clock signal 9, the output signal 307b of the EXOR gate 29 of LIFiQb is the signal 30 from the bus 103 because one input signal 308b of the EXOR gate 29 is Low.
This is a clock signal with an inverted phase of 2. In addition, both LIF1
When the power is turned on, Qa and iQb connect signal lines 204 and 2.
07, low level signals EXISTAL and Low, respectively.
Outputs the vbell signal EXISTBL.

Below, changes in the operation of each signal in the figure will be described.

First, section "A" will be explained. Both LIF10a
, 10b, the output signals 303a, 312a, 303b, 312b of the synchronization/alarm detection circuit 25°44 are Lo.
Since the output signal 305a of the AND gates 28 and 32 is
, 31 Qa , 305b , 310b and the output signal 306a of the seven lipfrogs 27.31.

311a, 306b, and 311b are Low. As a result, the signals ROP_AL, ROP_BL and SO2_AL on the signal lines 203 and 206 and the signal lines 202 and 205
.

The SOP level BL is also High. In addition, or gate 3
The output signals 304a, 304b of 0 and the output signals 309a, 309b of the other OR gate 43 are also High. Next, when the output signals 303a and 303b of the synchronization/alarm detection circuit 25 become High at point 0 in the figure, the output 305a of the AND gate 28.

305b becomes High at the same time.

Next, section "B" will be explained. The aforementioned signal 30
5a, 7 lipfrog 2T inputting 305kl is:
Due to the difference in phase between the output clocks of the EXOR gate 29, the rising edge of the clock 307a latches data first, and the output of 306a becomes High (point 0 in the figure).

This signal is inverted by the inverter 35 and the signal becomes 0P.
It is output as RAL to the signal line 203 and output LIF1Qb, and the output of the OR gate 30 is set to Low. Therefore, the output 305b of the AND gate 28 becomes Low again.
Therefore, the signal line 306b from the flip-flop 27 which uses this signal as input data becomes Low. the result,
The signal ROP BL on the signal line 206 becomes High, and the states of LIFIQa and 1Qb become stable, and while LIFIQa is in operation, L1. F I Q b is not operating. The synchronization alarm detection circuit 44 can also be explained in the same way, so the explanation will be omitted.

Next, consider a case where the synchronous alarm detection circuit 25.44 detects an error during operation. Synchronous alarm detection circuit 25
．． 44. Since the explanation can be made using either method, the reception system synchronous alarm detection circuit 25 will be used here. LIFl while driving
When Qa's synchronous alarm detection circuit 25 detects an error, its output signal 303a changes from High to Low (point 0 in the figure).

As a result, the output of the AND gate 28 becomes Low, changing the signal line 305a from High to Low.

Due to changes in each of the above signals, 7 rip 70 of LIFlQa
The output signal 306a of the knob 27 becomes Low in synchronization with the transition of the signal 307a from Low to High, deactivating the outputs of the drivers 36 and 37, and making the signal ROPAL on the signal line 203 High. It becomes non-operating (point 0 in the figure).

Next, section @C11 will be explained. When the signal OPAL on the signal line 203 becomes High, LIFIQb
The output signal 304b of the OR gate 30 becomes High, and the output signal 305b of the AND gate 28 also becomes High. Due to the change in the signal, p, LIFlQb, the output signal 306b of the clip-flop 27 changes to the L level of the signal 307b.
At the time of the transition from ow to High, it goes High, and the signal BL on the signal line 206 goes Low, and the outputs of the drivers 36 and 37 in LIFiQb become active, and it becomes operational ( (0 points in the figure).

Next, section 1D"K will be explained. LIFI is reached at point 0 in the figure.
When the receiving system of Qa recovers from a state such as being out of synchronization and the signal 303a from the synchronization/alarm detection circuit 25 changes to High, the signal OPAL on the signal line 203 changes to Low. However, there is no change in the other signals, and as described above, LIFIQa remains inactive and LIFIQb continues to operate.

The above description can also be applied to the synchronous alarm detection circuit 44 and can be explained in the same way, so it will be omitted here.

FIG. 4 shows LIFiQa in duplex switching.

The states taken by 10b are summarized below. This state transition diagram is
Since it can be applied to both the transmitting system and the receiving system, the case of the receiving system will be explained here as well. In addition, in the diagram, abnormality means out of synchronization,
Alarm conditions such as reception signal disconnection, cable disconnection, and LIF
This means that it is not implemented. Further, arrows indicate possible transition directions from each state, and an arrow returning to its own state indicates that the state is up to state 1.

When the self and the other party are in the state 1401 where both are normal and not driving, the self is in the state 2402 where the self is driving and the other party is not driving, or vice versa, when the other party is driving and the self is in the non-driving state 1401. It moves to a non-operating state 3403, or it changes to either a state 4404 in which the other party becomes abnormal, a state 5405 in which it becomes abnormal, or a state 6406 in which both become abnormal. When both are in state 2402 or 3403 where both are normal, one of them is abnormal in state 4404-! or state 5405, or state 6406 in which both are abnormal, or continue in state 402 or 403 as is. Status 4404
, both of them move to abnormal state 6406, or the other party's state recovers to normal, and both of them are normal.
The decision is whether to transition to state 2402 where there is no change in the operating status of state 4404, or to continue in state 404 of the reed.

When in state 5405, the transition is the same as when in state 4404, and you can either stay in state 405, move to state 3403, move to state 6406, or move to state 540.
The question is whether to continue with step 5.

If both are in state 6406, where both are in an abnormal state, either continue in state 40G, either the self or the other party recovers to normal state and move to state 4404 or state 5405, or both are normal. state 1401.

Note that the state 1401 is a transitional state that moves to another state immediately after the power is turned on or as a transition from the above-mentioned state 6406, and does not remain in that state.

The state transitions of the receiving system have been explained above, but since the transmitting system also performs the above operations independently of the receiving system, the explanation will be omitted.

Note that the connection between the DSU3, LIFIQa, and LIF1Qb is such that in the above embodiment, the LIF side of the cable 11 is branched into two, but each LIF1Qa is connected to the LIF1Qa.

Connect individual cables to 10b and DSU3,
These cables may be connected by a cable equivalent to the cable 11, a connector, or the like.

In addition, in the above embodiment, when both LIFIQa and 10b are in a normal state, both LIFIQa and 10b are controlled as competitive control to determine which LIFIQa or 10b is in operation.
l Qb is configured to transition from non-operating to operating, or vice versa, at different times of the same clock phase, but other competitive control such as general priority control may also be used; It has the same effect as.

Furthermore, although the above embodiment has a redundant configuration with two LIFs, it is also possible to have more than two LIFs.

〔Effect of the invention〕

As described above, according to the present invention, a signal line group for multiplexing switching is accommodated in the connection cable with the DSU, and switching control is performed independently in each LIF according to the signal state of this signal line group. Because of this structure, fewer modules are required for multiplexing switching than in the past, and fewer cables are needed to connect each module, making the equipment less expensive and more reliable. , Signals from the DSU and internal bus are input in parallel to each multiplexed LIF, and synchronous pull-in, etc. can be performed even when the school is not in operation, in the same way as when it is in operation. There is very little loss of bit information in the transmit/receive signal when the switch is made during operation, and since the transmit system and receive system operate independently, it is possible to avoid errors in either system as in the past. If a problem occurs, there is no need to switch both systems at the same time, and the associated instantaneous communication interruptions and loss of bit information can be minimized.Furthermore, the cable that sends and receives signals to and from the DSU Since the signal line for switching control is housed inside, if the other party's status cannot be monitored due to the cable being disconnected, it will also be impossible to exchange signals with the DSU, and the connection with the DSU and the signal line for switching control will become impossible. When cables are installed separately, each LIF becomes operational without knowing the status of the other LIFs, and each LIF outputs the transmission signal to the DSU and the reception signal to the internal bus. There are effects such as no

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a multiplexing device according to an embodiment of the present invention, FIG. 2 is a configuration diagram showing an example of the LIF, and FIG. 3 is a time chart showing duplex switching timing, and
The figure is a state transition diagram showing the possible state transitions of the LIF receiving system, and FIG. 5 is a configuration diagram showing a conventional multiplexing device. 1 is a multiplexer, 3 is a DSU, 10a, 10b are LIFs
, li is a cable, 12 is a clock generation module, 2
0 is a terminating resistor switching circuit, 21 is a code/decoder, 25.4
4 is a synchronization/alarm detection circuit, 26 is a switch, 27.
31 is clip 70 tube, 29 is EXOR game, 10
3 is a bus, 200 is a transmission line, 201 is a reception line, 202~
207 is a signal line. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation (2 others)

Claims (1)

[Claims] In a multiplexing device in which a plurality of line interface modules are provided for one line termination device to form a redundant configuration and the line interface modules can be switched and connected to the line termination device, a clock serving as a reference for the operation of the line interface module is provided. a clock generation module that generates a clock, inputs a reception line from the line termination device to each of the line interface modules, and inputs the transmission lines from each of the line interface modules together to the line termination device; It connects the line termination device to the line interface module, and also connects the line interface module during operation.
The line interface modules are interconnected by a group of switching control signal lines including a signal line indicating non-operation and a signal line indicating whether the line interface module is installed, and the line interface module is configured to operate when the line interface module is operating or not. In addition, the signal is received and synchronously pulled in regardless of whether the signal is installed or not, and the terminating resistance of the transmission line and the reception line with the line termination device is switched depending on the signal state of the signal line indicating the presence or absence of the installation. Impedance matching is achieved, and the transmitting system and the receiving system are independently operated according to the signal state of the switching control signal line group based on the clock provided by the clock generation module, and when one of the line interface modules is in operation. Multiplexing characterized in that when other line interface modules become non-operating and an operating line interface module enters an abnormal state, it becomes non-operating and one of the normal line interface modules becomes operating in place of it. Device.