KR20000006473U - ST-4 class physical layer board redundancy device in ATM switch - Google Patents

Abstract

The present invention relates to STM-4 physical layer board redundancy function in ATM exchange. Especially, since physical layer is very sensitive to clock and peripheral logic, it can cause problems such as thermal failure or link error. The present invention relates to an STM-4 class physical layer board redundancy device in an ATM exchange configured for cell transmission.

The present invention converts a physical layer processing unit into a sub-board to implement redundancy, and transmits / receives a redundancy control signal between the sub-boards and the duplicated main boards so that an error state occurs in the corresponding physical layer processing unit. You can control whether you can choose whether to increase the stability by redundancy.

Description

ST-4 class physical layer board redundancy device in ATM switch

The present invention relates to the STM (Synchronous Transfer Mode) class 4 physical layer board redundancy in ATM switches. Especially, the physical layer is very sensitive to clock and peripheral logic, which can cause problems such as thermal failure and link error. The present invention relates to an STM-4 class physical layer board redundancy device in an ATM switch that duplicates a physical layer and transmits a cell.

In general, in the super fast communication system, there is redundancy in the switch, the synchronizer clock part, and the processor part. When an error occurs on one side, it is possible to cope with the other side. High reliability

However, the physical layer processing cell streams such as conventional real user cells and OAM cells related to Alarm Indication Signal (AIS), Remote defect Indication (RDI), etc. are unified, and such a conventional unified board-to-board interface is illustrated in FIG. As shown in FIG. 1, a unitized main board 10 and a line matching unit 20 that is a unitized sub board are provided.

The main board 10 includes a physical layer processing unit 11, an ATM layer processing unit 12, and a switch link matching unit 13.

The line matching unit 20 performs a function of converting a cell stream received through an optical path into an optical signal or an electrical signal.

The physical layer processing unit 11 processes the frame input from the line matching unit 20 to extract an ATM cell, loads the ATM cell received from the ATM layer processing unit 12 into an STM-n frame, and matches the line. Performs a function to deliver to the unit (20).

The ATM layer processing unit 12 transfers the cell received from the physical layer processing unit 11 to the switch link matching unit 13 by performing UPC inspection, adding routing information, and header conversion, and matching the switch link. The data received from the unit 13 is converted into an ATM cell and applied to the physical layer processing unit.

The switch link matching unit 13 performs block coding on a cell received from the ATM layer processing unit 12, converts parallel data into serial data, and transmits the serial data to the switch link, and parallel data applied from the switch link. Is converted into serial data and applied to the ATM layer processing section 12.

As described above, in the conventionally provided system, the line matching unit 20 converts the cell stream received through the optical path from the optical signal to the electrical signal and transmits the converted signal to the physical layer processor 11.

The physical layer processor 11 performs termination of the STM-n frame, extracts an ATM cell, that is, restores clock and data from a signal input from the line matching unit 20, and extracts the STM-n frame. The ATM cell is extracted and transferred to the ATM layer processing unit 12.

Accordingly, the ATM layer processor 12 checks the cell received from the physical layer processor 11 and transmits the cell to the switch link matching unit 13.

Accordingly, the switch link matching unit 13 performs block coding on the cell received from the ATM layer processing unit 12, converts parallel data into serial data, and transfers the serial data to the switch link.

At this time, since the switch link is redundant in the switch link matching section 13, the switch link interface section selects an active link and transmits and receives data.

As such, the conventional line matching unit provides a function of simply converting an optical signal into an electrical signal or an electrical signal into an optical signal, and is configured to be monolithic. It does not provide the ability to switch to a link.

In addition, the physical layer processing unit that processes a cell stream such as an actual user cell or an OAM cell related to AIS, RDI, etc. may be monolithic to generate a clock, a data frame, and various OAM (Operation Administration and Maintenance) cells. There are problems in stability and reliability because it cannot cope with various situations.

The present invention has been made in view of the above-described problems, and by switching the physical layer processing unit to a sub-board to implement redundancy, transmitting and receiving redundancy control signals between mutual sub-boards and the redundant main board, and corresponding physical layer processing unit The purpose is to provide stability by redundancy by controlling to select whether or not the sub board is active when an error occurs.

1 is a block diagram showing a conventional interface device between a single board.

Figure 2 is a block diagram showing an interface device between the redundant board according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

30, 30a, 30b: sub board 31: signal converter

32: FIFO 33: STM-4 class physical layer processing unit

34-1 to 34-4: STM-1 class physical layer processor 35: signal controller

36: clock synchronizer 40: main board

41-1, 42-1: Buffer section 41-2.42-2: Signal control section

41-3, 42-3: ATM layer processing section 41-4, 42-4: STM-1 link section

In order to achieve the above object, the present invention provides an ATM exchanger having a sub board and a main board, and implements the sub board in redundancy, and provides a mutual interface between the activated sub board and the main board among the redundant sub boards. In addition, it is characterized in that the active sub-board is selected by transmitting and receiving redundant control signals between the redundant mutual sub-boards and the main board and controlling the active state of the corresponding sub-board.

On the other hand, the sub-board provides mutual control signals for the duplication between the sub-board, the signal control unit for transmitting and receiving data to the active side by checking the main board and the user cell interface and link status, clock status and parity of the frame and the like; ; A signal converter configured to convert a cell stream received through an optical path into an electrical signal or an electrical signal to an optical signal; A FIFO for applying data applied from the signal conversion unit under control of the signal controller, or for applying data to a counterpart sub board implemented by redundancy when an abnormal signal occurs in each unit in the sub board; An STM-4 class physical layer processing unit which demultiplexes STM-4 class physical layer processing data applied from the FIFO or applies STM-4 class data multiplexed with four STM-1 grades applied to the FIFO; ; Convert the data applied from the STM-4 class physical layer processing unit into a frame structure of a certain ATM and transmit it to the main board, or multiplex the STM-1 class physical layer processing data applied from the main board to the STM-4 class physical A plurality of STM-1 class physical layer processors applied to the layer processor; And a clock synchronizer 36 for restoring and synthesizing a clock applied from the main board, converting the clock to a required clock in the sub-board, and applying the same.

On the other hand, the main board includes a buffer unit for storing the data between the plurality of STM-1 class physical layer processing unit and the ATM layer processing for a while after receiving and transmitting; A signal controller for notifying the buffer unit that data is applied from an active subboard among the redundant subboards; An ATM layer processing unit for converting the data applied from the buffer unit to UPC inspection and routing information to the STM-1 link unit or receiving the data from the STM-1 link unit into an ATM cell; STM-1 link unit for converting the parallel data applied from the ATM layer processing unit into a serial data format to be applied to another ATM switch, or converting the data applied from another ATM switch into a data format that can be processed in the ATM layer. Characterized in that.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the redundant board-to-board interface device according to the embodiment of the present invention includes a main board 40 and a redundant sub-board 30.

Here, the redundant sub-board 30 transmits / receives a redundancy control signal between the sub-boards 30a and 30b and the main board 40 so as to select an active state of the corresponding sub-board.

The redundant sub-board 30 includes a signal converter 31, a FIFO 32, an STM-4 class physical layer processor 33, and a plurality of STM-1 class physical layer processor 34-1. 34-4), a signal controller 35, and a clock synchronizer 36.

The signal converter 31 performs a function of converting a cell stream received through an optical path into an optical signal or an electrical signal.

The FIFO 32 applies the data applied from the signal converter 31 to the STM-4 class physical layer processor 33 under the control of the signal controller 35 or in each sub-board 30a. When the abnormal signal occurs in the negative, data is applied to the counterpart sub board 30b implemented with redundancy.

The STM-4 class physical layer processing unit 33 FIFO (STM-4 class data obtained by multiplexing four STM-1 levels from the plurality of STM-1 class physical layer processing units 34-1 to 34-4) 32) or demultiplex STM-4 class physical layer processing data applied from the FIFO 32 to the plurality of STM-1 class physical layer processing units 34-1 to 34-4.

The plurality of STM-1 class physical layer processing units 34-1 to 34-4 convert the demultiplexed STM-1 class physical layer processing data from the STM-4 class physical layer processing unit 33 into a frame structure of a predetermined ATM. Transfer the data to the main board 40 or multiplex the STM-1 class physical layer processing data applied from the main board 40 to the STM-4 class physical layer processing unit 33.

The signal controller 35 provides control signals to each other for redundancy between the sub-boards 30, and checks the main board 40 and the user cell interface and link state, clock state, and parity of frames. It is applied to the FIFO 32 to process a signal capable of transmitting or receiving data to the active side.

The clock synchronizer 36 restores and synthesizes a clock applied from the main board 40 and converts the clock clock into a clock required in the sub-board 30.

On the other hand, the main board 40 is composed of two STM-1 link units (41-4, 42-4) considering that the sub-board 30 is STM-4 class, so that the two main boards Four STM-1 grades are formed, and the buffer units 41-1 and 42-2, the signal control units 41-2 and 42-2, and the ATM layer processing units 41-3 and 42-3 are Equipped with the sub-board is operated.

The buffer units 41-1 and 42-2 temporarily store data between the plurality of STM-1 class physical layer processors 34-1 to 34-4 and the ATM layer processors 41-3 and 42-3. And then send and receive.

The signal controllers 41-2 and 42-2 inform the buffer units 41-1 and 42-1 that data is applied from the activated sub-boards among the redundant sub-boards 30.

The ATM layer processing units 41-3 and 42-3 convert UPC checking and routing information from the data applied from the buffer units 41-1 and 42-1 to the STM-1 link unit or convert the data into the STM-1 link unit. -1 receives the data from the link units 41-4 and 42-4 and converts the ATM cell.

The STM-1 link unit 41-4, 42-4 converts parallel data applied from the ATM layer processing units 41-3, 42-3 into a serial data format and applies it to another ATM switch, or another ATM. The data applied from the exchange is converted into a cell form that can be processed in the ATM layer.

Referring to the operation of the present invention configured as described above in detail with reference to Figure 2 as follows.

The redundant sub-board 30 transmits and receives a redundancy control signal between the sub-boards and the main board 40 so as to select an active state of the corresponding sub-board 30. The main board 40 The two STM-1 class links are assembled into the main board 40 and the STM-4 sub board 30 to interface with each other.

Then, one of the sub-boards 30 is the sub-board 30a in an active state, and the rest of the sub-boards 30 from the first sub-board 30 to the main board 40 under the assumption that the sub-board 30b is in a standby state. Referring to the operation of transmitting data, the signal converter 31 converts the cell stream applied through the optical path into an electrical signal from the optical signal to the FIFO 32, wherein the signal controller 35 in the STM-4 The state of the class physical layer processing unit 33, the plurality of STM-1 class physical layer processing units 34-1 to 34-4, and the clock synchronizing unit 36 are checked to check for abnormalities.

At this time, the sub-board 30a checks the state of its own, and if an error occurs in any one of them, the 'high' level signal is applied to the main board 40 with the current state of its own. In addition, it sends a signal that an error has occurred to the standby sub-board implemented by redundancy, and applies a signal requesting active operation.

That is, the signal processing unit 35 monitors the link state, the LOS state, the frame state, etc. of the STM-4 class physical layer processing unit 33, and the STM-1 class also grasps the same state, and the clock synchronizer ( 36) and whether the clock is synchronized with the physical layer processing units 33,34-1 to 34-4, and when an error occurs, the FIFO 32 transmits a signal requesting activation to the counterpart sub-board 30a. Directly transmits data to the counter sub-board 30b via the bus.

Accordingly, the FIFO 32 applies data to the counterpart sub board 30b, processes the physical layer data in the counterpart sub board 30b, generates a frame, and applies the data to the main board 40 side.

At this time, only one of the redundant sub-boards 30 is connected to the terminal and the other one of the sub-boards 30b does not have to have all the same functions, and the functions below the FIFO 32, that is, the physical layer processing unit 33,34- Only 1 ~ 34-4) becomes the board and receives data from the sub board 30a which is currently active to process the same function.

On the other hand, when a plurality of signals are checked in the state of the sub-board 30, but no error occurs, the FIFO 32 applies the data to the STM-4 class physical layer processing unit 33, The data applied by the STM-4 class physical layer processing unit 33 is demultiplexed and applied to a plurality of STM-1 class physical layer processing units 34-1 to 34-4.

Thus, the plurality of STM-1 class physical layer processing units 34-1 to 34-4 are applied to the main board 40 side.

Accordingly, the signal controllers 41-1 and 42-1 in the main board 40 inform the buffer units 41-1 and 42-1 that data is applied from the activated sub-board 30a, and simultaneously The buffer units 41-1 and 42-1 receive data from the plurality of STM-1 class physical layer processing units 34-1 to 34-4 and apply the data to the ATM layer processing units 41-3 and 42-3. do.

Therefore, the ATM layer processing units 41-3 and 42-3 apply the data to the STM-1 link units 41-4 and 42-4 by adding UPC inspection and routing information, and corresponding STM. The -1 link units 41-4 and 42-4 convert the parallel data into serial data format and apply it to another ATM switch.

Meanwhile, referring to a second operation in which the sub board 30 receives data from the main board 40, the signal controllers 41-1 and 42-2 in the main board 40 may perform the sub board 30a. The abnormality of the STM-4 class physical layer processing unit 33 and the plurality of STM-1 class physical layer processing units 34-1 to 34-4 is applied from the corresponding signal control units 41-1 and 42-1. Will receive.

At this time, when the sub board 30a is normal, data is applied to the sub board 30a through the buffer units 41-1 and 42-1 in the main board 40.

However, when the sub board 30a is abnormal, data is transmitted to the counterpart sub board 30b under the control of the signal controllers 41-1 and 42-1 in the sub board 30a.

Then, the plurality of STM-1 class physical layer processing units 34-1 to 34-4 in the counterpart sub-board 30b multiplex the STM-1 class data to be applied to the STM-4 class physical layer processing unit 33. Done.

Accordingly, the STM-4 class physical layer processing unit 33 transmits the data applied from the plurality of STM-1 class physical layer processing units 34-1 to 34-4 through the FIFO 32 to the signal converter 31. To be applied.

Accordingly, the signal converter 31 converts the data applied through the FIFO 32 into an optical signal and applies it to the subscriber side.

As described above, the present invention converts the physical layer processing unit into a sub-board to implement redundancy, and transmits and receives redundant control signals between the sub-boards and the main board to activate the sub-board when an error occurs in the corresponding physical layer processing unit. The stability can be increased by redundancy by controlling whether the state can be selected.

As described above, the present invention is implemented by redundancy by switching the physical layer processing unit to a sub-board, by transmitting and receiving redundancy control signals between the sub-boards and the main board, when the error occurs in the corresponding physical layer processing unit The stability can be increased by redundancy by controlling whether or not to be active.

Claims (3)

In an ATM exchanger having a sub board (30) and a main board (40), By implementing the sub-board 30 in redundancy, inter-interface between the activated sub-board 30 and the main board 40 of the duplexed sub-board 30, between the duplicated mutual sub-board 30 and STM-4 class physical layer in an ATM exchange, characterized in that the active sub-board 30 is selected by transmitting and receiving a redundancy control signal with the main board 40 and controlling the active state of the corresponding sub-board 30. Board redundancy. The method of claim 1, The sub board 30 provides mutual control signals for duplication between the sub boards 30, and checks the main board 40 and the user cell interface and link states, clock states, and parity of frames. A signal controller 35 for transmitting and receiving data to the active side; A signal converter 31 for converting a cell stream received through an optical path into an electrical signal or an electrical signal into an optical signal; When the data applied from the signal conversion unit 31 is applied under the control of the signal control unit 35 or when an abnormal signal occurs in each unit in the sub board 30a, a counterpart sub board implemented as redundancy ( FIFO 32 for applying data to 30b); STM-4 which demultiplexes STM-4 class physical layer processing data applied from the FIFO 32 or applies STM-4 grade data multiplexed to four STM-1 grades applied to the FIFO 32; A fourth-level physical layer processing unit 33; The STM-4 class physical layer processing unit 33 converts the data applied to a frame structure of a predetermined ATM and transmits the data to the main board 40 or the STM-1 class physical layer processing data applied from the main board 40. Multiple STM-1 class physical layer processing units 34-1 to 34-4 for multiplexing and applying the same to the STM-4 class physical layer processing unit 33; And a clock synchronizer 36 for restoring and synthesizing the clock applied from the main board 40, converting the clock to the required clock in the sub-board 30, and applying the same. Tier board redundancy. The method of claim 1, The main board 40 temporarily stores data between the plurality of STM-1 class physical layer processing units 34-1 to 34-4 and the ATM layer processing units 41-3 and 42-3 and transmits and receives a buffer. Sections 41-1 and 41-2; Signal control units (41-2, 42-2) for informing the buffer units (41-1, 42-1) that data is applied from an active sub board among the redundant sub-boards (30); UPC inspection and routing information converted from the buffers 41-1 and 42-1 are applied to the STM-1 link unit, or from the STM-1 link units 41-4 and 42-4. ATM layer processing units 41-3 and 42-3, which receive the applied data and convert the data into ATM cells; Convert the parallel data applied from the ATM layer processing units 41-3 and 42-3 into a serial data format to be applied to another ATM switch, or convert data applied from another ATM switch into a data format that can be processed in the ATM layer. STM-4 class physical layer board redundancy device in an ATM exchange, characterized in that it comprises a STM-1 link portion (41-4, 42-4) to apply.