JPS63163445U - - Google Patents

Info

Publication number
JPS63163445U
JPS63163445U JP4775987U JP4775987U JPS63163445U JP S63163445 U JPS63163445 U JP S63163445U JP 4775987 U JP4775987 U JP 4775987U JP 4775987 U JP4775987 U JP 4775987U JP S63163445 U JPS63163445 U JP S63163445U
Authority
JP
Japan
Prior art keywords
tester
terminal group
connector terminal
terminals
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4775987U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4775987U priority Critical patent/JPS63163445U/ja
Priority to KR1019880001867A priority patent/KR910002804B1/en
Priority to US07/160,837 priority patent/US4924391A/en
Priority to DE3806794A priority patent/DE3806794A1/en
Publication of JPS63163445U publication Critical patent/JPS63163445U/ja
Pending legal-status Critical Current

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  • Testing Or Calibration Of Command Recording Devices (AREA)
  • Control Of Non-Electrical Variables (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係わる自己診断用多機能テス
タの外観斜視図、第2図は同テスタの底面を示す
斜視図、第3図は同テスタの制御回路を示すブロ
ツク図、第4図はテスタのコネクタを車両のコネ
クタに接続した場合のテスタの動作を示すフロー
チヤート、第5図はR―232cコードのフオー
マツトを示す図、第6図はテスタとECU間のデ
ータ転送を示す図、第7図は同テスタとデータ通
信を行なうECU側のデータ通信処理を示すフロ
ーチヤート、第8図は同データ通信処理のテスタ
側の処理を示すフローチヤート、第9図はアクチ
ユエータ強制駆動におけるECU側の処理を示す
フローチヤート、第10図はアクチユエータ強制
駆動におけるテスタ側の処理を示すフローチヤー
ト、第11図は通信データ速度を設定する場合の
テスタ側の処理を示すフローチヤート、第12図
は接続ミスを検出するECU側の処理を示すフロ
ーチヤート、第13図はコネクタを示す図、第1
4図は型式、車種を設定する手段を示す図、第1
5図はECU側のダイアグノシスデータを消去す
る場合のテスタ側の処理を示すフローチヤート、
第16図はECU側のダイアグノシスデータを消
去する場合のECU側の処理を示すフローチヤー
ト、第17図は表示のマルチ化を行なうテスタ側
の処理を示すフローチヤート、第18図は本考案
の一実施例に係わるROMパツクの外れをハード
的に検出する回路図、第19図は本考案の他の実
施例に係わるROMパツクの外れをソフト的に検
出するためのメモリの記憶内容を示す図、第20
図は従来の自己診断信号をチエツクするコネクタ
を示す図、第21図は同コネクタの配置場所を示
す図、第22図は従来の自己診断信号を表示する
回路図である。 31……テスタ、32……表示装置、37……
ROM、42……マルチプレクサ、43……CP
U、46……キーボード、51……排他的オア回
路、52……インバータ。
Fig. 1 is an external perspective view of a self-diagnosis multifunctional tester according to the present invention, Fig. 2 is a perspective view showing the bottom of the tester, Fig. 3 is a block diagram showing the control circuit of the tester, and Fig. 4 is a perspective view of the tester. A flowchart showing the operation of the tester when the connector of the tester is connected to the connector of the vehicle. Fig. 5 shows the format of the R-232c code. Fig. 6 shows the data transfer between the tester and the ECU. Figure 7 is a flowchart showing data communication processing on the ECU side that performs data communication with the tester, Figure 8 is a flowchart showing processing on the tester side of the data communication processing, and Figure 9 is a flowchart showing the processing on the ECU side in forced drive of the actuator. Flowchart showing the process; Figure 10 is a flowchart showing the process on the tester side when the actuator is forced to drive; Figure 11 is a flowchart showing the process on the tester side when setting the communication data rate; Figure 12 is a flowchart showing the process on the tester side when setting the communication data rate. Flowchart showing the processing on the ECU side to detect the
Figure 4 is a diagram showing the means for setting the model and vehicle type.
Figure 5 is a flowchart showing the process on the tester side when erasing the diagnosis data on the ECU side.
Fig. 16 is a flowchart showing processing on the ECU side when erasing diagnosis data on the ECU side, Fig. 17 is a flowchart showing processing on the tester side for multi-display, and Fig. 18 is a flowchart showing processing on the tester side when deleting diagnosis data on the ECU side. FIG. 19 is a circuit diagram for hardware-based detection of ROM pack dislodgement according to the embodiment; FIG. 19 is a diagram showing the stored contents of a memory for software-based detection of ROM pack dislodgement according to another embodiment of the present invention; 20th
FIG. 21 is a diagram showing a conventional connector for checking a self-diagnosis signal, FIG. 21 is a diagram showing the location of the connector, and FIG. 22 is a circuit diagram for displaying a conventional self-diagnosis signal. 31...Tester, 32...Display device, 37...
ROM, 42...Multiplexer, 43...CP
U, 46...Keyboard, 51...Exclusive OR circuit, 52...Inverter.

補正 昭63.1.30 図面の簡単な説明を次のように補正する。 明細書第26頁第7行目に「R―232cコー
ド」とあるを「RS―232cコード」と訂正す
る。
Amendment January 30, 1983 The brief description of the drawing is amended as follows. On page 26, line 7 of the specification, the phrase "R-232c code" is corrected to "RS-232c code."

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 車両に搭載されたn個の電子制御装置から出力
される自己診断出力信号あるいは各種RAMデー
タが転送される各電子制御装置毎に取出された第
1ないし第n信号線と、常時いずれか一方の論理
レベルが出力される各電子制御装置から出力され
る切換え信号線とが接続される第1型集中コネク
タとを有する車両において、各種診断機能を有す
るテスタ本体と、車両の車種、年式に固有のデー
タが記憶されるメモリパツクと、このメモリパツ
クが装着されるテスタ本体側に設けられた第1の
コネクタ端子群と、この第1のコネクタ端子群に
接続される上記メモリパツク側に設けられた第2
のコネクタ端子群と、この第2のコネクタ端子郡
の少なくとも2端子以上に一定論理レベルの信号
を供給する第1の回路手段と、一定論理レベルの
信号が供給された第2のコネクタ端子群の端子と
接続される上記第1のコネクタ端子群の端子の論
理をとる論理回路とを具備し、この論理回路のレ
ベルに応じてテスタ本体のCPUに割込みをかけ
るようにしたことを特徴とする自己診断用多機能
テスタ。
The first to nth signal lines taken out for each electronic control device to which self-diagnosis output signals output from n electronic control devices mounted on the vehicle or various RAM data are transferred, and one of the In a vehicle that has a type 1 centralized connector to which switching signal lines output from each electronic control unit that outputs logic levels are connected, the tester body with various diagnostic functions and a tester unit specific to the model and year of the vehicle a memory pack in which data is stored, a first connector terminal group provided on the tester main body side to which this memory pack is attached, and a second connector terminal group provided on the memory pack side connected to this first connector terminal group.
a first circuit means for supplying a signal at a constant logic level to at least two terminals of the second connector terminal group; and a second circuit means for supplying a signal at a constant logic level to at least two terminals of the second connector terminal group. The tester is characterized by comprising a logic circuit that takes the logic of the terminals of the first connector terminal group connected to the terminals, and interrupts the CPU of the tester body according to the level of the logic circuit. Diagnostic multi-function tester.
JP4775987U 1987-02-27 1987-03-31 Pending JPS63163445U (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP4775987U JPS63163445U (en) 1987-03-31 1987-03-31
KR1019880001867A KR910002804B1 (en) 1987-02-27 1988-02-23 Multi-function testor for self-diagnosis
US07/160,837 US4924391A (en) 1987-02-27 1988-02-26 Trouble-diagnosable multifunction testing apparatus
DE3806794A DE3806794A1 (en) 1987-02-27 1988-02-29 MULTI-FUNCTION TEST DEVICE FOR DETECTING FAULTS

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4775987U JPS63163445U (en) 1987-03-31 1987-03-31

Publications (1)

Publication Number Publication Date
JPS63163445U true JPS63163445U (en) 1988-10-25

Family

ID=30868668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4775987U Pending JPS63163445U (en) 1987-02-27 1987-03-31

Country Status (1)

Country Link
JP (1) JPS63163445U (en)

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