JP2538643B2 - Programmable controller - Google Patents

Description

The present invention relates to a programmable controller, and particularly to an improvement of its input / output bus check mechanism.

[Conventional technology]

FIG. 4 shows a general configuration example of the programmable controller in which the processor 1 and the input / output module 2 are connected via the input / output bus 3.

As a specification of the input / output bus 3 relating to the exchange of input / output data, a signal system as shown in FIG. 5 is adopted, and signals of respective parts in FIG. 5 have the meanings shown in the following table. It is a thing.

In such a configuration, the reading of signals from the input module and the writing of signals from the output module are
Each is performed at the timings shown in FIGS. 6 (A) and 6 (B). In such a programmable controller, however, data access is performed as follows in order to improve the reliability of input / output.

First, in the input module, a circuit as shown in FIG. 7 (A) is provided, and the processor 1 executes the procedure as shown in FIG. 7 (B) to read the input data. That is, input data from an external device is latched in the latch circuit 2I1 by the TEND signal (step S1), and RD
The output unit 2I2, which is operated by a signal, is energized to read input data from the data bus. This reading is performed twice (steps S3 and S5), the data for two times are collated (step S7), the input data is confirmed if both match (step S9), and the data is tried again if they do not match. .

Further, the output module is provided with a circuit as shown in FIG. 8A, and the output data is written by the processor 1 executing the procedure as shown in FIG. 8B.

That is, the output data is latched in the first stage by the WR signal.
Set to 201 (step S11). After that, the output unit 203 is operated by the RD signal to read the latch data of the first stage (step S13), and it is confirmed that the write data and the read data match (step S15).
The first stage latch data is transferred to the second stage latch 202 by the signal.
Transfer to. Then, this becomes output data. on the other hand,
If they do not match, try again.

[Problems to be Solved by the Invention]

However, the above data access may not be sufficient.

For example, consider the case where the address bus and the data bus are short-circuited as shown in FIG. As shown in the figure,
When the address line A4 and the data line B0 are short-circuited, when A4 = "L", B0 is always "L", and erroneous data becomes the input data even if the double reading and collating procedure in the input module is performed.

Further, as shown in FIG. 10, consider a short circuit between the data buses. As shown in the figure, when the data lines B0 and B1 are short-circuited, if either B0 or B1 is “H” and either is L, B0 and B1 are both “L” and also 2 in the input module. Even if you follow the read-ahead collation procedure, you will end up with incorrect data as input data.

As described above, the conventional programmable controller could not detect a bus short circuit even if the double reading / verifying procedure in the input / output module is taken into consideration, and there is a risk that incorrect data may be input / output data.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and provide a programmable controller capable of easily detecting a short circuit between an address bus and a data bus forming an input / output bus. .

[Means for solving the problem]

In order to achieve the above-mentioned object, the present invention provides a programmable controller in which a processor and an input / output module are coupled via a bus line, wherein the processor uses an address bus of a row which does not access any input / output module. The bus line is configured by setting the logic level, reading data from the data bus pulled up to the high logic level, and determining whether the read data is at the high logic level. And a means for detecting the presence or absence of a short circuit between the address bus and the data bus.

In the present invention, paying attention to the fact that the address bus is fixed to L and the data bus is fixed to H when the input / output module is not inputting / outputting data. A short circuit between the address bus and the data bus is detected by determining whether the data is H or not.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of an address bus-data bus short circuit detection procedure by the programmable controller of the present invention. This procedure can be adopted in the programmable controller having the configuration shown in FIG. 4, and this procedure can be provided in the system program that the processor 1 normally has.

When this procedure is activated, first, in step S21, the address bus signals A0 to A4 are all set to L, and in step S23, the data on the data buses B0 to B7 are read out without access to any of the input / output modules 2. And step
At S25, it is checked whether all the data are H. As shown in FIG. 9, the data bus is pulled up to 5V, so if there is no abnormality, all the read data should be H. However, if either the data bus or the address bus is When there is a short circuit, all the address buses A0 to A4 are at L, so the data bus line where the short circuit exists becomes at L. That is, it is possible to recognize the presence or absence of a short circuit (steps S27 and S29).

Then, if there is no short circuit, that is, the address bus,
If there is no abnormality in the data bus, the operation as the programmable controller may be continued as it is, and if a short circuit is detected, the operator may be notified by an appropriate notification means such as a display and a buzzer. .

In addition to the short circuit between the address bus and the data bus, an abnormality such as a short circuit of the data bus with another L signal line can be checked by this procedure.

FIG. 2 shows an example of means for detecting a short circuit between the data buses. In this example, after the test data is sequentially written to the output modules farthest from the processor 1 on the data buses B1 to B7, the same read verification as that performed to the circuit of FIG. 8 (A) is performed. This is a check, and at this time TEND is not set, so data is not output to the outside. Then, if there is no abnormality in all the data buses, it is possible to continue the operation of the programmable controller as if there is no short circuit, and if there is an abnormality in any of the data buses, it is possible to appropriately notify that there is a short circuit (step S47,
S49).

As the test data, as shown in FIG.
Eight types of data in which any one bit of the data is L may be prepared and used sequentially in the above procedure.
Such test data can also be stored in the ROM or the like of the processor 1. Then, the read data may be collated with the data shown in FIG. When there is a short circuit between the data buses, the write data and the read data do not match, so that an abnormality can be detected.

〔The invention's effect〕

As described above, according to the present invention, the address bus and the data bus can be easily and easily performed without requiring a special circuit or the like for detecting a short circuit between the address bus and the data bus in the input / output bus. Since a short circuit between and can be detected, erroneous input and erroneous output can be prevented, and the reliability of the programmable controller can be improved.

[Brief description of drawings]

FIG. 1 is a flowchart showing an example of a procedure for detecting a short circuit between an address bus and a data bus by the programmable controller of the present invention, FIG. 2 is a flowchart showing an example of a procedure for detecting a short circuit between data buses, and FIG. FIG. 4 is an explanatory view showing test data that can be used in the procedure of FIG. 4, FIG. 4 is a block diagram showing a general configuration example of a programmable controller, and FIG. 5 shows signals exchanged between the processor and the input / output module in FIG. 6 (A) and 6 (B) are timing charts for explaining the timing of signal transmission / reception in FIG. 5, and FIGS. 7 (A) and 7 (B) are input data, respectively. FIG. 8 is a block diagram showing a circuit example on the input module side for collation and a flow chart showing a processing example by a processor. A) and (B) are a block diagram showing an example of a circuit on the output module side for collating output data and a flow chart showing an example of processing by a processor, respectively. FIG. 9 shows a short circuit between the address bus and the data bus. FIG. 10 is an explanatory diagram for explaining, and FIG. 10 is an explanatory diagram for explaining a short circuit generated between the data buses. 1 ... Processor, 2 ... I / O module, 3 ... I / O bus, A0-A4 ... Address bus, B0-B7 ... Data bus.

Claims (1)

(57) [Claims] 1. A programmable controller in which a processor and an input / output module are coupled via a bus line, wherein the processor sets an address bus to a low logic level state which does not access any input / output module. At the same time, by reading the data from the data bus pulled up to the high logic level and determining whether or not the read data is at the high logic level,
A programmable controller comprising means for detecting the presence / absence of a short circuit between an address bus and a data bus constituting the bus line.