JPS63161719A - Latch circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction by providing hysteresis characteristic so that a input gate of a master circuit and an input gate of a slave circuit are not turned on at a threshold voltage of a control signal of each gate when the master latch circuit is read and the slave circuit is latched. CONSTITUTION:When a control signal phi, changes slowly, the master latch circuit M changes to the reading state from the latch state and the slave latch circuit S changes from the read state into the latch state, the hysteresis characteristic is provided to the threshold voltage of each control signal controlling the enable or disable state of gates G1-G4 so that the input gate G1 of the master latch circuit and the gate G3 of the slave latch circuit S inputting the latch output B of the master latch circuit M are not turned on simultaneously. Thus, the input signal A read in the master latch circuit M is not delivered directly to the output C of the slave latch circuit S and no malfunction is caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a latch circuit used in a semiconductor integrated circuit device, etc., and particularly relates to prevention of malfunction.

[Conventional technology]

FIG. 9 shows a conventional mask slave latch circuit. In the figure, A is the input of the master latch circuit M, B is the input of the slave latch circuit S which is also the output of the master latch circuit M, C is the output of the slave latch circuit S, and φ(tGs and tGs) and i<ias and; feat> are a control signal and its inverted signal, respectively; G5 and G8 are gates whose enabled and disabled states are controlled by control signals φG5 and tGs; G6 and G7 are inverted control signals, respectively; Gate whose enable state is controlled, B3 is a buffer of master latch circuit M, B4
' is the buffer of the slave latch circuit S, 05 is the gate G
5 output, 06 is the output of gate G6, 07 is gate G7
The output 08 is the output of gate G8. Further, FIG. 10 shows the gates G5 to G depending on the state of the control signal φ.
8 and the states of latch circuit outputs B and C.

Next, the operation of the conventional device will be explained.

When gates G5 and G8 are enabled (main) by control signal φ (tGs and tGs), gates G6 and G7 are activated by control signal 1 (ice and r
G7) is in the disabled state (slave), and the input A
The signal is read up to the output 05 of the game) G5, and in the slave latch circuit S, the signal of the output C before the control signal φG8 is inverted is latched by 08 and the buffer B4.

Next, when the control signals φ and f are inverted, the gate G
s and G8 are in a disabled state (slave), and gates G5 and G7 are in an enabled state (main). In this state, in the master latch circuit M, the signal of output B before tGs is inverted is G6. The signal of output B latched by buffer B3 and simultaneously latched by master latch circuit M is read by gate G7 of slave latch circuit S and transmitted to output C.

[Problem that the invention seeks to solve]

In the conventional mask slave latch circuit, when the control signal φ changes slowly between the "L" potential and the "I" potential, the potential of the control signal φ changes between the "H" potential and the "L" potential. When the potential becomes unstable with respect to the potential of the master latch circuit M, a problem arises in that the signal of the input A read into the master latch circuit M is directly transmitted to the output C of the slave latch circuit.

When the master latch circuit M changes from the latch state to the read state, in the conventional mask slave latch circuit, the control signals φ (φG5 and ψG8) and 9T
The threshold voltages of the control signals φ and 1 are set around cc/2 so that the margin for the gates G5 to G7 (JG6 and 1irG7) is maximized. Therefore, in the above example, as shown in FIG.
After the gate 1-05 of the master latch circuit M changes from the disabled state (slave) to the enabled state 3 (main), and the gate Ge changes from the enabled state (main) to the disabled state (slave), the gate of the slave latch circuit S G7 becomes disabled (slave) rather than enabled (main), gate G
8 changes from the disabled state F3 (slave) to the enabled state (main). Also, the gate G7 of the slave latch circuit
After the gate G8 changes from the disabled state 3 (slave) to the enabled state (main) and the gate G8 changes from the enabled state (main) to the disabled state (slave), the master latch circuit M
The gate G5 changes from the enabled state (main) to the disabled state (slave), and the gate G6 changes from the disabled state (slave) to the enabled state (main). Therefore, the output is 0
A situation occurs in which both G5 and G7 appear as "main", and the input A signal read into the master latch circuit M is directly transmitted to the slave latch circuit output C, without fulfilling the original function of the mask/slave latch circuit. There was a problem with malfunctions.

This invention was made to solve the above-mentioned problems, and it is possible to maintain the original master/slave latch function even when the potential of the control signal becomes unstable, and to provide a mask/slave latch that can prevent malfunctions. The purpose is to obtain a slave latch circuit.

[Means for solving problems]

In the latch circuit according to the present invention, while the master latch circuit changes from the latch state to the read state, and the slave latch circuit changes from the read state to the latch state, the threshold voltage of the control signal that controls the enable or disable state of each gate is changed. , a hysteresis characteristic is provided so that both the input gate of the master latch circuit and the gate of the slave latch circuit which inputs the latch output of the master latch circuit are not turned on.

[Effect]

In this invention, when the master latch circuit changes from the latch state to the read state, and the slave latch circuit changes from the read state to the latch state, the input gate 1- of the master latch circuit is set to the threshold voltage of the control signal of each gate. Since a hysteresis characteristic is provided so that the gates of the slave latch circuit which input the latch output of the master latch circuit are not both turned on, the signal read into the master latch circuit does not directly appear at the output of the slave latch circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a latch circuit according to one embodiment of the invention. In the figure, A is the input of the master latch circuit M, B is the input of the slave latch circuit S which is also the output of the master latch circuit M, C is the output of the slave latch circuit S, φ (φG1 and φG4) and p<Ta2 and ;Ta3> are a control signal and its inverted signal, G1 and G4 are read gates and latch gates whose enable state 3 (main) and disable state (slave) are controlled by control signals φGl and φG4, respectively, and G2 and G3 are control signals. Latch gate and read gate whose enable state (main) and disable state (slave) are controlled by signals <6G2 and Ta2, B1 is the buffer of the master latch circuit M, B2 is the buffer of the slave latch circuit S, 01 is the gate 02 is the output of gate G2, 03 is the output of gate G3, and 04 is the output of gate G4.

FIG. 2 is a diagram showing the states of the gates 01 to G4 and the latch circuit outputs B and C depending on the voltage level of the control signal φ. Figures 3 and 4 show the control signal φ
The equivalent circuit of the master latch circuit M and the slave latch circuit S when the potential changes to 0-■CC-0v is shown,
It represents how the input signal of A is transmitted.

Next, the operation will be explained.

In FIG. 1, gates G1 and G4 are in an enabled state;
When I:t (main) and gates G2 and G3 are disabled (slave), the master latch circuit M reads the input A signal to the output 01 of the gate G1, and the slave latch circuit S reads the control signal φ. The signal of output C before it is inverted is latched by gate G4 and buffer B2.

Next, when the control signal φ is inverted, the gate '
Gi and OA disabled:! (slave), and gates G2 and G3 are enabled. At this time, in the master latch circuit M, the signal of the output B before the control signal φ is inverted is latched by the gate G2 and the buffer B1, and at the same time, the signal of the output B latched by the master latch circuit M is latched by the slave latch circuit S. It is read by gate G3 and transmitted to output C.

Next, the relationship between the control signal φ, moxibustion, and the output state of each gate in the circuit of FIG. 1 will be explained using FIGS. 2, 3, and 4. In this example, game 1-G
Control signal φ (φG1 and φ
G4) and ;
(ON)<Vcc=V3 (OFF)<Vl (
ON) and Vcc-V2 (ON)<Vt (OFF)=V4
(OFF)<Vcc-V3 (ON) (However,
Vl (ON) to v4 (ON) are the threshold voltages at which the control signals φG1 to φG4 change from "L" to "H', and vl (OFF) to v4 (OFF) are the threshold voltages at which the control signals φG1 to φG4 change from "H" to "H". 2, 3 and 4.
As shown in the figure, the gate G1 of the master latch circuit M is in the enabled state from the disabled state (slave)! (Main) Game) G2 changes from enabled state fi (main) to disabled state (slave) (Figures 3 and 4 (11-(
3) or 3) to (5)) Previously, gates 1-G3 of the slave latch circuit S were changed from an enabled state (main) to a disabled state (slave), and gate G4 was changed from a disabled state (slave) to an enable state. state (main), and the gate G3 of the slave latch circuit S is disabled (main).
Before the gate G4 changes from the enabled state f3 (main) to the disabled state (slave), the gate Gt of the master latch circuit M changes from the enabled state 3 (main) to the disabled state (slave). ), gate G2 changes from the disabled state (slave) to the enabled state 3 (main).

In this embodiment, the outputs of Gl and G3 are 0.
There is no state in which both 1 and 03 appear as "main", and a state in which the input signal read by the master latch circuit M is directly transmitted to the slave latch circuit output C does not occur.
No malfunctions will occur.

In the above embodiment, an example using buffers Bl and B2 has been described, but if the outputs of gates 01 to G4 are sufficiently large, buffers Bl and B2 are used.

A similar effect can be obtained by omitting B2 and using the circuit configuration shown in FIG.

In the above embodiment, the output B of the master latch circuit M is connected to the connection point between the output 01 of the gate Gl and the output 02 of the gate G2, and the output C of the slave latch circuit S is connected to the connection point of the output 03 of the gate G3 and the output 04 of the gate G4. However, as shown in FIG. 6, the input of the gate G2 may be the output B of the master latch circuit M, and the input of the gate G4 may be the output C of the slave latch circuit S, as shown in FIG. As shown in FIG. 8, the input of the gate G4 may be the output C of the slave latch circuit S, or the input of the gate G2 may be the output B of the master latch circuit M, as shown in FIG.

Further, in the above embodiment, the gates G1 and G4 are connected to the
The roll signal φ (φG1 and φG4) controls the gates G2 and G3 using the control signal $ (?G2 and IG3), but the gates G1 and G4 are controlled by the control signal f and the gates G2 and G3 are controlled by the control signal φ. However, the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the latch circuit according to the present invention, when the voltage of the control signal changes slowly between 0 and VccO, the master latch circuit changes from the latched state to the read state, and the slaver/Sochi circuit changes from the read state to the latch state. When the state changes, both the input gate of the master latch circuit and the gate of the slave latch circuit whose input is the latch output of the master latch circuit are turned on at the threshold voltage of each control signal that controls the enable or disable state of each gate. Since a hysteresis characteristic is provided to prevent this, there is an effect that malfunctions such as the input signal being directly transmitted to the output of the slave latch circuit through the master latch circuit will not occur.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a master-slave latch circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the states of each gate and output depending on the state of the control signal in the circuit, and FIGS. 3 and 4. are diagrams showing equivalent circuits of a master latch circuit and a slave latch circuit depending on the states of control signals, respectively, and FIGS. 5, 6, 7, and 8 are diagrams showing mask/slave latch circuits according to other embodiments of the present invention. 9 is a circuit diagram showing a conventional general mask slave latch circuit, and FIG. 10 is a diagram showing the states of each gate and output depending on the state of a control signal in the circuit. In the figure, A is the input of the master latch circuit M, B is the input of the slave latch circuit S which is the output of the master latch circuit M, C is the output of the slave latch circuit S, φ is a control signal, J is an inverted signal of the control signal φ, G1 and G4 are gates whose enable or disable states are controlled by the control signal φ, B1 is a buffer for the master latch circuit M, B2 is a buffer for the slave latch circuit output S, 01 to 04 are the outputs of G1 to G4, respectively, φ0 to φ8 are respectively 0〈φ1×φ
2〈φ3〈Vcc, Q〈φ6〈φ5〈φ4〈Vcc
, Q'<φ7〈ψO〈φB<Vcc. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) A first gate whose enable or disable state is controlled by a control signal and receives an input signal; and a second gate whose enable or disable state is controlled by the control signal and which performs latching, reciprocal to the first gate. the output of the first gate and the output of the second gate are connected to an AND tie,
When the first gate is enabled and the second gate is disabled, the first gate reads the input signal, and when the first gate is disabled and the second gate is disabled, the first gate is enabled and the second gate is disabled. a master latch circuit that is in a latched state by the second gate when in the enabled state and generates a latch output; a third gate that performs latching when the enable or disable state is controlled by a control signal; and a fourth gate whose enable or disable state is reciprocally controlled by the control signal and whose input is the latch output of the master latch circuit,
The output of the third gate and the output of the fourth gate are connected in an AND tie, and when the fourth gate is enabled and the third gate is disabled, A latch output is read, and when the third gate is enabled and the fourth gate is disabled, the third gate enters a latch state and generates a latch output from the third gate. In the master/slave latch circuit, the threshold voltage of the control signal that controls the enable or disable state of each gate is such that the master latch circuit changes from the latched state to the read state, and the slave latch circuit changes from the latched state to the read state. A latch circuit having a hysteresis characteristic so that both the first gate and the fourth gate do not turn on during the change from a state to a latch state. (2) The threshold voltage of the control signal of each gate is such that the first gate of the master latch circuit changes from a disabled state (slave) to an enabled state (main), and the second gate of the master latch circuit changes from an enabled state (main) to a disabled state. Before changing to the enabled state (slave), the fourth gate of the slave latch circuit changes from the enabled state (main) to the disabled state (slave), and the third gate changes from the disabled state (slave) to the enabled state (slave). (mainly) and also
Before the fourth gate of the slave latch circuit changes from a disabled state (slave) to an enabled state (main), and before the third gate changes from an enabled state (main) to a disabled state (slave), the master latch circuit It has a hysteresis characteristic so that the first gate changes from an enabled state (main) to a disabled state (slave), and the second gate changes from a disabled state (slave) to an enabled state (main). The latch circuit according to claim 1, characterized in that: (3) The threshold voltage of the control signal of each gate above is as follows: the power supply voltage is Vcc, and the threshold voltage is Vcc.
_1 to V_4, control signal from “L” to “H”
”, the threshold voltage when it changes to V_1 (ON
) or V_4 (ON), the threshold voltage when the control signal changes from “H” to “L” is V_1.
(OFF) or V_4(OFF), Vcc-V_2(OFF)=V_4(ON)<Vcc-
V_3(OFF)<V_1(ON) and Vcc-V_2(ON)<V_1(OFF)=V_4(
3. The latch circuit according to claim 2, wherein the latch circuit has a hysteresis characteristic so as to satisfy (OFF)<Vcc-V_3(ON).