JPS61184919A - High voltage circuit - Google Patents

Abstract

PURPOSE:To attain low power consumption by eliminating a period that a load transistor (Tr) of an output section of a high voltage circuit provided with a bi-stable element and a drive Tr are both turned on. CONSTITUTION:A CR delay circuit 16 is provided between a control signal input terminal 5 and a gate of an NMOSTr2. The circuit 16 gives the same time delay as the state inverting time of the bi-state element 3. Through the provision of the circuit 16, it is possible to make the time of state change of a PMOSTr1 and the time of state change of the Tr2 coincident. Thus, simultaneous turning-on of the Trs 1, 2 during the state inversion of the element 3 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high voltage circuit having an output stage of CMO3 configuration.

[Prior art and its problems]

Conventionally, a circuit as shown in FIG. 2 is known as a high voltage circuit having an output stage of CMO3 configuration.

In FIG. 2, 20 is a control signal input terminal, 21 is a high voltage power supply terminal, 22 is a reference potential application terminal, 23 is a high voltage output terminal, 24 is a high voltage capacitor, 25 is a resistor, and 26 is a high voltage output terminal.
is a high voltage PMO5) transistor, 27 is a high voltage NMOS
It is a transistor. This PMO3) transistor 26 and NMOS transistor 27 constitute a high voltage inverter.

In the high voltage circuit configured as above, the input terminal 20
Considering the case where the input signal to capacitor 2 is periodic,
4 and the resistor 25 is the CR time constant determined by the input terminal 2
It needs to be sufficiently larger than the period of the signal input to 0. Therefore, the capacitance value of the capacitor 24 and the resistance value of the resistor 25 must be selected in accordance with the input signal. On the other hand, if the input signal is not periodic, for example, direct current, and has little change (or if there is a long time between signal change points, the charge stored in the capacitor 24 will be discharged, so the PMO5 ) The transistor 26 is the control signal input terminal 20
This turns off regardless of the input signal to the MOS transistors 26 and 27, causing a malfunction of the high voltage CMOS inverter made up of MOS transistors 26 and 27.

Conventional high-voltage circuits having an output stage with a CMO3 configuration have the disadvantage of malfunctioning in response to non-periodic signals with little variation, and the difficulty in inputting capacitance and resistance values in response to periodic signals. It has the disadvantage that selection must be made in accordance with the signal.

Therefore, the inventor of the present invention has proposed a circuit as shown in FIG. 3 as a high-voltage circuit that improves upon such drawbacks. This circuit is formed by forming an N-well on a P-type substrate, a PMO3 high-voltage transistor in the N-well, and a high-voltage NMO3) transistor in the P-type substrate region.
It is a high voltage integrated circuit with an output stage configured as follows.

This high voltage circuit consists of PMO3) transistor 1 and NM
an output stage with a CMO3 configuration consisting of two OS transistors;
It includes a bistable element 3 which is composed of two sets of inverters and has an output that is logically the same as an input, and a high voltage capacitor 4. One end of the capacitor 4 is connected to the control signal input terminal 5, and the other end of the capacitor 4 is connected to the input terminal 6 of the bistable element 3.
It is connected to the. Output terminal 7 of bistable element 3 is PMO
Connected to the gate of S transistor 1. The control signal input terminal 5 is also connected to the gate of the NMO5I-transistor 2.

The bistable element 3 is a high voltage PMOS l-transistor 8,
High voltage PMO3) transistor 9 and two resistors 10.11
The input terminal 6 of the bistable element is PMO5.
) The output terminal 7 is connected to the gate of the transistor 8, and the output terminal 7 is connected to the drain of the transistor 9. Further, the gate of PMO3) transistor 8 is connected to the drain of PMO3) transistor 9, and the gate of PMO3) transistor 9 is connected to the drain of PMOS transistor 8. The sources of these MOS) transistors 8 and 9 are connected to the high voltage terminal 12, and the drains are connected to resistors 10 and 11, respectively.
It is connected to the voltage application terminal 13 via.

The high voltage power supply terminal 12 is further connected to the source of the PMOS transistor 1, the connection point between the drain of the PMOS transistor 1 and the drain of the NMO transistor 2 is connected to the high voltage output terminal 14, and the connection point between the drain of the PMOS transistor 1 and the drain of the NMO transistor 2 is connected to the The source is connected to the reference potential application terminal 15.

For example, a voltage of 200 V is applied to the high voltage power supply terminal 12, and a voltage of 0.0 V, for example, is applied to the reference potential application terminal 15. For example, an IOV signal is input to the control signal input terminal 5, and a high voltage power supply terminal 12 is input to the voltage application terminal 13.
A voltage lower than the voltage 20QV by the amplitude voltage of the input signal of the control signal input terminal 5, for example, a voltage of 190V, is applied.

In this high voltage circuit, IOV is applied to the control signal input terminal 5.
When the input signal is applied, the state of the NMOS transistor 2 immediately changes from off to on. On the other hand, the input signal passes through the high voltage capacitor 4 to the input terminal 6 of the bistable element 3.
transmitted to. As a result, the PMO3) transistor 8 is turned off and the PMOS transistor 9 is turned on.As a result, the input signal is latched, and a signal having the same phase as the latched signal is output to the output terminal 7 of the bistable element 3. This signal is P
MO3) is applied to the gate of transistor l, which turns off transistor 1 and outputs terminal 1 of the high voltage circuit.
The voltage of 4 becomes OV.

Conversely, when the input signal is no longer applied to the control signal input terminal 5, the NMO 3) transistor 2 is turned off, while the state of the bistable element 3 is reversed, the PMOS transistor 1 is turned on, and the high voltage output terminal 14 is turned off. A voltage of 200V is output.

According to such a high voltage circuit, the input signal to the control signal input terminal 5 is latched by the bistable element 3, and the PMO transistor 1 is turned on and off by the latched input signal. Even if the signal is DC and the time between the signal change points is long and the capacitor 4 is discharged during this period, the CMOS inverter can be operated normally as long as it has a capacitance value that can invert the bistable element 3. It can be made to work. Furthermore, even if the input signal is periodic, the capacitance value of the high voltage capacitor 4 only needs to have a capacitance value necessary for inverting the state of the bistable element 3, regardless of the input signal. , it becomes unnecessary to select the CR time constant in accordance with the input signal as in the high voltage circuit shown in FIG.

However, in the high voltage circuit shown in FIG.
O3) Turn on transistor.

There is a delay in turning off and turning on the PMOS (PMOS) transistor. Therefore, the input signal to the control signal input terminal 5 immediately changes the NMO transistor from off to on, but the PMOS transistor changes from on to off with a delay of the state inversion time of the bistable element. Therefore, during this period, PMOS) transistor l and NMO3) transistor 2
Both transistors of the CMOS inverter are turned on. Therefore, although the high voltage circuit shown in FIG. 3 has improved the drawbacks of the high voltage circuit shown in FIG. 1, it has a new drawback in that the power consumption is larger than that of the ideal CMO5 circuit.

[Purpose of the invention]

An object of the present invention is to provide a high voltage circuit including a bistable element that operates with low power consumption by eliminating the period in which both the load transistor and the drive transistor of the high voltage output section are on. .

[Structure of the invention]

The present invention provides a high voltage circuit having an output stage of a complementary circuit consisting of a load transistor and a drive transistor.
A series circuit including a capacitor and a bistable element having an output logically the same as the input is provided between the control signal input terminal of the complementary circuit and the gate of the load transistor, and one terminal of the capacitor is connected to the gate of the load transistor. a control signal input terminal, an output terminal of the bistable element is connected to the gate of the load transistor, and further between the control signal input terminal and the gate of the drive transistor.
1. The device is characterized by comprising a delay circuit that provides a delay equal to the state inversion time of the bistable element.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of the present invention. This high voltage circuit is the high voltage circuit shown in FIG. 3 in which a CR delay circuit 16 is provided between the control signal input terminal 5 and the gate of the NMO transistor 2, and the other configuration is as shown in FIG. This delay circuit 16 is exactly the same as the circuit shown in FIG.
It provides the same time delay as the state inversion time of the bistable element 3, and in this embodiment a simple example consisting of two capacitors 17.degree. 18 and one resistor 19 is shown.

The control signal input terminal 5 is connected to one end of a capacitor 17 and a resistor 19, the other end of the resistor 19 is connected to one end of a capacitor 18, and the other end of the capacitor 17 is connected to one end of a capacitor 18.
connected to the other end. One end of the capacitor 18 is NM
O3) Connected to the gate of transistor 2 and capacitor 18
The other end is connected to a reference potential application terminal 151Km.

By providing this delay circuit 16, the time when the state of the PMOS transistor 1 changes and the time when the state of the NMOS transistor 2 changes.
It becomes possible to match the time when the state changes.

Therefore, it is possible to prevent both the PMOS transistor 1 and the NMOS transistor 2 from turning on during state inversion of the bistable element 3. Therefore, the output stage of the high voltage circuit shown in FIG. 1 can perform ideal CMO3 operation.

Although the above embodiment has been explained by taking the N-well structure CMO3 circuit as an example, it is clear that the present invention can be implemented in the same manner with a P-well structure 0M08 circuit. Furthermore, regarding the delay circuit, the present invention can be implemented using not only the CR delay circuit shown in FIG. 1 but also a delay circuit having a configuration similar to that of the bistable element 3 in FIG. 1.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a high voltage circuit without ineffective power consumption in the high voltage output stage.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a high voltage circuit according to the present invention. 1.8.9.26...High voltage PMO3) transistor 2.27...High voltage NMOS transistor 3...
...Bistable element 4.24...High voltage capacitor 5.20...Control signal input terminal 6...Bistable element input terminal 7...
・Bistable element output terminals 10.11, 19.25...Resistance 12.21...High voltage power supply terminal 13...Voltage application terminal 14.23...High voltage output terminal 15.22 ...Reference potential application terminal 16...Delay circuit 17.18...Capacitor Fig. 2

Claims (1)

[Claims] (1) In a high voltage circuit having an output stage of a complementary circuit consisting of a load transistor and a drive transistor, a capacitor is connected between the control signal input terminal of the complementary circuit and the gate of the load transistor, and the input and logic a series circuit with a bistable element having identical outputs, one terminal of the capacitor being connected to the control signal input terminal, an output terminal of the bistable element being connected to the gate of the load transistor; , a high voltage circuit comprising a delay circuit that provides a delay equal to the state inversion time of the bistable element between the control signal input terminal and the gate of the drive transistor.