JPS63159425U - - Google Patents
Info
- Publication number
- JPS63159425U JPS63159425U JP4908787U JP4908787U JPS63159425U JP S63159425 U JPS63159425 U JP S63159425U JP 4908787 U JP4908787 U JP 4908787U JP 4908787 U JP4908787 U JP 4908787U JP S63159425 U JPS63159425 U JP S63159425U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- control signal
- tri
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 claims description 6
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4908787U JPS63159425U (enExample) | 1987-04-01 | 1987-04-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4908787U JPS63159425U (enExample) | 1987-04-01 | 1987-04-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63159425U true JPS63159425U (enExample) | 1988-10-19 |
Family
ID=30871216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4908787U Pending JPS63159425U (enExample) | 1987-04-01 | 1987-04-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63159425U (enExample) |
-
1987
- 1987-04-01 JP JP4908787U patent/JPS63159425U/ja active Pending
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