JPS63158883A - Pnpn photo-thyristor - Google Patents

Pnpn photo-thyristor

Info

Publication number
JPS63158883A
JPS63158883A JP61307033A JP30703386A JPS63158883A JP S63158883 A JPS63158883 A JP S63158883A JP 61307033 A JP61307033 A JP 61307033A JP 30703386 A JP30703386 A JP 30703386A JP S63158883 A JPS63158883 A JP S63158883A
Authority
JP
Japan
Prior art keywords
emitting layer
light
layer
band width
forbidden band
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61307033A
Other languages
Japanese (ja)
Other versions
JPH079997B2 (en
Inventor
Kenichi Kasahara
健一 笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP30703386A priority Critical patent/JPH079997B2/en
Priority to DE8787118935T priority patent/DE3782232T2/en
Priority to CA000554905A priority patent/CA1271549A/en
Priority to EP87118935A priority patent/EP0273344B1/en
Priority to US07/136,588 priority patent/US4829357A/en
Publication of JPS63158883A publication Critical patent/JPS63158883A/en
Publication of JPH079997B2 publication Critical patent/JPH079997B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Thyristors (AREA)
  • Led Devices (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)

Abstract

PURPOSE:To increase the forbidden band width of a carrier fonfinement layer with a separation from a light-emitting layer, and to accelerate the speed of response by forming a base region by the light-emitting layer and the carrier confinement consisting of a semiconductor having forbidden band width higher than the light-emitting layer and joining with the light-emitting layer. CONSTITUTION:In a pnpn photo-thyristor in which a base region composed of a plurality of semiconductor layers having forbidden band width layer than an anode region 13 and a cathode region 15 is held by the anode region 13 made up of p-Al0.3Ga0.7As and the cathode region 15 consisting of n-Al0.3Ga0.7As, the base region has a light-emitting layer 14d composed of n-GaAs and carrier confinement layers 14c, 14e made up of n-AlZGa1-ZAs (0<=z<=0.3) having forbidden band width higher than the light-emitting layer 14d and joining with the light-emitting layer 14d. The forbidden band width of the carrier confinement layers 14c, 14e increases with a separation from the light-emitting layer 14d. Accordingly, the injection and confinement action of carriers are improved, thus allowing fast response without lowering the absorption efficiency of trigger beams.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は画像処理や光論理演算等に必要とされる半導体
光メモリとして使用されるpnpn光サイリスタに関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pnpn optical thyristor used as a semiconductor optical memory required for image processing, optical logic operations, etc.

〔従来の技術〕[Conventional technology]

微少なトリガ光によって内部状態が変化して発光し始め
、トリガ光が消えた後でも光り続けるような機能を備え
た半導体光メモリは、これからの光交換や並列情報処理
システムを構成する際に不可欠なキー・デバイスである
Semiconductor optical memory, which has the ability to change its internal state in response to a minute trigger light and begin emitting light, and continue to emit light even after the trigger light has disappeared, will be essential when constructing future optical exchange and parallel information processing systems. It is a key device.

第5図はジャーナル・オン・アプライド・フィジックス
(Journal of Applied Physi
cs)誌、第59巻、第596頁〜第600頁、198
6年に記載されている半導体光メモリの従来例の断面図
である。
Figure 5 is from the Journal of Applied Physics.
cs) Magazine, Volume 59, Pages 596-600, 198
1 is a cross-sectional view of a conventional example of a semiconductor optical memory described in 1996.

この従来例はpnpnサイリスク構造となっている。ア
ノード領域53とカソード領域55はそれぞれp−AI
!GaAsとn−Al!G1Asからなり、これらが禁
制帯幅の狭いn −GaAsで形成されたn型ベース層
54aを挟む構造となっている。サイリスタがオンし、
高インピーダンス状態から低インピーダンス状態に移る
と、n型ベース層54aにキャリアが注入され、この部
分に閉じ込められる結果、光が生じる。トリガ光はn型
ベース層54aで吸収させるようにするので、この部分
の層厚は吸収長程度必要である。 GaAsの吸収長は
0.8μmの光で約1μmである。一方、ターンオフ時
間を短縮して応答速度を上げる点からはn型ベース層5
4aの層厚は薄い方が良い。サイリスタのターンオフ時
間τOFFは で表わせる。(1)式でτPはn型ベース層54aにお
ける少数キャリアである正孔の寿命、IPは導通時に流
れていた電流、I)Iは非導通時の電流である。τop
pを短縮するにはτeを減少する必要がある。τPはキ
ャリア密度を上げると小さくなる。従って、一定の注入
電流に対してはn型ベース層54aの層厚を薄くした方
がτPは小さくなり、それによってτOFFも短縮でき
る。従って、第5図に示した従来構造ではトリガ光の吸
収効率を上げたいという要求と応答を速くしたいという
二つの要求を同時に満足させることはできなかった。
This conventional example has a pnpn cyrisk structure. The anode region 53 and cathode region 55 are each p-AI
! GaAs and n-Al! It is made of G1As, and has a structure in which an n-type base layer 54a made of n-GaAs with a narrow forbidden band width is sandwiched therebetween. The thyristor turns on,
When the impedance state changes from the high impedance state to the low impedance state, carriers are injected into the n-type base layer 54a and are confined in this portion, thereby producing light. Since the trigger light is absorbed by the n-type base layer 54a, the layer thickness of this portion needs to be about the same as the absorption length. The absorption length of GaAs is about 1 μm for 0.8 μm light. On the other hand, from the point of view of shortening the turn-off time and increasing the response speed, the n-type base layer 5
The thinner the layer 4a, the better. The turn-off time τOFF of the thyristor can be expressed as τOFF. In equation (1), τP is the lifetime of holes, which are minority carriers, in the n-type base layer 54a, IP is the current flowing during conduction, and I) I is the current flowing during non-conduction. τop
To shorten p, it is necessary to reduce τe. τP becomes smaller as the carrier density is increased. Therefore, for a constant injection current, τP becomes smaller when the thickness of the n-type base layer 54a is made thinner, and thereby τOFF can also be shortened. Therefore, with the conventional structure shown in FIG. 5, it was not possible to simultaneously satisfy the two demands of increasing the absorption efficiency of the trigger light and increasing the response speed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のpnpn光サイリスタは、n型ベース層
が単一の半導体層で構成されているので、トリガ光の吸
収効率と応答速度の両方を向上させることができないと
いう欠点があった。
The above-mentioned conventional pnpn optical thyristor has the drawback that since the n-type base layer is composed of a single semiconductor layer, it is not possible to improve both the trigger light absorption efficiency and the response speed.

本発明の目的は、トリガ光の吸収効率及び応答速度の改
善されたpnpn光サイリスタを提供することにある。
An object of the present invention is to provide a pnpn optical thyristor with improved trigger light absorption efficiency and response speed.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のpnpn光サイリスタは、n型半導体からなる
アノード領域とn型半導体からなるカソード領域とで、
禁制帯幅が前記アノード領域及びカソード領域のそれ以
下の複数の半導体層からなるベース領域を挟んでなるp
npn光サイリスタにおいて、前記ベース領域は、発光
層及び禁制帯幅が前記発光層のそれ以上の半導体からな
り前記発光層と接合しているキャリア閉込め層を有し、
前記キャリア閉込め層の禁制帯幅が前記発光層から離れ
るに従って大きくなっているという構成を有している。
The pnpn optical thyristor of the present invention has an anode region made of an n-type semiconductor and a cathode region made of an n-type semiconductor.
p whose forbidden band width is sandwiched between a base region consisting of a plurality of semiconductor layers below the anode region and the cathode region;
In the npn optical thyristor, the base region includes a light emitting layer and a carrier confinement layer that is made of a semiconductor and whose forbidden band width is larger than that of the light emitting layer and is in contact with the light emitting layer;
The carrier confinement layer has a configuration in which the forbidden band width increases as the distance from the light emitting layer increases.

〔発明の作用〕[Action of the invention]

発光層と接合しているキャリア閉込め層の禁制帯幅が、
発光層から離れるに従って大きくなっている結果キャリ
アの発光層への注入と閉込めが効果的に行なわれるので
、発光層の厚さを薄くしないでも発光層内における少数
キャリアの寿命は小さくできる。
The forbidden band width of the carrier confinement layer that is in contact with the light emitting layer is
As a result of carriers increasing in size as they move away from the light-emitting layer, carriers can be effectively injected into the light-emitting layer and confined, so the lifetime of minority carriers in the light-emitting layer can be reduced without reducing the thickness of the light-emitting layer.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の主要部を示す半導体チップ
の断面図である。
FIG. 1 is a sectional view of a semiconductor chip showing the main parts of an embodiment of the present invention.

この実施例は、P −he □、3Ga、)、7Asか
らなるアノード領域13とn  Aj’ o、3Gao
、7Asからなるカソード領域15とで、禁制帯幅がア
ノード領域13及びカソード領域15のそれ以下の複数
の半導体層からなるベース領域を挟んでなるρnpn光
サイリスタにおいて、前述のベース領域は、n −Ga
Asからなる発光層14dと禁制帯幅が発光層14dの
それ以上のn−Aj’ zGa+−z^s(0≦Z≦0
43)からなり発光層14dと接合している第1、第2
のキャリア閉込め層14c、14eを有し、第1.第2
のキャリア閉込め層14c、14e(7)禁制帯幅は発
光層14dから離れるに従って大きくなっているという
ものである。
In this example, an anode region 13 consisting of P -he □, 3Ga, ), 7As and n Aj'o, 3Gao
, and a cathode region 15 made of 7As, sandwiching a base region made of a plurality of semiconductor layers whose forbidden band width is less than that of the anode region 13 and the cathode region 15. Ga
The light-emitting layer 14d made of As has a forbidden band width greater than that of the light-emitting layer 14d, n-Aj'zGa+-z^s (0≦Z≦0
43) and are connected to the light emitting layer 14d.
carrier confinement layers 14c and 14e, and the first. Second
The forbidden band width of the carrier confinement layers 14c and 14e (7) increases as the distance from the light emitting layer 14d increases.

なお、11はp −GaAsからなる半導体基板、12
はp −GaAsからなる厚さ0.5μmのバッファ層
である。アノード領域13は厚さ0.5μm。
Note that 11 is a semiconductor substrate made of p-GaAs, and 12 is a semiconductor substrate made of p-GaAs.
is a 0.5 μm thick buffer layer made of p-GaAs. The anode region 13 has a thickness of 0.5 μm.

不s4物濃度I X 1018cri3のpAN O,
3GaO−7As層からなり、第1.第2のキャリア閉
込め層14c、14eは厚さ0.5μm、’不純物濃度
1×10宜6c11−3のn −Aj? zGal、−
zAs層からなりZは発光層14d側で0.2、発光層
14 dから離れるに従って単調に0.3まで増加して
いる。発光層14dは厚さ0.1.4zn、不純物濃度
I X 10 l6cm−3のn −GaAs層からな
っている。14c、i4d。
pAN O of s4 substance concentration I x 1018cri3,
The first layer consists of 3GaO-7As layers. The second carrier confinement layers 14c and 14e have a thickness of 0.5 μm and an impurity concentration of 1×106c11-3 n −Aj? zGal,-
It is made of a zAs layer, and Z is 0.2 on the side of the light-emitting layer 14d, and increases monotonically to 0.3 as the distance from the light-emitting layer 14d increases. The light emitting layer 14d is made of an n-GaAs layer with a thickness of 0.1.4 zn and an impurity concentration of I x 10 l6 cm-3. 14c, i4d.

14eでn型ベース領域14aを構成しているわけであ
る。14bは厚さ0.05μm、不純物濃度5 X 1
0” cta−’のp −GaAs層からなるp型ベー
ス領域、15は厚さOjμm、不純物濃度1×1018
C11′−3のn −Aj’ o、Ga1)、7As層
からなるカソード領域、16は厚さ0.1μm、不純物
濃度5×10”Calづのn −GaAsからなるキャ
ップ層、17はAuGe−Niからなるカソード電極、
18はAuZnからなるアノード電極である。なおメサ
部は直径60μmの円柱状をなくしている。
14e constitutes the n-type base region 14a. 14b has a thickness of 0.05 μm and an impurity concentration of 5×1
A p-type base region 15 made of a p-GaAs layer with a thickness of 0"cta-', a thickness of Oj .mu.m, and an impurity concentration of 1.times.10.sup.18
C11'-3 n-Aj'o, Ga1), a cathode region made of a 7As layer, 16 a cap layer made of n-GaAs with a thickness of 0.1 μm and an impurity concentration of 5×10"Cal, 17 a AuGe- Cathode electrode made of Ni,
18 is an anode electrode made of AuZn. Note that the mesa portion does not have a cylindrical shape with a diameter of 60 μm.

第2図は実施例のエネルギーバンド図であるが、簡単の
ためにヘテロ接合でのバンド不連続等、本発明に関わり
ないところは定性的に近似を施して示しである。第2図
(a>は、外部からバイアス電圧が加わっていない状態
のエネルギーバンド図、第2図(b>は高インピーダン
ス状態のエネルギーバンド図、第2図(c)は低インピ
ーダンスでオン状態のエネルギーバンド図である。
FIG. 2 is an energy band diagram of the example, but for the sake of simplicity, portions that are not related to the present invention, such as band discontinuity at a heterojunction, are qualitatively approximated. Figure 2 (a) is an energy band diagram when no external bias voltage is applied, Figure 2 (b) is an energy band diagram in a high impedance state, and Figure 2 (c) is an energy band diagram in a low impedance and on state. It is an energy band diagram.

サイリスタがオンした後は、各pn接合は順方向にバイ
アスされた状態となる(第2図(c))。
After the thyristor is turned on, each pn junction becomes forward biased (FIG. 2(c)).

従来例のようにn型ベース領域が単一の半導体層で形成
されている場合には注入されたキャリアは拡散でこの中
に拡がっていく、一方、第2図(c)の様なバンド構造
が作られていると、内部に作り込まれたポテンシャル勾
配に沿ってキャリアはドリフトし、層厚の薄いn−Ga
As(14d)中に効率良く速やかに落ち込んでい(、
n型ベース領域の厚゛さはキャリアにとって実効上n 
−GaAs(14d)の厚さにほぼ等しいと考えてよい
わけである。又、トリガ光の波長は禁制帯幅で言ってA
/ yGal−wAs (w ) 0.2 )の程度に
しておけば吸収効率を下げることはない。
When the n-type base region is formed of a single semiconductor layer as in the conventional example, the injected carriers spread into the region by diffusion, but on the other hand, a band structure as shown in Fig. 2(c) When n-Ga is formed, carriers drift along the potential gradient built inside, and the thin n-Ga
It efficiently and quickly falls during As (14d) (,
The thickness of the n-type base region is effectively n for carriers.
- It can be considered that the thickness is approximately equal to the thickness of GaAs (14d). Also, the wavelength of the trigger light is A in terms of forbidden band width.
/yGal-wAs (w) 0.2), the absorption efficiency will not be lowered.

第3図は電流(I)−電圧(V)特性を定性的に示した
もので、右側の縦軸には光出力(Pa )を示しである
。バイアス電圧をV=Voに設定しておき、そこに適当
な強度のトリガ光を入れれば、サイリスタはオンする。
FIG. 3 qualitatively shows the current (I)-voltage (V) characteristics, and the vertical axis on the right side shows the optical output (Pa). If the bias voltage is set to V=Vo and a trigger light of appropriate intensity is applied thereto, the thyristor is turned on.

オンした後は順方向電流の増加と共に光出力が増大して
いく。
After turning on, the optical output increases as the forward current increases.

第4図はベース領域のキャリア濃度や層厚等のパラメー
タを定めるための特性設計図である。
FIG. 4 is a characteristic design diagram for determining parameters such as carrier concentration and layer thickness in the base region.

サイリスタの高インピーダンス状態から低インピーダン
ス状態への移行はn型ベース領域のパンチ・スルー電圧
72丁となだれ降伏電圧VBHによって決まる。n型ベ
ース領域が単一半導体層でできている場合、オン電圧は
、パンチ・スルー制限では、階段接合近似を用いると、 又、なだれ降伏制限では ■Bθ=Va  (1−αl−α ) 1/a  ・・
・(3)Va ”60 (Eg/l、1) ””(ND
/10 ”) −”’・・・(4) と書き表わせる。(2)〜(4)式で、NDはベース層
のキャリア濃度、dはベース層厚、′εSは誘電率・α
IIα2はそれぞれnpn、pnp)ランジスタの電流
利得、nは定数、E5は禁制帯幅エネルギーである。(
4)式ではE、、Noの単位はそれぞれe V 、 C
11−’である。第4図はベースがGaAsの場合に対
してオン電圧とキャリア濃度の関係を示したものである
0本発明ではオン電圧が第4図で示された値より若干、
高電圧側にシフトする。
The transition of the thyristor from a high impedance state to a low impedance state is determined by the punch-through voltage 72 of the n-type base region and the avalanche breakdown voltage VBH. If the n-type base region is made of a single semiconductor layer, the on-voltage is: For the punch-through limit, using the step junction approximation, and for the avalanche breakdown limit, ■Bθ=Va (1−αl−α) 1 /a...
・(3) Va “60 (Eg/l, 1)” (ND
/10 ”) −”'...(4) It can be written as: In equations (2) to (4), ND is the carrier concentration of the base layer, d is the base layer thickness, and ′εS is the dielectric constant α
IIα2 is the current gain of the transistor (npn, pnp, respectively), n is a constant, and E5 is the forbidden band energy. (
4) In the formula, the units of E, and No are e V and C, respectively.
11-'. FIG. 4 shows the relationship between on-voltage and carrier concentration for the case where the base is GaAs. In the present invention, the on-voltage is slightly higher than the value shown in FIG.
Shift to high voltage side.

前述した実施例ではオン電圧はn型ベース領域14aの
パンチスルーでほぼ決まり、約6Vであった。応答速度
としては100MIIzのスピードで動作させることが
できる。
In the embodiment described above, the on-voltage was approximately determined by the punch-through of the n-type base region 14a, and was approximately 6V. As for the response speed, it can be operated at a speed of 100 MIIz.

以上の実施例では層厚方向に出力光を得たが、層厚と垂
直方向にへき開面を形成してやれば、長手方向に発光を
得ることも可能で、応用上有利である。
In the above embodiments, output light was obtained in the layer thickness direction, but if cleavage planes are formed in a direction perpendicular to the layer thickness, it is also possible to obtain light emission in the longitudinal direction, which is advantageous in terms of application.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、発光層にヘテロ接合を設
けることにより、キャリアの注入、閉込め作用がよくな
る結果、トリガ光の吸収効率を下げることなく速い応答
が可能なpnpn光サイリスタが得られる効果がある。
As explained above, in the present invention, by providing a heterojunction in the light-emitting layer, carrier injection and confinement effects are improved, and as a result, a pnpn optical thyristor that can respond quickly without reducing trigger light absorption efficiency can be obtained. effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の主要部を示す半導体チップ
の断面図、第2図(a)は一実施例のバイアス電圧が加
わっていない状態のエネルギーバンド図、第2図(b)
は同じく高インピーダンス状態のエネルギーバンド図、
第2図(C)は同じく低インピーダンス状態のエネルギ
ーバンド図、第3図は一実施例の電圧−電流特性と光出
力の関係を示す特性図、第4図は特性設計図、第5図は
従来例を示す半導体チップの断面図である。
FIG. 1 is a cross-sectional view of a semiconductor chip showing the main parts of an embodiment of the present invention, FIG. 2(a) is an energy band diagram of the embodiment with no bias voltage applied, and FIG. 2(b)
is also the energy band diagram in the high impedance state,
Figure 2 (C) is an energy band diagram in the same low impedance state, Figure 3 is a characteristic diagram showing the relationship between voltage-current characteristics and optical output of one embodiment, Figure 4 is a characteristic design diagram, and Figure 5 is FIG. 2 is a cross-sectional view of a semiconductor chip showing a conventional example.

Claims (1)

【特許請求の範囲】[Claims] p型半導体からなるアノード領域とn型半導体からなる
カソード領域とで、禁制帯幅が前記アノード領域及びカ
ソード領域のそれ以下の複数の半導体層からなるベース
領域を挟んでなるpnpn光サイリスタにおいて、前記
ベース領域は、発光層及び禁制帯幅が前記発光層のそれ
以上の半導体からなり前記発光層と接合しているキャリ
ア閉込め層を有し、前記キャリア閉込め層の禁制帯幅が
前記発光層から離れるに従って大きくなっていることを
特徴とするpnpn光サイリスタ。
In the pnpn optical thyristor, an anode region made of a p-type semiconductor and a cathode region made of an n-type semiconductor sandwich a base region made of a plurality of semiconductor layers whose forbidden band width is less than that of the anode region and the cathode region. The base region includes a light emitting layer and a carrier confinement layer which is made of a semiconductor and whose forbidden band width is larger than that of the light emitting layer and is in contact with the light emitting layer, and the forbidden band width of the carrier confinement layer is greater than that of the light emitting layer. A pnpn optical thyristor, characterized in that the size of the pnpn optical thyristor increases as the distance from the pnpn optical thyristor increases.
JP30703386A 1986-12-22 1986-12-22 pnpn optical thyristor Expired - Lifetime JPH079997B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP30703386A JPH079997B2 (en) 1986-12-22 1986-12-22 pnpn optical thyristor
DE8787118935T DE3782232T2 (en) 1986-12-22 1987-12-21 PNPN THYRISTOR.
CA000554905A CA1271549A (en) 1986-12-22 1987-12-21 Pnpn thyristor
EP87118935A EP0273344B1 (en) 1986-12-22 1987-12-21 A pnpn thyristor
US07/136,588 US4829357A (en) 1986-12-22 1987-12-22 PNPN thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30703386A JPH079997B2 (en) 1986-12-22 1986-12-22 pnpn optical thyristor

Publications (2)

Publication Number Publication Date
JPS63158883A true JPS63158883A (en) 1988-07-01
JPH079997B2 JPH079997B2 (en) 1995-02-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP30703386A Expired - Lifetime JPH079997B2 (en) 1986-12-22 1986-12-22 pnpn optical thyristor

Country Status (1)

Country Link
JP (1) JPH079997B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05119357A (en) * 1991-10-28 1993-05-18 Nec Corp Optical matrix switch

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5548466A (en) * 1978-10-04 1980-04-07 Toshiba Corp Pressure-feed injection furnace on direct current feed system
JPS6127088A (en) * 1984-07-14 1986-02-06 新光金属株式会社 Cooking or drinking vessel

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5548466A (en) * 1978-10-04 1980-04-07 Toshiba Corp Pressure-feed injection furnace on direct current feed system
JPS6127088A (en) * 1984-07-14 1986-02-06 新光金属株式会社 Cooking or drinking vessel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05119357A (en) * 1991-10-28 1993-05-18 Nec Corp Optical matrix switch

Also Published As

Publication number Publication date
JPH079997B2 (en) 1995-02-01

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