JPH079997B2 - pnpn optical thyristor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a pnpn optical thyristor used as a semiconductor optical memory required for image processing, optical logic operation and the like.

[Conventional technology]

A semiconductor optical memory that has the function of changing its internal state by a slight trigger light and starting to emit light and continuing to emit light even after the trigger light disappears is indispensable for future optical switching and parallel information processing systems. It is a key device.

FIG. 5 is a sectional view of a conventional example of a semiconductor optical memory described in Journal of Applied Physics, Volume 59, pages 596 to 600, 1986.

This conventional example has a pnpn thyristor structure. The anode region 53 and the cathode region 55 are p-AlGaAs and n-, respectively.
It is made of AlGaAs and has a structure sandwiching an n-type base layer 54a made of n-GaAs having a narrow band gap. When the thyristor is turned on and the state changes from the high impedance state to the low impedance state, carriers are injected into the n-type base layer 54a and are confined in this portion, so that light is generated. Since the trigger light is absorbed by the n-type base layer 54a, the thickness of this portion needs to be about the absorption length. GaAs
Has an absorption length of about 1 μm at 0.8 μm of light. On the other hand, from the viewpoint of shortening the turn-off time and increasing the response speed, it is preferable that the layer thickness of the n-type base layer 54a is thin. The turn-off time τ _{OFF of the} thyristor is Can be expressed as In the formula (1), τ _P is the life of holes which are minority carriers in the n-type base layer 54a, I _F is the current flowing during conduction, and I _H is the current during non-conduction. To shorten τ _OFF , it is necessary to reduce τ _P. τ _P becomes smaller as the carrier density is increased. Therefore, for a constant injection current, τ _P becomes smaller when the layer thickness of the n-type base layer 54a is made smaller, so that τ _OFF can also be shortened. Therefore, the conventional structure shown in FIG. 5 cannot simultaneously satisfy the two requirements of increasing the absorption efficiency of the trigger light and speeding up the response.

[Problems to be solved by the invention]

The above-described conventional pnpn optical thyristor has a drawback in that both the absorption efficiency of trigger light and the response speed cannot be improved because the n-type base layer is composed of a single semiconductor layer.

An object of the present invention is to provide a pnpn optical thyristor with improved absorption efficiency of trigger light and improved response speed.

[Means for solving problems]

In the pnpn optical thyristor of the present invention, an anode region made of a p-type semiconductor and a cathode region made of an n-type semiconductor sandwich a base region made of a plurality of semiconductor layers having a forbidden band width smaller than the anode region and the cathode region. In the pnpn optical thyristor of the type having no gate electrode, the base region has a light-emitting layer and a carrier confinement layer which is made of a semiconductor having a forbidden band width larger than that of the light-emitting layer and joined to the light-emitting layer. The forbidden band width of the carrier confinement layer increases with increasing distance from the light emitting layer, and the light emitting layer also serves as an absorption layer for trigger light.

[Operation of the invention]

The forbidden band width of the carrier confinement layer joined to the light emitting layer is
As the distance from the light emitting layer increases, the carriers are effectively injected and confined in the light emitting layer. Therefore, even if the thickness of the light emitting layer is not reduced, the life of minority carriers in the light emitting layer can be shortened.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a main part of an embodiment of the present invention.

This example shows an anode region made of p-Al _0.3 Ga _0.7 As
13 and a cathode region 15 made of n-Al _0.3 Ga _0.7 As, which has no gate electrode and has a forbidden band width sandwiching a base region made of a plurality of semiconductor layers having an anode region 13 and a cathode region 15 or less. In the pnpn optical thyristor, the above-mentioned base region has a light emitting layer 14d made of n-GaAs and an n-Al _z Ga _1-z As (0 ≦ z ≦ 0.3) whose forbidden band width is larger than that of the light emitting layer 14d.
Which has first and second carrier confinement layers 14c and 14e which are joined to the light emitting layer 14d.
The forbidden band width of 4c and 14e increases with increasing distance from the light emitting layer 14d, and the light emitting layer 14d also serves as an absorption layer for trigger light.

In addition, 11 is a semiconductor substrate made of p-GaAs, and 12 is p-GaAs.
Is a buffer layer having a thickness of 0.5 μm. The anode region 13 has a thickness of 0.5 μm and an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ of p-Al _0.3.
Ga _0.7 As layer, first and second carrier confinement layers 14c, 1
4e is n-Al _z Ga with a thickness of 0.5 μm and an impurity concentration of 1 × 10 ¹⁶ cm ^-3.
_It is composed of a _1-z As layer, and z is 0.2 on the side of the light emitting layer 14d, and monotonically increases to 0.3 with increasing distance from the light emitting layer 14d. Light emitting layer 14d
Is an n-GaAs layer having a thickness of 0.1 μm and an impurity concentration of 1 × 10 ¹⁶ cm ^-3 . The n-type base region 14a is composed of 14c, 14d and 14e. 14b has a thickness of 0.05 μm and an impurity concentration of 5
× 10 ¹⁷ cm ^-3 p-type base region consisting of p-GaAs layer, 15 has a thickness of 0.3 μm, and impurity concentration is 1 × 10 ¹⁸ cm ^-3 n-Al _0.3 Ga _0.7 A
Cathode region composed of s layer, 16 is a cap layer composed of n-GaAs having a thickness of 0.1 μm and impurity concentration of 5 × 10 ¹⁸ cm ⁻³ , and 17 is AuGe
A cathode electrode made of -Ni and an anode electrode 18 made of AuZn. The mesa portion does not have a cylindrical shape with a diameter of 60 μm.

FIG. 2 is an energy band diagram of the example, but for simplicity, band discontinuities at the heterojunction and the like, which are not related to the present invention, are qualitatively approximated. 2 (a) is an energy band diagram in a state where no bias voltage is applied from the outside, FIG. 2 (b) is an energy band diagram in a high impedance state, and FIG. 2 (c) is a low impedance and on state. It is an energy band figure. After the thyristor turns on, each pn junction is forward biased. (FIG. 2 (c)). N as in the conventional example
If the mold base region is formed of a single semiconductor layer, the injected carriers will diffuse and spread therein.
On the other hand, when a band structure as shown in FIG. 2 (c) is created, carriers drift along the potential gradient built in the inside, and efficiently move into n-GaAs (14d) with a thin layer thickness. Immediately depressed. It can be considered that the thickness of the n-type base region is substantially equal to the thickness of n-GaAs (14d) for the carrier. Further, if the wavelength of the trigger light is set to Al _w Ga _1-w As (w> 0.2) in terms of the forbidden band, the absorption efficiency will not be lowered.

FIG. 3 qualitatively shows the current (I) -voltage (V) characteristics, and the light output (P ₀ ) is shown on the right vertical axis. If the bias voltage is set to V = V ₀ and driga light having an appropriate intensity is put therein, the thyristor turns on. After turning on, the light output increases with an increase in the forward current.

FIG. 4 is a characteristic design diagram for determining parameters such as carrier concentration and layer thickness of the base region.

The transition from the high impedance state of the thyristor to the low impedance state is the punch-through voltage of the n-type base region.
Determined by V _PT and avalanche breakdown voltage V _B1 . When the n-type base region is made of a single semiconductor layer, the on-voltage is, in punch-through limitation, using the step junction approximation, In the case of avalanche yield limitation, V _BO = V _B (1-α ₁ −α ₂ ) ^{1 / n} … (3) V _B 60 (E _g /1.1) ^3/2 (N _D / 10 ¹⁶ ) ^-3/4 It can be written as (4). In the equations (2) to (4), N _D is the carrier concentration of the base layer, d is the base layer thickness, ε _s is the dielectric constant, α ₁ ,
α ₂ is the current gain of the npn and pnp transistors, n is a constant, and E _g is the band gap energy. In equation (4)
The units of E _g and N _D are eV and cm ^-3 , respectively. FIG. 4 shows the relationship between the on-voltage and the carrier concentration when the base is GaAs. In the present invention, the ON voltage is slightly shifted to the high voltage side from the value shown in FIG.

In the above-described embodiment, the on-voltage is about 6V, which is almost determined by punch-through of the n-type base region 14a. The response speed can be 100MHz.

In the above embodiments, output light was obtained in the layer thickness direction, but if a cleavage plane is formed in the direction perpendicular to the layer thickness, it is possible to obtain light emission in the longitudinal direction, which is advantageous in application.

〔The invention's effect〕

As described above, according to the present invention, by providing a heterojunction in the light emitting layer, carrier injection and confinement functions are improved, and as a result, a pnpn optical thyristor capable of quick response without lowering the absorption efficiency of trigger light can be obtained. effective.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing a main part of one embodiment of the present invention, FIG. 2 (a) is an energy band diagram of one embodiment in which a bias voltage is not applied, and FIG. 2 (b).
Is also the energy band diagram of the high impedance state,
FIG. 2 (c) is an energy band diagram of the same low impedance state, FIG. 3 is a characteristic diagram showing the relationship between the voltage-current characteristic and the optical output of one embodiment, FIG. 4 is a characteristic design diagram, and FIG. It is sectional drawing of the semiconductor chip which shows a prior art example. 11, 51 ... Semiconductor substrate, 12, 52 ... Buffer layer, 13, 53 ... Anode region, 14, 54 ... Base region, 14a, 54a ... N-type base region, 14b, 54b ... P-type base layer, 14c ... First Carrier confinement layer, 14d ... Emissive layer, 14e ... Second carrier confinement layer, 1
5,55 ... Cathode region, 16,56 ... Cap layer, 17,57 ... Cathode electrode, 18,58 ... Anode electrode.

Claims (1)

[Claims] 1. A gate having an anode region made of a p-type semiconductor and a cathode region made of an n-type semiconductor sandwiching a base region made of a plurality of semiconductor layers having a forbidden band width smaller than that of the anode region and the cathode region. Type pn without electrode
In the pn optical thyristor, the base region has a light emitting layer and a carrier confinement layer which is made of a semiconductor having a forbidden band width larger than that of the light emitting layer and is joined to the light emitting layer. A pnpn optical thyristor, wherein the band width increases with increasing distance from the light emitting layer, and the light emitting layer also serves as an absorption layer for trigger light.