JPS63157950U - - Google Patents

Info

Publication number
JPS63157950U
JPS63157950U JP5141787U JP5141787U JPS63157950U JP S63157950 U JPS63157950 U JP S63157950U JP 5141787 U JP5141787 U JP 5141787U JP 5141787 U JP5141787 U JP 5141787U JP S63157950 U JPS63157950 U JP S63157950U
Authority
JP
Japan
Prior art keywords
lead
foil
semiconductor wafer
mentioned
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5141787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5141787U priority Critical patent/JPS63157950U/ja
Publication of JPS63157950U publication Critical patent/JPS63157950U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の実施例の外装被覆を除いた
平面図及びＸ―Ｘ線に沿う外装被覆を含む断面図
、第２図は従来の半導体素子の平面図及び側面図
、第３図は第２図示の素子を使用した装置の平面
図、第４図は同装置の側面図である。 １……アルミニウム基板、２……絶縁物層、３
〜５……銅箔、３ａ〜５ａ……端子部、３ｂ〜５
ｂ……リード部、４ｃ……ウエハ支持部、６……
半導体ウエハ、７及び８……リード線、９……外
装被覆。 Fig. 1 is a plan view of an embodiment of this invention excluding the outer covering and a sectional view including the outer covering taken along line X--X, Fig. 2 is a plan view and side view of a conventional semiconductor element, and Fig. 3 is a FIG. 2 is a plan view of a device using the illustrated element, and FIG. 4 is a side view of the device. 1... Aluminum substrate, 2... Insulator layer, 3
~5...Copper foil, 3a~5a...Terminal section, 3b~5
b...Lead part, 4c...Wafer support part, 6...
Semiconductor wafer, 7 and 8...Lead wire, 9...Exterior coating.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 金属基板面に被着した絶縁物層上に、端子部及
びリード部からなる導体箔の複数個を形成し、そ
の導体箔の少くとも１個のリード部の先端にウエ
ハ支持部を拡大形成し、このウエハ支持部上に半
導体ウエハを取付け、この半導体ウエハの表面電
極をリード線を用いて他の導体箔のリード部に結
線し、少くとも上記端子部を残して上記絶縁物層
と上記導体箔の残部と上記半導体ウエハとを絶縁
性合成樹脂によつて外装被覆してなる半導体装置
。 A plurality of conductive foils each consisting of a terminal portion and a lead portion are formed on an insulating layer adhered to a metal substrate surface, and a wafer support portion is enlarged and formed at the tip of at least one lead portion of the conductive foil. , a semiconductor wafer is mounted on this wafer support, and the surface electrode of this semiconductor wafer is connected to the lead part of another conductor foil using a lead wire, and the above-mentioned insulating layer and the above-mentioned conductor are connected, leaving at least the above-mentioned terminal part. A semiconductor device formed by covering the remaining portion of the foil and the semiconductor wafer with an insulating synthetic resin.
JP5141787U 1987-04-03 1987-04-03 Pending JPS63157950U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5141787U JPS63157950U (en) 1987-04-03 1987-04-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5141787U JPS63157950U (en) 1987-04-03 1987-04-03

Publications (1)

Publication Number Publication Date
JPS63157950U true JPS63157950U (en) 1988-10-17

Family

ID=30875655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5141787U Pending JPS63157950U (en) 1987-04-03 1987-04-03

Country Status (1)

Country Link
JP (1) JPS63157950U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4732602U (en) * 1971-04-22 1972-12-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4732602U (en) * 1971-04-22 1972-12-12

Similar Documents

Publication Publication Date Title
JPS63157950U (en)
JPH01152491U (en)
JPS6395271U (en)
JPH02114943U (en)
JPS6294673U (en)
JPH01146559U (en)
JPH0269379U (en)
JPH0333912U (en)
JPH01137523U (en)
JPS6282736U (en)
JPH0217848U (en)
JPS61188214U (en)
JPS6240846U (en)
JPH0485610U (en)
JPS62160556U (en)
JPS6223439U (en)
JPS6260024U (en)
JPS60121222U (en) insulated wire
JPS62107436U (en)
JPS5923728U (en) composite electronic components
JPH0160525U (en)
JPS6184628U (en)
JPS61146977U (en)
JPS62116543U (en)
JPS63131170U (en)