JPS63157508A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To lower an oscillation frequency and to save power consumption, by providing a constant current generating means between a power source potential supplier and a self-exciting oscillation circuit in which the output of an inverter at the final stage of plural cascade-connected inverters is feedback-connected to the input of the inverter at the first stage. CONSTITUTION:The plural inverters I1-I5 are cascade-connected, and the self-exciting oscillation circuit is constituted by connecting the output of the inverter I5 to the input of the inverter I1, and an N-channel MOSFET Q1 is connected between the common contact Nl of the load use N-channel MOSFETs Q11-Q51 of the inverters I1-I5 and a power source VCC. The gate of the FETQ1 is connected to a resistor R1 between the power source VCC and an earth power source VSS, and the connection point of a Zener diode D1. When the potential of the power source VCC rises, the conduction resistance of the FETQ1 is increased by that share, and a current being permitted to flow from the power source VCC to the common contact N1 becomes constant invariably, then, the potential of the contact N1 is lowered. In such way, the oscillation frequency is set at a low level, and also, a stable oscillation frequency can be obtained even when a voltage fluctuates, and the power consumption of an integrated circuit in a standby state can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit equipped with an automatic oscillation circuit.

(Prior Art) In semiconductor integrated circuits, self-excited oscillation circuits are often used in substrate potential generation circuits, chip internal booster circuits, and the like.

For example, as shown in FIG. 5, the self-excited oscillation circuit includes N-channel type MOS transistors Q11 for each load.
~Qnl and driving N-channel type MOS transistors 012~Qn2 inverter circuits 11~in are connected in cascade in an odd number of stages. stage inverter n
It consists of a circuit in which positive feedback is applied to the first stage inverter 1.

The oscillation frequency of such a self-help oscillation circuit can be set by the dimension ratio between the load transistor and the driving transistor in each inverter 11 to ln, and the number of stages of cascade-connected inverters.

Most of the power consumed during standby of a semiconductor integrated circuit is due to the operation of the substrate potential generation circuit and the chip internal booster circuit. The power consumed by these substrate potential generation circuits and chip internal booster circuits largely depends on the oscillation frequency of a self-help oscillation circuit as shown in FIG. 5 provided inside these circuits.

Furthermore, the oscillation frequency of the self-excited oscillation circuit increases as the power supply Vcc, which is commonly supplied to one end and the gate of the load transistors Q11 to Qn1, increases.
As cc increases, power consumption during standby also increases.

Therefore, in order to reduce such power consumption during standby of a semiconductor integrated circuit, the oscillation frequency of the self-excited oscillation circuit should be lowered within a range that does not interfere with the operation of the substrate potential generation circuit and the chip internal booster circuit. At the same time, it is necessary to reduce the dependence of this oscillation frequency on the power supply voltage.

In order to lower the excavation frequency, conventionally an inverter ■
Methods such as setting the channel width W/channel length of each load transistor Q11 to Qnl of 1 to 1 inch to be small, increasing the number of stages of cascade-connected inverters, or adding capacitance between each inverter, etc. is used.

However, W of the load transistors Q11 to Qnl
In the method of reducing /L, the minimum channel width is limited due to process reasons, so the channel length must be increased in order to reduce W/L. Furthermore, when the W/L of the load transistors Q11 to Qn1 is set small in this way, the inverters 11 to l
In order to optimize each circuit threshold value of n, it is necessary to set the W/L of the driving transistors 012 to Qn2 to be large. Therefore, although the excavation frequency can be lowered, the pattern area of the circuit will increase.

In the method of increasing the number of inverter stages connected in cascade,
In addition to an increase in the pattern area, the through current from the power supply ycc to the ground power supply VSS increases, resulting in an increase in the power consumed by the oscillation circuit itself.

Furthermore, even with the method of loading a capacitor to each node between the inverters 11 to 1, an increase in area and an increase in power consumption of the oscillation circuit itself due to charging and discharging of the capacitor cannot be avoided.

Furthermore, the dependence of the excavation frequency on the power supply voltage cannot be completely eliminated by these methods.

(Problems to be Solved by the Invention) This invention has been made in view of the above points.In conventional semiconductor integrated circuits, the oscillation frequency of the self-excited oscillation circuit increases at a low power supply voltage, resulting in power consumption. In addition, in order to obtain a low excavation frequency even when the power supply voltage is not high, the area and power consumption of the oscillation circuit itself will increase. To provide a semiconductor integrated circuit that consumes less power during standby by allowing the excavation frequency to be set low without increasing the area and power consumption of the circuit itself.

[Structure of the Invention] (Means and Effects for Solving the Problems) The semiconductor integrated circuit according to the present invention is composed of a plurality of inverters connected in cascade, and the output terminal of the inverter in the final stage is connected to the inverter in the first stage. A self-excited oscillation circuit that is feedback-connected to an input terminal, and a constant current generating means that is provided between the self-excited oscillation circuit and a power supply potential supply terminal and generates a constant current for driving the oscillation circuit. This is what I did.

In the semiconductor integrated circuit having such a configuration, the delay time in each inverter is made substantially constant by the constant current generating means regardless of fluctuations in the voltage, so that a stable excavation frequency can be obtained. Furthermore, it is possible to easily obtain a low oscillation frequency due to the voltage drop caused by the constant current generating means.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit according to an embodiment of the present invention, and this semiconductor integrated circuit has five stages of inverters connected in cascade! A self-excited oscillation circuit consisting of circuit elements 1 to I5, a resistor R1, a Zener diode D1, and an N-channel MoS transistor Q1 are provided.

One end of the N-channel type MOS transistor Q1 is connected to the power supply VCC, and the other end is connected to the inverter 1.
N-channel type MOS transistor Q for load from 1 to I5
It is commonly connected to one end of each of Q11 to Q51.

Further, its gate is connected to a connection point between a resistor R1 and a Zener diode D1, which are connected in series between a power supply vCC and a ground power supply Vss. The resistor R1 and the Zener diode D1 constitute a constant voltage generation source.

Therefore, as the potential of power supply ycc rises, the conduction resistance of transistor Q1 increases accordingly.
The current flowing from is constant.

Note that the constant voltage generation source is not limited to such a circuit, and may be any circuit that supplies a constant voltage.

Since the oscillation frequency of the self-excited oscillation circuit depends on the potential of the connection point N1, setting the dimensions of the transistor Q1,
Alternatively, the oscillation frequency can be set to an arbitrary low value by setting the value of the constant voltage supplied to the gate of the transistor Q1.

FIG. 2 shows how the oscillation frequency of the self-excited oscillation circuit changes when the dimensions of the transistor Q1 are changed.

In this way, the oscillation frequency can be set low by setting the channel width/channel length of the transistor Q1 small, so the desired oscillation frequency can be achieved without making the channel lengths of the load transistors Q11 to Q51 too large as described above. It becomes possible to obtain.

Furthermore, as shown in FIG. 3, the oscillation frequency of the self-excited oscillation circuit remains approximately constant regardless of fluctuations in the voltage m V cc. This is because, as mentioned above, even if the potential of the power supply Vcc rises, the potential of the connection point N1 remains the same as that of the transistor Q1.
, resistor R1, and Zener diode D1 to maintain a constant potential.

FIG. 4 shows another embodiment of the present invention. In this semiconductor integrated circuit, a CMOS inverter 101 consisting of P-channel type MOS transistors Tpl to Tp5 and N-channel type MoS transistors Tn1 to Tn5 is shown.
~105 constitute a self-excited oscillation circuit.

Furthermore, each of the P-channel type MOS transistors Tp1
A P-channel MO8 transistor Q2 is connected between the common connection point N2 of ~Tp5 and the power supply VCC, and a Zener diode connected in series with the polarity shown between the power supply VCC and the earth power supply VSS is connected to the gate of this transistor Q2. Which connection point between D2 and resistor R2 is connected.

Even with such a configuration, the potential of the connection point N2 is set to the power supply VO.
Since the potential is lower than the potential of C and can be held constant regardless of fluctuations in the power supply VCC, the same effect as the circuit shown in FIG. 1 can be obtained.

Furthermore, it is also possible to use bipolar transistors in place of the MOS transistors Q1 and Q2 shown in FIGS. 1 and 4.

[Effects of the Invention] As described above, according to the present invention, the oscillation frequency of the self-excited oscillation circuit can be set low without increasing the circuit area.
Moreover, a stable oscillation frequency can be obtained regardless of fluctuations in the power supply voltage. Therefore, it is possible to effectively reduce the power consumption of the semiconductor integrated circuit during standby.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram illustrating a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a self-excited generator when the dimensions of the transistor used in the constant current generating means of the semiconductor integrated circuit are changed. FIG. 3 is a diagram showing how the oscillation frequency changes when the power supply voltage changes; FIG. 4 is a circuit configuration diagram illustrating another embodiment of the present invention; FIG. 5 is a circuit configuration diagram illustrating a conventional semiconductor integrated circuit. ■1~I5...Inverter, R1...Resistor, Dl.
...Zener diode, Ql...N channel type M
OS transistor. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (3)

[Claims] (1) A self-excited oscillation circuit consisting of a plurality of cascaded inverters, in which the output terminal of the final stage inverter is feedback-connected to the input terminal of the first-stage inverter, and this self-excited oscillation circuit and the power supply potential supply terminal. 1. A semiconductor integrated circuit comprising: a constant current generating means provided between the oscillator circuit and a constant current generating means for generating a constant current for driving the oscillation circuit. (2) The constant current generating means includes a constant voltage generating source, a transistor having a current path connected between the power supply potential supply terminal and the power supply side terminal of each inverter, and having a gate connected to the constant voltage generating source. A semiconductor integrated circuit according to claim 1, characterized in that it is comprised of: (3) The constant voltage generation source includes a load element and a constant voltage element connected in series between the power supply potential supply end and the reference potential supply end. The semiconductor integrated circuit according to item 2.