JPS63157363A - Signal discriminating circuit - Google Patents

Abstract

PURPOSE:To surely and easily discriminate input signals by producing the synchronizing, switching and error signals based on the basic signals corresponding to different input signals as well as these input signals and discriminating the changes of input signals from the synchronizing and switching signals to switch the basic signals. CONSTITUTION:The digital input signal DS is inputted to a demodulation circuit 13 and this circuit 13 produces a switching signal LR from a synchronizing signal NSC and a master clock signal MC received from a PLL circuit 12. A phase difference detecting circuit receives the signals SNC and LR from the circuit 13 and detects the phase difference between these two signals caused by the change of the signal DS to send it to a switching circuit 15. The circuit 15 performs the switching between vibrators 16 and 17 via a changeover switch 15a and then switches a 1st MC signal MC1 received from the circuit 12 to a 2nd MC signal MC2 to supply it to the circuit 13. The circuit 13 compares the frequency divided MC signals with the sampling frequency Fa2 of a 2nd signal input DS. The circuit 12 secures coincidence between the MC2 and the Fa2 based on the error signal obtained from said comparison. when this coincidence is secured, the signal MC is produced with high stability.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal discrimination circuit, and more particularly to a signal discrimination circuit suitably implemented for frequency discrimination and switching of sampling signals in a digital audio system.

Background Art Information recorded on a recording medium such as a compact disc (so-called CD) or digital audio tape (so-called DAT) is used as a signal source, and this is transferred to and recorded on a recording medium such as a cassette tape. ,
In order to improve recording characteristics such as signal-to-noise ratio and maintain high fidelity when performing so-called ``grabbing'' operations, a direct digital recording method is used in which the digital signal of the signal source is directly recorded as a digital signal on the recording side. It will be done.

When transmitting an information signal to the recording side based on a digital signal in this way, the recording side must record the transmitted content at the same sampling frequency as the sampling frequency of the signal source, and the sampling frequency is different from that of the recording medium. For example, compact disc (CD)
So 44,1. kHz.

Also, for digital audio tape (DA, T), 48
Various frequencies are used, such as kHz. Therefore, on the recording side, if the recording medium of the signal source is different, the sampling frequency must be set correspondingly. For this reason, a signal discrimination circuit is used to discriminate the sampling frequency of the signal source from the digital signal input and to set its own sampling frequency.

FIG. 4 is a block diagram showing the electrical configuration of the signal tlI separate circuit 1 according to the prior art. A digital input signal DS from a first signal source (not shown) is connected to a line 11.
via the demodulator 11t! ! 2, input to the first bandpass filter 3 and the second bandpass filter 4. 1st
The center frequencies of the bandpass filter 3 and the second bandpass filter 4 correspond to the first sampling frequency Fsl based on the vJ1 signal source and the second sampling frequency Fs2 based on the second signal source, and the center frequencies of the frequency Fsl or Fs2 are based on the second signal source.
s2 is #IJ1 band pass filter 3 or second
Selected by bandpass filter 4, either signal is on line J! 2nd line! Switching circuit 5 through 3
is input.

The switching circuit 5 thereby switches between its own built-in changeover switch 5.
A is driven and switched to the side corresponding to one of the sampling frequencies Fsl+Fs2, and one of the oscillators 6 and 7 realized by a crystal oscillator or the like is connected to the PLL circuit 8. P
The L L circuit 8 has an oscillation circuit (not shown) inside thereof, and transmits a master clock signal MC having a frequency determined by the oscillator 6+7 to the line! 4 to the clock input terminal of the demodulation circuit 2.

The demodulation circuit 2 converts the digital input signal DS to the synchronization signal SN.
C, master clock signal MC and synchronization signal SN
From C, various tarok signals necessary for the operation of the recording side equipment (not shown), such as the switching signal LR necessary for anotal/analog conversion, are created, and these are sent to line nos. 4 and 15.
The data is output to the recording device via the . Furthermore, the frequency error between the digital input signal DS and the master clock signal MC of the PLL circuit 8 is detected, and the error signal ER is sent to the PLL circuit 8 via the line 15, whereby the PLL circuit 8 corrects its own oscillation frequency. The master clock signal MC is held constant in accordance with the digital input signal DS.

When the signal source changes from one signal source to the other, the selection of the bandpass filters 3 and 4 changes h9 and the PLL circuit 8.
The six master clock signals MC to which the vibrators 6 and 7 connected are switched also naturally switch from one frequency to the other, corresponding to changes in the digital input signal DS. In this way, in the prior art, changes in the sampling frequencies Fsl and Fs2 of the digital input signal DS from the signal source are selectively determined using the bandpass filter 3.4, and the vibrations connected to the PLL circuit 8 are determined depending on the magnitude of the output level. Switch children 6 and 7,
Setting the own sampling frequency.

Problems to be Solved by the Invention However, the use of a bandpass filter for signal detection as in the prior art increases the scale of the discrimination circuit including the bandpass filter, complicates the circuit, and increases the number of parts. This has been an obstacle to reducing production costs and downsizing equipment. Therefore, a signal discrimination circuit that operates reliably with a simple circuit configuration has been desired.

The present invention has been made in view of the above problems, and includes:
Means for Solving 6 Problems An object of the present invention is to provide a signal discriminating circuit realized by a simple circuit configuration. basic signal generating means for individually generating basic signals corresponding to different types of input signals;
Fj and error signal generation means; phase difference detection means for detecting the phase difference between the synchronization signal and the switching signal; and a change in the input signal determined by the output of the phase difference detection means, and the basic signal is detected as the input signal. The present invention is a signal discrimination circuit characterized by comprising a switching means for switching in response to a signal.

According to the present invention, basic signals corresponding to at least two types of input signals of different frequencies are created, and a synchronization signal, a switching signal, and an error signal are created based on the input signals and the basic signal.

Means for detecting the phase difference between the synchronizing signal and the switching signal is provided, and a change in the input signal is determined based on the output thereof, and the basic signal is made to correspond to the input signal by the switching means (the circuit is switched).

Embodiment FIG. 1 is a block diagram showing the electrical configuration of a signal discrimination circuit 11 according to an embodiment of the present invention. The signal discrimination circuit 11 is
a PLL circuit 12 as a means for individually creating basic signals corresponding to two types of digital input signals;
A demodulation circuit 13 is a means for creating a synchronization signal, a switching signal and an error signal based on an input signal and a basic signal, a phase difference detection circuit 14 is a means for detecting a phase difference between the synchronization signal and a switching signal, and It operates based on the output of the phase difference detection circuit 14, and includes a switching circuit 15 as switching means for switching the vibrator 1f3.17 attached to the PLL circuit 12 so that the basic signal corresponds to the input signal.

A digital input signal DS from a signal source (not shown) is a line! 11 to the input terminal ds of the demodulation circuit 13.

The demodulation circuit 13 converts the digital input signal DS to the synchronization signal S.
Take out the NC and connect the line 1 from the PLL circuit 12
From the master clock signal MC as a basic signal input through 2 and the synchronization signal SNC mentioned above, various clock signals necessary for the operation of recording side equipment (not shown), such as switching necessary for digital/analog conversion, are generated. These are connected to the US equipment (not shown) via lines i73, . . . /4.

The PLL circuit 12 has an oscillation circuit (not shown) inside thereof, and one of the outputs of a vibrator 16117 realized by a crystal oscillator or the like is connected to the changeover circuit 15 by a changeover switch 15a. The above-mentioned vibrator 16.
A first or second master clock signal MC1 or MC2 (generally referred to as MC) having a frequency determined by 17 is input to the clock input layer me of the demodulation circuit 13 via line 2.

The first master clock signal MCI is, for example, 11.28.
96 MHz, which corresponds to a multiplication frequency of 44.1 kHz, which is the M1 sampling frequency Fs1.

Further, the second master clock signal MC2 is, for example, 12.
The frequency is 288 MHz, which corresponds to a frequency multiplied by 48.0 kHz, which is the second sampling frequency Fs2.

The first master clock signal MCI or the second master clock signal MC2 is supplied to a frequency dividing circuit (
), and the frequency is divided by the first sampling frequency Fsl or the second sampling frequency F! +2
(When collectively referred to as F9).

The tPJ1 master clock signal MCI' frequency-divided by the arithmetic circuit i1g (not shown) in the demodulation circuit 13 is
Input signal D S l: The included first sampling frequency Fsl and the frequency-divided second master clock signal MC2' (written as MC' when referred to as 4m) are compared with the second sampling frequency Fs2, and the frequency difference is calculated. is sent to the PLL circuit 12 via line 5 as the error signal ER.
will be returned to. The PLL circuit 12 thereby corrects its own oscillation frequency and holds the master clock signal MC constant in accordance with the digital input signal DS.

The phase difference detection circuit 14 receives the synchronization signal S from the demodulation circuit 13.
NC and the switching signal LR are received, and the above two signals SN are changed as the signal source changes, and thus the input signal DS changes.
This detects the phase difference between the C and LR signals. *The switching circuit 15 determines the change in the input signal DS based on the detection output of the phase difference detection circuit 14, and generates a master clock signal MC as a basic signal corresponding to the input signal DS. 17 is connected to the PLL circuit 12. Next, the operation of the phase difference detection circuit 14 will be explained with reference to FIGS. 2 and 3.

FIG. 2 is a waveform diagram of input and output signals in the phase difference detection circuit 14, and FIG. 3 is an electric circuit diagram showing the configuration of the phase difference detection circuit 14.

In FIG. 2, an interval A from time to to 1 corresponds to the first sampling frequency Fsl of the first human power signal DSL.
B indicates a synchronization period in which synchronization is achieved with the first master clock signal MCI' created by the PLL circuit 12 and frequency-divided by the demodulation circuit 13. However, since the first human input signal DSI changed to the second input signal DS2 and the vJ1 sampling frequency Fsl changed to the second sampling frequency Fs2, the first master clock signal M
It shows an asynchronous section in which synchronization with CI' is lost, and section C after time t2 is a PLL period as described later.
This indicates a synchronization period in which the master clock signal MC of the circuit 12 follows the change in the input signal DS and is synchronized with the second human input signal DS2 and therefore with the second sampling frequency Fs2. In the synchronization period A in Fig. 2, the synchronization signal SNC with a constant pulse width of 1 shown in Fig. 2 (1) and the synchronization signal SNC shown in Fig. 2 (2)
The pulse width input 2 switching signal LR shown in is the demodulator circuit 13.
It is derived from Switching signal L R is synchronizing signal SN
The demodulation circuit 13 is set so that the pulse rises at a predetermined time T after the rise of the pulse of the synchronization signal SNC, and similarly falls at the fall of the pulse of the synchronization signal SNC. Therefore, in the synchronization period A, the synchronization signal The phase difference between SNC and switching signal LR is approximately constant.

In this state, the first D-7177 block circuit 14a formed by the phase difference detection circuit 14 shown in FIG.
The inverted output terminal Q is generated by the switching signal LR input to the input terminal and the synchronization signal SNC input to the CK input terminal.
As shown in FIG. 2 (3), it is in the state of low level "0", and the following 20-7 lip 70 tube circuit 14
The state of the output terminal Q of D-b is also low level "0" and does not change in the synchronous area rIrIA.
The 7-lip, 70-tube circuit 15c connects the inverting output terminal Q and the input terminal to form a 1/2 frequency dividing circuit for the output of the ID-7, 70-tube circuit 14a.

Referring to FIG. 2, from the first signal source to the second signal source at time t1,
When the signal source changes, the synchronization signal SNC becomes out of order due to a change in the signal input DS, resulting in an asynchronous section B. In the asynchronous section B, the synchronization signal pulse pa - pb - pc is disordered.
The pulse qt-qb of the switching signal LR does not follow -pd, and the phase difference between the synchronization signal SNC and the switching signal LR becomes indefinite. Therefore, from the level relationship between the two at time t2, the third
As shown in Figure (3), the output terminal Q of the #41D-7 lip 70 tube circuit 15b becomes high level "1",
Therefore, the output terminal Q of the second D-7 lip 70 tube circuit 14b, that is, the output of the phase difference detection circuit 14 becomes high level "1".

Referring to FIG. 1, the output "1" of the phase difference detection circuit 14 is the line! 6 to the switching circuit 15. The changeover circuit 15 thereby has a built-in changeover switch 15a.
to switch the vibrators 16 and 17 from one force to the other. The changeover switch 15g is realized by, for example, an analog switch.

By switching the oscillators 16 and 17, the tp11 master clock signal M derived from the PLL circuit 12
CI changes into a second master clock signal MC2 corresponding to the second signal input DS2, which is input to the demodulation circuit 13 and frequency-divided into r:, second master clock signal MC2' and f.
:tS2 signal Sampling frequency Fs2 of human power DS2
are compared. If there is an error here, the PLL circuit 12 operates based on the error signal ER so that the master clock signal MC2, which is the basic signal, matches the doubling loss of the second sampling frequency.

Second master clock signal MC frequency-divided by demodulation circuit 13
2' and the second sampling frequency FS2 match, at time t3 in FIG. 2, the output level of the first D-71 hoop circuit 14a shown in FIG. , 2nd D-7') Tube 70
The output level of the 7' circuit 14b is maintained at the 7% level "1", and the generation of the master clock signal of the PLL circuit 12 is maintained stably.

The circuit element used in this embodiment is realized by a one-chip integrated circuit element (so-called IC), does not require a complicated configuration like the bandpass filter described in the prior art section, and is therefore small and stable. It is possible to realize a signal discrimination circuit.

Effects As described above, according to the present invention, basic signals corresponding to input signals of different frequencies are created in a PLL circuit, and a synchronization signal, a switching signal, and an error signal are generated based on the input signals and the basic signal. Created using demodulation circuit. Both the synchronization signal and the switching signal are demodulated outputs from the demodulation circuit, and the error signal is fed back to the PLL circuit to stabilize the basic signal, making it possible to reliably and easily distinguish between 1' input signals. I did it like that.

In addition, a means for detecting the phase difference between the synchronization signal and the switching signal is provided, and changes in the input signal are digitally determined from the output thereof, and the basic signal is made to correspond to the input signal using the switching means (by switching the oscillator). This makes it possible to realize a signal discrimination circuit that has a simple configuration and is easy to use.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the electrical configuration of a signal discrimination circuit 11 according to an embodiment of the present invention, FIG. 2 is a waveform diagram of input/output signals in the phase difference detection circuit 14, and FIG.
FIG. 4 is a block diagram showing the electrical configuration of a signal discrimination circuit according to the prior art. 1.11...Signal discrimination circuit, 2,13...Demodulation circuit, 3.4...Band pass filter, s, 15...Switching circuit, 5a115a...Selector switch, 6,7.1
(3, 17... vibrator, 8, 12... PLL circuit, 14... Sae phase difference detection circuit

Claims (1)

[Scope of Claims] Basic signal creation means for individually creating basic signals corresponding to at least two types of input signals having different frequencies and input at intervals, and the input signal and the basic signal. a means for creating a synchronization signal, a switching signal, and an error signal based on the above; a phase difference detection means for detecting a phase difference between the synchronization signal and the switching signal; and a change in the input signal determined by the output of the phase difference detection means. and switching means for switching a basic signal to correspond to the input signal.