JPS63155874A - Video intermediate frequency signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a stable detection output even at automatic search by providing a lock detection circuit separately from a video detection circuit and switching the detection system in response to the result of lock detection so as to detect the lock state up to a weak electric field. CONSTITUTION:With PLL sections 6, 7, 8, 9 locked to an input signal at the discrimination of lock, a lock detection circuit 100 discriminates the lock state. Thus, a PLL carrier (b) is outputted as a video detection signal (c) and a synchronizing detection circuit 3 applies PLL synchronizing detection. In this case, the lock range of the PLL is always constant independently of lock/unlock state and set to + or -1MHz or below to obtain a narrow noise band. Thus, a detection output without S/N deterioration is always obtained so long as the PLL is locked even at a weak electric input. Moreover, since a video detection circuit 3 is provided separately from the lock detection circuit 100 as to an input electric field, the lock state is detected with high accuracy up to a small electric field and the PLL synchronizing detection is applied up to a smaller electric field.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to television reception t1! The present invention relates to a video intermediate frequency signal processing circuit of a machine, and particularly relates to an improvement of a PLL synchronous detection method.

[Conventional technology]

FIG. 3 shows this type of conventional circuit. In the figure, 1 is a video intermediate frequency (hereinafter abbreviated as VIF) signal input terminal, 2 is an amplifier, 3 is a synchronous detection circuit, 4 is a video amplifier, and 5 is a video signal output. It is a terminal. Also, 6 is a phase detection circuit, 7 is a loop filter, 8 is a voltage controlled oscillator (VCO), and 9 is a 9
0° phase circuit, 10 is a lock detection circuit, the above phase detection circuit 6° loop filter 7, VCO 8, and 90°
The phase circuit 9 constitutes a PLL.

Next, the operation will be explained. Amplifier 2 by the above PLL
The outputs of VCO8 and VCO8 are in phase. Then, the input from input terminal 1 is amplified by amplifier 2, and V
The cos output is synchronously detected by the synchronous detection circuit 3 and obtained as a video detection output, amplified by the video amplifier 4 and output to the video signal output terminal 5. Furthermore, the lock detection circuit 10
Detects whether the PLL is in a locked state based on whether or not there is a detection output, and uses this information to control the time constant of the loop filter. In other words, when locked, the time constant of the loop filter is slowed down to obtain a narrow noise band, and when unlocked, the time constant is accelerated to obtain a wide pull-in range.

[Problem that the invention seeks to solve]

However, in such conventional devices, even if the pull-in range is expanded when unlocked, there is a limit to the value, which is usually about ±1 to ±2 MHz, and there is also a time until the pull-in occurs, so it is particularly difficult to During automatic search in an automatic channel selection system, if the search speed or search step of the frequency of the VIF signal is large, the VIF signal is often not pulled in.

In addition, the lock detection circuit 10 uses the fact that the waveform of the video detection output is a beat when it is not locked and a video output waveform when it is locked, as shown in FIG. is installed to determine whether the lock is present. This lock detection circuit 10 uses a video detection output signal as its input signal, but since the video detection circuit must have good linearity, the input dynamic range is widened. I try to do that. Therefore, at this time, the DC voltage when there is no signal also changes, making it difficult to set Vr as shown in FIG. 4. For this reason, a slightly larger Vr is set in consideration of variations in parts.

However, when a weak electric field is input, the amplitude value of the video detection signal becomes small even if it is locked, so if you set a large "■" as above, the lock detection circuit will judge that it is not locked. The accuracy of lock detection deteriorates.

Furthermore, even if the lock detection accuracy is good, if the input signal is very weak, it will be determined that the lock is not locked, but in this case, even though the S/N ratio of the input signal is very poor,
Since the time constant of is accelerated, unnecessary vibrations in the frequency of the VCO due to noise increase, and as a result, the video detection circuit obtains a signal with a worse S/N ratio.

Furthermore, if the lock is released due to strong electric field input for some reason, for example, if the CO coil is misadjusted,
A large beat output appears in the video signal, and abnormal phenomena on the screen become extreme.

The present invention has been made in view of the above points, and provides a video intermediate frequency signal processing circuit that can obtain accurate lock detection sensitivity and compensate for the drawbacks of PLL during auto search and weak electric field input. The purpose is to

[Means for solving problems]

The video intermediate frequency signal processing circuit according to the first invention of the present application includes:
The lock detection circuit is provided separately from the video detection circuit.

Further, the second invention is provided with a wave means for performing synchronous detection or square law detection, and the video detection method is switched between synchronous detection and square law detection according to the output result of the lock detection circuit. .

[Effect]

In this invention, since the edge detection circuit is provided separately from the video detection circuit, it is not affected by the video detection processing during lock detection, and the lock state can be detected even in weak electric fields, resulting in a narrow noise band. It will be done. In addition, since the detection method is switched according to the lock detection result, a stable detection output can be obtained even during automatic search in an automatic channel selection system, and when a weak electric field is input, the detection output with little S/N degradation is achieved by square law detection. can get.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In FIG. 1, the same reference numerals as in FIG. 2 indicate the same or equivalent parts, 100 is a lock detection circuit, 101 is a carrier switching circuit, and the lock detection circuit 100 performs video detection similarly to the synchronous detection circuit 3. However, the input dynamic range can be narrowed, and lock detection can be performed by accurately detecting even weak electric fields. In addition, the carrier switching circuit 101 uses a control signal from the lock detection circuit 100 to use the PLL carrier b from the vcos as the signal C for video detection when locked, and to use the amplified VIF signal a as the signal C for video detection when not locked. It is output as C.

Further, FIG. 2 shows a specific example of the structure of an IC circuit for the lock detection circuit 100, and the circuit 100 is composed of a transistor element, a resistor element, a constant current source, and an external capacitor. Here, assuming the power supply voltage, the resistance value of each resistance element, and the current value flowing through each constant current source as shown in the figure, the no-signal special voltage of section d is Vcc-%R1・r 1 Voltage of section e is Vcc-%R1.11 %R2.11. Therefore, in the case of this embodiment, the voltage Vr in FIG. 4 is set to %R2.■1.

Next, the effects will be explained.

First, at the time of lock determination, PLL sections 6, 7.8. and 9 are locked to the input signal, this is detected by the lock detection circuit 10.
0, it is determined to be in a locked state, and as a result, PLL carrier b
is output as a video detection signal C, and PLL synchronous detection is performed in the synchronous detection circuit 3. This is the same operation as the conventional example, but unlike the conventional example, the PLL pull-in range is locked.

It is always constant regardless of whether it is unlocked or not, and is set to below ±1 MHz to obtain a narrow noise band.

Therefore, even when a weak electric field is input, as long as it is locked, the S/
A detected output without N deterioration can be obtained. Regarding the input electric field, since the lock detection circuit 100 is provided separately from the video detection circuit 3, the accuracy is high and it is possible to detect the lock state even in a smaller electric field than in the conventional example, thereby eliminating the narrow noise mentioned above. PLL up to a smaller electric field in conjunction with the band
Synchronous detection can be performed.

On the other hand, when a non-lock determination is made, the amplified VIF signal a is output as the video detection signal C, and therefore the synchronous detection circuit 3 performs square law detection.

In the case of square-law detection, even if the frequency of the input VrF signal shifts, a detection output is always obtained, and it is obtained instantaneously, so the detection output is stable even if there is a large frequency movement during auto search during automatic tuning. can be obtained. The disadvantage of square law detection is that the linearity of the detection output is poor.
During auto-search, linearity is not a concern because it is only necessary to determine the presence or absence of a detection output. Further, even in the case of a delicate input electric field that does not cause locking at all, this embodiment switches to square-law detection, so a detected output is always obtained.

Further, in the operation of the PLL, the pull-in range is narrower than the holding range, so there is hysteresis in the switching operation of PLL detection and square-law detection with respect to the input frequency, and there is no instability at the time of switching.

Furthermore, even when implementing the circuit of this embodiment with a TC, in the conventional example, one pin is required for the lock detection filter of the lock detection circuit 10, and one pin is required for switching the time constant of the filter outside the IC of the loop filter 7. However, in this embodiment, as shown in Fig. 2, one pin is required for the lock detection filter, and the switching circuit 101 can be processed inside the IC, so one pin was removed in the end. can do.

In this way, this embodiment has the following features: ■ Since it has a wide reception range against frequency fluctuations of the input signal, stable operation is possible even during automatic search for automatic tuning ■ The time constant of the PLL loop filter is made slower than before. This makes it easy to obtain a narrower noise band, and in particular removes unnecessary components such as voice buzz. ■ High judgment accuracy of the lock detection circuit. There is little deterioration in the S/N ratio when inputting a weak electric field. ■ Even if the PLL does not lock at all for some reason, a detected output can be obtained reliably. ■ The number of terminals can be reduced when integrated into an IC. Easy to replace. This system has the advantage of being able to switch between PLL detection and square law detection.

Note that in the above embodiment, (1) the lock detection circuit is provided separately from the video detection circuit;
(2) Although switching between PLL detection and square law detection is performed simultaneously using a control signal from the lock detection circuit, only one of the two may be provided.

That is, it may be possible to have only the configuration (2) above, and in this case, the time constant or loop gain of the loop filter may be switched by lock detection. Accurate lock detection is also possible with such an embodiment, and a narrow noise band can be obtained by detecting a lock state even in a weak electric field.

As another example, the lock detection circuit uses the output of the video detection circuit, but two detection circuits, a PLL detection circuit and a square law detection circuit, are provided, and the output of the PLL detection circuit is guided to the lock detection circuit. It is conceivable that the output of the PLL detection circuit is taken out as the video detection output, and the output of the square law detection circuit when the lock is not locked. In this case, a stable detection output can be obtained even during auto-search, and a detection output with little S/N degradation can be obtained by square law detection when a weak electric field is input.

〔Effect of the invention〕

As described above, according to the present invention, since the lock detection circuit is provided separately from the video detection circuit, it is possible to detect a lock state even in a weak electric field and obtain a narrow noise band. In addition, since the detection method is switched depending on the lock detection result, stable detection output can be obtained even during auto search, and S/N
This has the effect of obtaining a detection output with little deterioration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video intermediate frequency signal processing circuit according to an embodiment of the present invention, and FIG. 2 shows a lock detection circuit of the circuit.
Figure 3 is a diagram showing the circuit configuration of a conventional video intermediate frequency signal processing circuit, Figure 4 is a signal waveform diagram for explaining its lock determination operation, and Figure 5 is a diagram of the conventional circuit. It is a circuit diagram when a loop filter and a lock detection circuit are integrated. 3... Synchronous detection circuit, 4... Video amplifier, 6...
Phase detection circuit, 7... loop filter, 8... VC
o, 9...90° phase shift circuit, 100...lock detection circuit, 101...carrier switching circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (4)

[Claims] (1) In the video intermediate frequency signal processing circuit of a television receiver, a PL that oscillates a signal that is phase-synchronized with an external input signal.
L means, synchronous detection means for performing synchronous detection on the input video intermediate frequency signal using the output of the PLL means, and the synchronous detection means are provided separately, The locked/unlocked state of the PLL is detected based on the output, and the PLL is
A video intermediate frequency signal processing circuit comprising lock detection means for controlling the operating state of the L means. (2) When the PLL means is in the locked state, the lock detecting means detects the PLL according to the detection result of the locked state.
Video intermediate frequency signal processing according to claim 1, characterized in that the time constant of a loop filter constituting the means is slowed down, and the time constant of the loop filter is made fast when in an unlocked state. circuit. (3) In the video intermediate frequency signal processing circuit of a television receiver, a PL that oscillates a signal that is phase-synchronized with an external input signal.
L means; a detection means for performing PLL synchronous detection or square law detection on the input video intermediate frequency signal; a lock detection means for detecting whether the PLL is locked or unlocked; A video intermediate frequency signal processing circuit comprising detection switching means for causing the detection means to perform PLL synchronous detection and for performing square law detection when in an unlocked state. (4) The lock detection means is provided separately from the detection means and detects whether the PLL is locked or unlocked based on the input video intermediate frequency signal and the output of the PLL means. Claim 3
2. The video intermediate frequency signal processing circuit described in .