JPS63155635U - - Google Patents
Info
- Publication number
- JPS63155635U JPS63155635U JP4887587U JP4887587U JPS63155635U JP S63155635 U JPS63155635 U JP S63155635U JP 4887587 U JP4887587 U JP 4887587U JP 4887587 U JP4887587 U JP 4887587U JP S63155635 U JPS63155635 U JP S63155635U
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- electrode
- chip carrier
- chip
- empty space
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000011156 evaluation Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の一実施例を示す正面図である
。 １……チツプキヤリア本体、２……ボンデイン
グ電極、３……空スペース、４……評価電極。
。 １……チツプキヤリア本体、２……ボンデイン
グ電極、３……空スペース、４……評価電極。
Claims (1)
- 半導体集積回路チツプにボンデイング接続する
ボンデイング電極を設けたチツプキヤリアにおい
て、チツプキヤリア本体上のボンデイング電極以
外の空スペースにボンデイング強度測定用の電極
を有することを特徴とするチツプキヤリア。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4887587U JPS63155635U (ja) | 1987-03-31 | 1987-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4887587U JPS63155635U (ja) | 1987-03-31 | 1987-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63155635U true JPS63155635U (ja) | 1988-10-12 |
Family
ID=30870817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4887587U Pending JPS63155635U (ja) | 1987-03-31 | 1987-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63155635U (ja) |
-
1987
- 1987-03-31 JP JP4887587U patent/JPS63155635U/ja active Pending