JPS6315556B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a digital waveform storage device, and particularly to a digital waveform storage device that can display input signal waveforms in real time and digitally store them.

[Prior Art] A digital waveform storage device samples an input signal using a clock pulse of a predetermined period, converts it into a digital signal, and stores it in a storage means such as a RAM (random access memory). This stored waveform data is read out at desired times and displayed and reproduced on a display device such as a cathode ray tube (CRT). Data stored in RAM can be retained for an arbitrary period of time before being erased, which is extremely convenient.

In order to display the input signal waveform in real time like a conventional oscilloscope and to accurately digitally store and reproduce the displayed input signal waveform, a predetermined number of samples (N>1), for example 1000, are required per waveform. shall be. Therefore, the clock pulse is configured to be automatically switched and selected according to the sweep speed of the real-time display. This theoretically allows a constant number (N) of samples to be obtained for any sweep speed, so that the real-time display waveform and the digitally stored waveform can be displayed in substantially the same way.

By the way, the minimum sweep speed of a real-time oscilloscope is generally 5 seconds/division, so one sweep time is 50 seconds. However, it is impossible to display certain electrical phenomena over several hours, such as the drift of a DC power supply, on a real-time oscilloscope. In other words, at such a low sweep speed, there is a risk of burning the CRT screen, and
This is because the afterglow time is so short that it cannot be displayed.

[Summary of the Invention] Therefore, the present invention makes active use of the features of a digital waveform storage device, obtains N samples from a signal waveform displayed in real time, and adds 1/N minutes to a clock generator. By adding a frequency filter to obtain one sample per sweep time, and expanding the time axis of the waveform by N times with N samples obtained during N sweep periods (for example, up to several hours), A novel digital waveform storage device that compensates for the shortcomings of real-time oscilloscopes can be provided.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram of one embodiment of a digital waveform storage device according to the present invention. In FIG. 1, an input terminal 10 to which an analog input signal is applied is connected to a display device such as a CRT via an input circuit 11, a preamplifier 12, a delay circuit 13, a switch circuit 14, and a main amplifier 15. There is. A portion of the input signal is extracted from the preamplifier 12 and applied to a trigger circuit 17 . As will be described later, the trigger circuit 17 generates a trigger pulse when the level of the applied signal exceeds a predetermined value, and applies the trigger pulse to the sawtooth wave generator 18. The sawtooth generator 18 starts generating a sawtooth signal by a trigger pulse, and the slope of the sawtooth signal is controlled by the sweep speed control circuit 19. The sawtooth signal is sent to preamplifier 2.
0 is applied to the X time axis circuit (not shown) of the display device 16 via the switch circuit 22 and main amplifier 23. For purposes such as expanding the measurement range, the gain of the preamplifier 20 can be adjusted by the operator using the amplification switching circuit 2.
Switching is possible by operating 1. The outputs of preamplifiers 12 and 20 are applied to sampling circuits 26 and 27 via amplifiers 24 and 25, respectively, under the control of clock pulse generator 29.
The sampling outputs from the sampling circuits 26 and 27 are converted to analog signals via a multiplexer 30.
The signal is applied to a digital converter (ADC) 31 and converted into a digital signal. The digital signal is stored in a predetermined storage location of the storage means 32, which is, for example, a semiconductor RAM. The stored digital signal is
The signal is read out when necessary, converted into an analog signal by a digital-to-analog converter (DAC) 33, and then applied to the display device 16 via switch circuits 14, 22 and main amplifiers 15, 23 for display. still,
The stored digital signal continues to be stored in the storage means 32 until updated by a new digital signal. The comparator 34 compares the sawtooth signal voltage generated from the sawtooth wave generator 18 with the control DC voltage from the pre-trigger control potentiometer 35. The output of the comparator 34 is sent to the Z-axis amplifier 36
is applied to When the sawtooth signal voltage exceeds the control DC voltage from potentiometer 35, the output of comparator 34, via Z-axis amplifier 36, interrupts the clock pulses of clock pulse generator 29. The output of Z-axis amplifier 36 is applied to display device 16 as a brightness control signal.

The operation of the digital memory system shown in FIG. 1 will be further explained with reference to the waveform diagrams shown in FIGS. 2A to 2H. It is assumed that an input signal having a waveform as shown in FIG. 2A is applied to the input terminal 10. The trigger circuit 17 detects when the level of the input signal is
At t ₁ , a trigger pulse (FIG. 2B) is generated when a controllable trigger level T1 is exceeded. The sawtooth wave generator 18 is triggered by this trigger pulse and generates a sawtooth signal (FIG. 2C) with a slope selected by the sawtooth slope control circuit 19, and at the same time, sweeps the gate during the generation period of the sawtooth signal.・
A pulse (FIG. 2D) is generated. The comparator 34 is
The level of the sawtooth signal is the reference voltage set by the pre-trigger control potentiometer 35.
When Vref is exceeded (time t ₂ ), the pulse shown in FIG. 2E is output. A reset circuit (not shown) within sawtooth generator 18 resets sawtooth generator 18 when the sawtooth signal level reaches a predetermined maximum value at time _t3 . Therefore, the sweep gate
The pulses and the output pulses of comparator 34 also return to their initial state at time _t3 . The sampling circuits 26 and 27 are
The input signal and the sawtooth signal are sampled as controlled by the clock pulse (Figure 2H), and the stop pulse (or pre-trigger control pulse) shown in Figure 2G is triggered from the clock pulse generator at time _t2 . Continue sampling until the clock pulse is cut off. The stop pulse in FIG. 2G is at time t ₂
can be obtained, for example, by differentiating the leading edge of the output pulse of the comparator 34 in FIG. 2E. The storage means 32 stores the samples obtained by the above sampling during the period t ₀ to _{t 2} . In addition, as described later, the period t ₀ to _{t 2}
(or t ₁ to _{t 3} ) is determined by taking into account the period of the clock pulse and the storage capacity of the storage means 32. That is, the clock pulse generator 29 is used to automatically select the optimum clock pulse period, taking into account the selected sweep speed and the storage capacity of the storage means.
is equipped with multiple frequency dividing circuits.

The input signal and the sawtooth signal are applied to the display device 16, and the input signal waveform for the period _t1 to _t3 is displayed on the display device 16. To show the part of the input signal waveform for the period t ₁ to _{t 3} that is stored in the storage means 32, the output pulse of the comparator 34 (FIG. 2E) is plotted from the sweep gate pulse (FIG. 2D). The brightness control pulse (FIG. 2F) is obtained by subtracting . This brightness control pulse is applied to the display device 16, for example.
Controls the CRT grid voltage. Therefore,
Since the brightness of the waveform portion during the period t ₁ to t ₂ is greater than the brightness of the waveform portion during the period t ₂ to _{t 3} , the operator can easily identify the waveform portion stored in the storage means 32 . Note that at time t ₂ , that is, during the pre-trigger period from t ₀ to _{t 1} , the pre-trigger control potentiometer 3
5 can be controlled very easily.

The display device 16 displays the input signal waveform during the period t ₁ to _{t 3} in real time mode, or
Alternatively, the switch circuits 14 and 22 are controlled to selectively display the input signal waveforms stored in the period t ₀ to _{t 2} in a storage mode. Furthermore, since it is possible to simultaneously display both the signal waveforms before and after the trigger pulse generation time _t1 by time division, the waveform measurement apparatus shown in FIG. 1 is most suitable for detailed observation of a single expression image. Furthermore, if a storage tube (in particular, a so-called split screen type storage tube (disclosed in Japanese Patent Publication No. 41-1813) for which the present applicant has patent rights) is used in the device shown in FIG.
It's even more convenient. That is, the input signal waveform after the trigger point can be accumulated and stored on the CRT screen, and the input signal waveform before the trigger point can be stored in the storage means 32 and displayed on the non-accumulated screen portion of the CRT. .

The sweep speed control circuit 19 switches the sweep speed, ie, the slope of the sawtooth wave (FIG. 2C) from time _t1 to _t3 in this embodiment, in steps of 1-2-5. The input signal waveform for the period t ₁ to _{t 3} is displayed on the CRT screen of the display device 16, but as the sweep speed becomes faster, the displayed portion of the input signal waveform becomes narrower. will be displayed partially enlarged. Furthermore, in this embodiment, the gain of the amplifier 20 can be increased by 10 times by the amplification switching circuit 21, so the maximum sweep speed obtained by the sweep speed control circuit 19 can be increased by 10 times. When the amplification switching circuit 21 is operated at a certain sweep speed, it is also possible to display the input signal waveform at a magnification of 10 times. The clock signal generator 29 operates by the sweep speed control circuit 19 and the amplification switching circuit 21 so that the sampling numbers of the sampling circuits 26 and 27 remain constant regardless of changes in the sweep speed and the state of the amplification switching circuit 21. controlled. The broken lines in FIG. 1 indicate the control path for the above-mentioned control.

FIG. 3 is a block diagram showing one embodiment of clock signal generator 29 shown in FIG. 1. Note that for convenience of explanation, the clock signal generator 29 is not shown in FIG.
Related circuits 19, 21, etc. are also shown. In this embodiment, the reference clock pulse oscillator 40 is
This is a crystal oscillator that outputs a 20.48MHz clock pulse corresponding to 1024 words, which is the maximum storage capacity of the RAM 32. In the following explanation, in order to avoid complexity, the decimal part of the clock pulse frequency may be omitted, and 20.48MHz may be changed to 20MHz, for example. The 20 MHz output pulse of the reference clock pulse oscillator 40 is applied to a 1/2 frequency divider 41A consisting of one stage of flip-flop to produce a 10 MHz clock pulse. The output pulse of the frequency divider 41A is applied to a first multiplexer (or switch circuit, hereinafter referred to as MUX) 43, a 1/2 frequency divider 42A, and a 1/5 frequency divider 42B. Frequency dividers 42A and 42B apply 5MHz and 2MHz clock signals to first MUX 43, respectively. No.
1MUX43 uses a commercially available IC (for example, 74LS151, etc.)
You can use The clock pulse (2MHz) from the 1/5 frequency divider 42B is passed through the two-stage frequency divider circuit 42.
B is also added, and the two types of clock pulses obtained from it, 1 MHz and 500 KHz (0.5 MHz), are sent to the first MUX 4.
3. 2nd MUX 4 with the same configuration as the 1st MUX
Clock pulses of 20 MHz, 10 MHz, and 5 MHz are applied to clock pulses 4 from a reference clock pulse generator 40 and frequency dividers 41A and 42A, respectively. As shown in FIG. 3, the amplification switching circuit 21 includes a control switch 55 and a selection logic circuit 56, and the logic circuit 56 applies a high level or Apply a low level logic signal. 1st MUX43 and 1st MUX43
The output end of 2MUX44 is directly connected, and the 3rd MUX4
8 inputs and 5 cascaded 1/10 frequency dividers 4
It is also connected to the input terminals of the first stages of 5A, 45B, 46A, 46B, and 47. The output terminals of the five 1/10 frequency dividers 45A to 47 are connected to the input terminal of the third MUX 48, respectively. The sweep speed control circuit (or timing logic circuit) 19 includes a reference clock pulse oscillator 40, an amplification switching circuit 21, a first
to the third MUX 43, 44, and 48, and apply control logic signals to each of them.

The output of the third MUX 48 is applied directly to the fixed contact a of the selection switch 49, and is also applied to the fixed contact b via the 1/1K frequency divider 50. An external clock pulse is applied to the fixed contact c via an external input terminal 53 and a buffer amplifier 54.

Referring to FIG. 4, the operation of clock signal generator 29 shown in FIG. 3 will be explained. FIG. 4 shows the relationship between the clock pulse frequency determined by switching the selection switches 49 and 55 and the sweep speed of the oscilloscope. In the normal state where the selection switches 49 and 55 are at the terminal a and X1 positions, respectively, the first MUX 43
is in an operating state, and the second MUX 44 is in an inactive state.
The sweep speed is 10μS/DIV as shown in Figure 4.
From 5S/DIV can be selected in 1-2-5 steps. At the lowest sweep speed of 5S/DIV,
Clock pulse (2MHz) from 1/5 frequency divider 42B
is applied to the 1/10 frequency divider 45A via the first MUX 43, and the third MUX 48 selects the output pulse (20Hz, precisely 20.48Hz) of the frequency divider 48 and outputs it to the output terminal 52. The time it takes for an electron beam to cross a CRT screen is
For a CRT screen with 10 divisions, it is 50 seconds.
Therefore, in the above case, the number of samples extracted in 50 seconds (i.e., one cycle) is 50×20.48=
1024, which is equal to the maximum number of words stored in the RAM 32. Incidentally, if the maximum storage capacity of the RAM 32 is not 1024 words, it is of course necessary to change the clock pulse frequency accordingly. At the second slowest sweep speed (2S/DIV), the sweep speed control circuit 19 causes the first MUX 43 to select the output pulse (500KHz) of the frequency divider 41B, and the third MUX 48
A control signal is applied to the first and third MUX 43, 48 so that the output pulse of the frequency divider 46B is selected. Therefore, a 51.2 Hz clock pulse is taken from output terminal 52. In this case as well, 1
Note that the number of samples taken in a cycle is 1024. When the sweep speed is switched to 1S/DIV, the first MUX 43 and the third MUX 48
Since the output pulses of frequency dividers 41B and 46B are selected, respectively, a 102.4 Hz clock pulse is taken out from output terminal 52. At a sweep speed of .5S/DIV, the first MUX 43 and the third MUX 48 select the output pulse (2MHz) of the frequency divider 42B and the output pulse of the frequency divider 46B, respectively, so that a 204.8Hz clock pulse is output from the output terminal 52. can get. Similarly, the sweep speed is .2S/DIV, .1SS/DIV, 50
When switching in the order of mS/DIV, the first MUX 43
select clock pulses of 0.5MHz, 1MHz, and 2MHz, respectively, and the third MUX 48 selects the frequency divider 46A that generates a 1/1K divided output, so the output terminal 52
Clock pulses of 512KHz, 1.025KHz, and 2.048KHz can be obtained from. Furthermore, the sweep speed was increased to 20mS/DIV.
When switching sequentially from 10 μS/DIV to 10 μS/DIV, the clock pulses change from 5.12 KHz to 10.24 MHz, respectively, as shown in FIG. Note that regardless of the sweep speed, the number of clock pulses generated within one sweep period is constant (1024 in this embodiment), so a constant number of samples can always be obtained. The maximum clock pulse frequency depends on the analog-to-digital converter (ADC)
31 conversion speed, but fast
ADCs can be used to increase the upper limit of clock pulse frequency.

When the selection switch 55 is switched to the X10 position to increase the sweep speed by ten times, the selection logic circuit 56
The first MUX 43 is made inactive, and the second MUX 44 is made active. Therefore, the second MUX receives clock pulses of 20 MHz and 10 MHz from the reference clock pulse oscillator 40 and frequency dividers 41A and 42B, respectively.
Receives Hz, 5MHz. 2nd MUX44 and 2nd MUX44
The 3MUX 48 outputs a predetermined clock pulse shown in FIG.
It is controlled by the sweep speed control circuit 19 so as to output from As an example, the maximum sweep speed
In 5S/DIV, 2nd MUX 44 and 3rd MUX 48
are each reference clock pulse oscillator (20.48MHz)
and frequency divider 47, 20.48MHz÷
100K = 204.8Hz clock pulse is output from terminal 52
obtained from. In this embodiment, when the sweep speed is 20μS/DIV or 10μS/DIV in relation to the conversion speed of the ADC 31, the first MUX 4
Both MUX 3 and MUX 2 44 are inactive so that no clock pulses are generated from output terminal 52. It is clear from FIG. 4 that if the selection switch 55 is switched from the X1 to X10 position and the sweep speed is increased ten times, the clock pulse frequency will also be increased ten times.

By the way, when switch 49 is switched to contact b, the first
The frequency of the output pulse of 3MUX48 is 1/1000
be lowered to Frequency divider 50 is provided so that only one clock pulse is generated per sweep and only one piece of information is sampled and stored per sweep. This mode of operation is suitable for applications where the input signal changes very slowly, such as in drift measurements or environmental tests, where data is obtained over a long period of time, for example one hour or more. Of course, the frequency division ratio of the frequency divider 50 is related to the number of clock pulses required for each sweep or the storage capacity of the RAM 31.

When switch 49 is switched to contact C, the input signal waveform can be sampled by an external clock pulse applied to external input terminal 53. Therefore, the operator can sample the input signal with pulses of any frequency within the predetermined maximum clock pulse frequency.

[Effects] As is clear from the above description, the digital waveform storage device of the present invention allows input signal waveforms to be displayed and observed in real time at any sweep speed in the same way as a normal oscilloscope. Signal waveforms can be stored and displayed digitally with a predetermined resolution (number of samples), and the switch 49 can be switched to the output of the frequency divider 50 to sample one signal per sweep to effectively measure drift, etc. It can be done in a specific manner. That is, for example, assuming that the sweep is repeated once every 2 seconds, 1000 samples will be obtained in 1000 sweeps, so approximately 30
Drift information, which is signal changes over a minute, can be stored and displayed at one time. Of course, even when sweeping at higher speeds, multiple points (e.g. trigger point) at the same point (e.g.
1000) It goes without saying that samples can be stored digitally and waveform changes can be stored and displayed. Therefore, the digital waveform storage device according to the present invention not only simply stores and displays the same input signal waveform in real time or digitally, but also has a new function of being able to collectively display and observe changes in input signals over a long period of time. is added, so the practical effect is significant.

Although the preferred embodiments of the present invention have been described above, those skilled in the art can make modifications to the above-described embodiments depending on the application.

[Brief explanation of the drawing]

FIG. 1 is a simplified block diagram of an embodiment of the digital waveform storage device according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of the device shown in FIG. 1, and FIG. FIG. 4 is a detailed block diagram showing the clock signal generator shown in FIG. 14, 22... Selection means, 26, 27... Sampling means, 29... Clock pulse generator,
31...Analog-to-digital converter, 32...Storage means.

Claims (1)

[Claims] 1. A real-time signal waveform display device that displays an input signal waveform on a display device using an input signal and a sawtooth wave generated in synchronization with the input signal, a sampling circuit, an analog-to-digital converter, a clock generator, The clock pulse period of the clock generator is controlled according to the sweep period of the sawtooth wave of the real-time signal waveform display device, and the storage capacity of the storage means is controlled for each sweep period. a digital storage device that obtains a predetermined number (N>1) of samples determined by and stores them in the storage device, and displays the stored data on the display device via the digital-to-analog converter when desired. In the storage device, the clock generator is further provided with an N frequency dividing means to divide the clock pulse from the clock generator into 1/N and apply it to the sampling circuit, so that the frequency of the clock pulse from the clock generator is divided by 1/N and applied to the sampling circuit for each sweep period of the sawtooth wave. A digital waveform storage device characterized in that one sample per sample is obtained and stored in the storage means.