JPS63153942A - Digital delay detecting circuit - Google Patents

Abstract

PURPOSE:To miniaturize a delay detection circuit and to make adjustment unnecessary for it, by performing the delay and detection of a signal after converting it to a base band by using a local signal having a frequency same as that of an input signal and a phase different by 90 deg.. CONSTITUTION:An input modulation wave converted to a digital signal by A/D conversion is multiplied by the local signal having the phase shifted by 90 deg. at multipliers 12 and 17, and respective wave, after being LPF-processed by digital filters 13 and 18, is delay-processed by memories 14 and 19. After through multiplication processes by multipliers 15, 20, 21, and 25, and addition processings by adders 16 and 22, detection outputs B(t) and C(t) at every channel can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) Delay detection is well known as one of the methods of detecting a signal digitally modulated by phase modulation.

The present invention relates to a processing method for delayed detection that realizes this delayed detection by digital signal processing.

The circuit of the present invention is a delay detection circuit that is used for differential phase digital transmission using subcarriers in the audio frequency band.

(Prior art) Phase shift keying (PSK) is often used to transmit digital data, but differential phase modulation is used when communicating using a propagation path where fading etc. It is known that the detection method is resistant to phase fluctuations and provides good error rate characteristics. (Here, a case will be explained using four-phase differential phase modulation as an example.

) FIG. 2 is a diagram showing an example of the configuration of a conventional delay detection circuit (here, a case using four-phase differential phase modulation will be explained as an example).

) In the figure, symbol 1 is a 906 phase shifter, and symbols 2 and 3 are mixers (MI
X), 4 and 5 are LPFs (low-band p-wave filters), 6 is a delay circuit, 7 is a received modulated wave input, 8 and 9 are detection outputs, and this output is the inverse of the code conversion on the modulator side and Information is output after parallel-to-serial conversion.

Now, the received modulated wave signal is inputted directly to the old X2, or it is delayed by one element time in the delay circuit 6 and then inputted to the old X2.

This delay time needs to be an integral multiple of the repetition period of the carrier signal. The output of MIX2 passes through LPF4 and becomes a detection output of 8.

On the other hand, the modulating wave cuff becomes one input of the restoration
The other input is the output of the delay circuit (DLY) 6.

The output of MIX 3 passes through LPF 5 and becomes detection output 9.

Cocote LPF4 and LPF5 have the role of removing the carrier component and sum component in the signals multiplied by MIX2 and MIX3, as well as removing noise outside the required band.

Delayed detection circuits have conventionally been realized using analog circuits, but analog circuits require troublesome work such as fine adjustment of the phase to match the phase relationship, and have problems such as large changes over time.

On the other hand, when delay detection is realized by digital calculation, the following two problems arise when the circuit shown in FIG. 2 is directly replaced with a digital calculation circuit. The first is that it is difficult to realize a phase shifter. To implement a phase shifter, it is usually necessary to perform a Hilbert transform, which requires a complex circuit. Therefore, delay circuits are generally used to approximately realize the phase shifter. In this case, it is necessary to set the carrier frequency of the modulated wave to be sufficiently larger than the modulation speed (preferably 10 times or more) so that the delay for phase shifting does not affect the element timing. Therefore, there is a drawback that the sampling frequency of the AD converter before digital calculation must be increased.

The second problem is that the delay time of the delay circuit needs to be an integral multiple of the repetition period of the carrier signal of the modulated wave.If the ratio of the carrier frequency and modulation speed is not an integer, the carrier frequency and sampling In addition to the need to increase the frequency, it is also necessary to make the sampling frequency an integral multiple of the carrier frequency, which has the disadvantage of reducing the degree of freedom in device design.

(Specific Object of the Invention) The present invention was carried out to eliminate the drawbacks of the conventional method, and uses a local signal having the same frequency as the carrier frequency of the input signal and a phase difference of 90" to convert the signal to the baseband. It is characterized by performing delay and detection after conversion.

(Configuration and Operation of the Invention) FIG. 1 is a diagram showing an example of the configuration of a delay detection circuit embodying the present invention. In this figure, 11 is an AD converter, and the input modulated wave A
(t) is converted into a digital signal. 12.15°1? ,
20, 21, and 23 are digital multipliers, 13 and 18 are digital filters, 14 and 19 are delay memories, 16 and 22 are digital adders, 24 and 25 are ROM (read only memory) tables, and 26 is a counter. . Note that the digital filters 13 and 18 have the same functions as the LPF4 and LPF5 shown in FIG. 2, respectively.

Now, 24, 25, and 26 constitute two local signal generation circuits. The generated local signal has ωl as its angular frequency (nT) = cos (n ω1 T)
and E(nT)=sin(nωx T). However, T is the sampling period and n is the sampling number.

The counter 26 adds ωtT to the previous value for each sampling, and thereby calculates the phase of the local signal. Further, the ROM tables 24 and 25 have cos θ and sin θ, respectively, when θ is input as an address.
The conversion table is written so that θ is output,
This allows D (nT) and E (nT) to be obtained.

Since si mouth θ=COS (θ+π/2),
In this conversion table, one conversion table is shared for two local signals, and two local signals can be generated by shifting and reading the address.

Now, the input modulated wave converted into a digital signal by AD conversion is multiplied by a local signal having a phase difference of 90'' in multipliers 12 and 17, and each is subjected to LPF processing by digital filters 13 and 18.The output of the digital filter is Delay processing is performed by the memories 14 and 19, and the detection outputs B(t) and C(t) for each channel are obtained through multiplication processing by the multiplier in 15.20.21.23 and addition processing by the adder in 16.22. It will be done.

Next, the above operation will be explained in more detail. In FIG. 1, the input signal is A (tl), and the local signal is D (t).

It is expressed as E(t) as follows. Note that the actual processing is processing of sampled signals, but for ease of explanation, it will be explained as a continuous wave.

A(t)=cos (ωct+φ(t)]D(t)=c
os [ωz t+ψ(t)]E(t)=sin (ω
z t+φ(t)) Here, ω is the angular frequency of the input modulated wave, φ(1) is the modulation phase, ωl is the angular frequency of the local signal, and ψ(1) is the phase difference between ω0 and ωl.

Therefore, 12 and 1 of A(t), D(t) and E(t)
The outputs F(t) and G(t) after passing the multiplication results by the 7th multiplier through the 13th and 18th LPFs are expressed as follows.

F(t)−−cos ((ωc(dt)t+φ(
11−ψ(t)]G(t) = −5in ((ω.−
ωz)t+φ(11-ψ(t)) At this time, the output H(t) of the delay circuit 14 and the output 1(t) of the delay circuit 19 are expressed as follows, assuming that the delay time is τ.

11(t) = −cos ((ω.−ωz)(t−τ
)+φ(tl)−ψ(t−τ)] 1(t)=−sin((ωc a)z)(t−r)+
φ(t-r)-ψ(t-τ)] Therefore, one detection output B(t) is expressed as follows.

B(t) =F(t) xH(t) +G(t) x
I(t)=cos ((ω.-ω1)τ+φ(1)-φ
(-τ)-ψft+-ψ(at t-)] Here, ω. -ωl is the frequency difference between the input modulated wave and the local signal, and this value can be set to (ω0-ωl)τ#0 by making it extremely small.

Also, since ψ(1) is constant, ψ(11−ψ(t−τ)
is zero. Therefore, B(t)#cos (φ(tl-φ(t-r)).Similarly, the other detection output C(t) is H(t)
From xG(L) +F(t) x I(t), C(tl
#sin (φ(11-φ(t-r)). From the above explanation, with the configuration shown in FIG. 1, the same detection output as the analog circuit in FIG. 2 can be obtained by digital calculation. Also, this circuit configuration In this case, a phase shifter and a delay circuit at the carrier frequency are not required, and the above-mentioned drawbacks of the conventional method are eliminated.

Now, to explain the relationship between the method of phase change in differential phase modulation and the method for determining the detection output described above, in 4-phase differential phase modulation, the phase difference between elements corresponding to 2 bits of information is 45". , 135°, 225", 315°, and O", 90", 18
0'.

There is a method of having four positions of 270'. In the former case, the threshold for judgment in reception is a phase difference of 0.
', 90'', 180'', and 270°, it is possible to determine whether B(t) and C(t) are positive or negative, and determine the data based on the combination of the positive or negative values. On the other hand, in the latter case, the phase difference is 45', 135'', 225',
Since the point 315' is the threshold for judgment, B'
(t)=B(t)+C(L)=ffsin (φ(1)
-φ(t-τ) ten-] C'(t)=B(t)-C(t)=&cos (φft
+-φ(t-τ)+] and make the same determination for B'ftl and C'(L). Furthermore, in the case of two-phase differential phase modulation with a 180' shift, it is sufficient to determine whether B(t) is positive or negative. Furthermore, B(t)cos α−C(t) sincr −cos (
φ (1) − φ (tr) + z) 8 (t) sin α + c (
t) coacx=sin (φ(1)−φ(t−r)+
α) Therefore, by appropriately selecting the value of α and calculating the above equation, it is possible to determine an arbitrary phase difference as a threshold. Therefore, the present invention can also be applied to differential phase modulation of eight or more phases.

, For example, in normal 8-phase PSK, 22.5°, 67
．． 5@.

112.5°, 157.5°, 202.5”,
247.5 @, 292.5°.

Since 337.5° is the threshold, cos (
φ(1)−φ(t−τ)×−〕sin(φ(1)−φ
(at t-) 10-) is obtained, the positive and negative values are determined, and the data is determined based on the combination of the positive and negative values.

(Effects of the Invention) According to the present invention, delay detection can be performed by digital signal processing, and since a digital signal processing LSI can be used for this purpose, the delay detection circuit can be miniaturized and no adjustment is required. Another major advantage of digital circuits is that they do not change over time.

In addition, the detection circuit using digital processing has a relatively narrow bandwidth, so it is suitable for applications where the modulation speed is not very fast.
For example, it is particularly effective in code transmission in the audio frequency band.

[Brief explanation of the drawing]

FIG. 1 is a side view of the configuration of a delay detection circuit according to the present invention, and FIG. 2 is a side view of the configuration of a conventional delay detection circuit. 1-90'' phase shifter, 2.3... mixer, 4.5...
...LPF. 6...Delay circuit, 7...Reception modulation input, 8.9...
・Detection output, 1l-AD converter, 12.15.17.2
0.21゜23...Digital multiplier, 13.18.
...Digital filter, 14.19...Delay memory, 16.22...Digital adder, 24.25.
...RO? t table, 26... counter.

Claims (1)

[Claims] An analog input signal is digitally encoded by an AD converter, and the phase is 90 degrees at the same frequency as the carrier frequency of the input signal generated by digital arithmetic processing.
°A time delay of 1 element is applied to each of the two signals obtained by multiplying with two different local signals by separate multipliers and passing through a low-pass filter separately, and the two signals before the delay are signal and the two delayed signals as 2
A digital delay detection circuit characterized in that a detection output is obtained by performing multiplication one by one and combining two sums and differences of the multiplication results.