JPS63152096A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To facilitate battery backup, by invalidating an address signal which instructs the selection of one of the memory arrays at the time of performing a read/write operation, and validating it at the time of performing a refresh operation. CONSTITUTION:The address selection of a row system is performed by invalidat ing the address signal which instructs the selection of one of plural memory arrays M-ARY1 (M-ARY2) in which dynamic memory cells are arranged and constituted in a matrix shape, at the time of performing the read/write opera tion, and validating it at the time of performing the refresh operation. Therefore, since only a sense amplifier SA-1 (SA-2) provided on a selected memory array M-ARY1 (M-ARY2) is set at an operating state at the time of performing the refresh operation, it is possible to reduce the number of the sense amplifiers being operated in one refresh cycle. In such way, it is easy to perform the battery backup.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is effective when used in an internally synchronized dynamic RAM (pseudo-static RAM) whose peripheral circuit is constituted by a CMO3 (complementary MO3) circuit.

[Conventional technology]

The applicant first developed a pseudo-static RAM that detects changes in address signals and forms various timing signals necessary for the operation of internal circuits.
(See Japanese Patent Application No. 57-164831). In other words, a capacitor that stores information in the form of charge and an address selection MO
By using a dynamic type memory cell composed of 5 FETs and its peripheral circuitry using a CMOS static type circuit, and obtaining the necessary timing signal by detecting changes in the address signal, it is possible to use a static type RAM from the outside. This allows them to be treated equally.

In a dynamic memory cell formed on a semiconductor substrate, the charge accumulated in the capacitor decreases over time due to leakage current or the like. Therefore, in order to always store accurate information in the memory cells, the pseudo-static RAM reads out the information stored in the memory cells and amplifies it before it is lost. An operation of writing to the same memory cell again, a so-called self-refresh function, is provided.

[Problem that the invention seeks to solve]

The present inventor has developed a static RA using the self-refresh function of the above-mentioned pseudo-static RAM.
As a result of considering battery backup similar to M, it was found that the following problems would occur. If the self-refresh operation is performed during battery backup, all the sense amplifiers start their operations at the same time, which consumes a relatively large pulsed current.

Therefore, it is necessary to use a battery with a large current supply capacity. Furthermore, in order to prevent the operating voltage from decreasing due to the pulsed current, it is necessary to connect a capacitor with a large capacitance value to the battery in parallel. Therefore, the bank amplifier power supply becomes large.

An object of the present invention is to provide a semi-quadruple storage device that has a simple configuration and facilitates battery bank up.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the address signal that instructs the selection of one of a plurality of memory arrays consisting of dynamic memory cells arranged in a matrix is disabled during a write/read operation, and enabled during a refresh operation, and the address signal for the row system is disabled. It allows you to make a choice.

[For production]

According to the above-mentioned means, during refresh operation, only the sense amplifiers provided in the selected memory array are activated, so the number of sense amplifiers that operate in one refresh cycle can be reduced, and battery bank up is reduced. This can be easily done using a simple power supply circuit.

〔Example〕

FIG. 1 shows an internally synchronous (so-called pseudo-static RAM) dynamic RA to which the present invention is applied.
A circuit diagram of one embodiment of M is shown. Each circuit element in the figure is manufactured using known CMO3 integrated circuit manufacturing technology.
formed on a semiconductor substrate such as single crystal silicon. In the figure, the MOSFETs whose channel portions are marked with arrows are of the P-channel type.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel part
SFET consists of a source region, a drain region formed on the surface of such a semiconductor substrate, and polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. It consists of a gate electrode. The P-channel MO3FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the substrate gate of the P-channel MO5FET formed thereon. The substrate gate or N-type well region of the P-channel MO3FET is coupled to the power supply terminal Vcc of FIG. The substrate bias voltage generation circuit vBG generates a negative back bias voltage -vbb to be supplied to the semiconductor substrate. by this,
A bank bias voltage is applied to the substrate gate of the N-channel MOSFET, and as a result, the parasitic capacitance between the source and drain of the N-channel MOSFET and the substrate is reduced, resulting in faster circuit operation. Minorities (
Since the minority) carriers are absorbed and the loss of information charges stored in the information storage capacitor is reduced, the refresh period of the memory cell can be lengthened.

The more specific structure of an integrated circuit can be roughly explained as follows.

That is, of the surface portion of the semiconductive substrate made of single crystal P-type silicon and on which the N-type well region is formed, the surface portion other than the surface portion that is used as the active region, in other words, the semiconductor wiring region, the capacitor formation region, and the N-type well region are formed. Channel and P-channel region A relatively thick field insulating film formed by a known selective oxidation method is formed on the surface portions other than the source, drain, and channel formation region (gate formation region) of the SFET. ing. Although not particularly limited, a first polysilicon layer is formed on the capacitor formation region with a relatively thin insulating film (oxide film) interposed therebetween. The first polysilicon layer extends over the field insulating film.

A thin oxide film formed by thermal oxidation of the first polysilicon layer is formed on the surface of the first polysilicon layer. A channel is formed on the surface of the semiconductor substrate in the capacitor formation region by forming an N-type region by ion implantation (or by supplying a predetermined voltage). As a result, a capacitor consisting of the first polysilicon layer, a thin insulating film, and a channel region is formed. The first polysilicon layer on the field oxide film is regarded as a type of wiring.

A second polysilicon layer to serve as a gate electrode is formed on the channel formation via a thin gate oxide film. This 2N polysilicon layer is field-perfect! !
It extends over the film and the first polysilicon layer. Although not particularly limited, word lines and dummy word lines in a memory array, which will be described later, are constructed from a second polysilicon layer.

The active area surface not covered by the field insulating film, the first and second polysilicon layers, is impure? The source, drain, and semiconductor wiring regions are formed by a known impurity introduction technique used as an I introduction mask.

An interlayer insulating film having a relatively thick thickness is formed on the surface of the semiconductor substrate including the first and 27th polysilicon layers, and a conductor layer made of aluminum is formed on this interlayer insulating film. ing. The conductor layer is electrically coupled to the polysilicon layer and the semiconductor region through a contact hole provided in the insulating film below. Although not particularly limited, data lines in a memory array, which will be described later, are composed of conductor layers extending on this interlayer insulating film.

The surface of the semiconductor substrate including the interlayer insulating film and the conductor layer is covered with a final passivation film such as a silicon nitride film and a phosphosilicate glass film.

Although not specifically squared, in this example two memory arrays (or memory mats) M-ARYI and M
- Has ARY2. In the figure, one of the memory arrays M-ARY1 and its selection circuit are exemplarily shown. Although not particularly limited, the memory array M-ARY1 is of a two-intersection (folded bit line or digit line) type.

FIG. 1 specifically shows the pair of data lines. That is, a pair of parallel arranged complementary data lines (
The input/output nodes of a plurality of memory cells each composed of an address selection MO3FET Qm and an information storage capacitor Cs are distributed to bit lines (or deshift lines) D and D with a predetermined regularity as shown in the figure. are combined.

The precharge circuit PC is MO3F shown as a representative.
Like ETQ5, it is composed of a switch MO3FET provided between the complementary data line and D. This M.O.
The 3FET Q5 is turned on by being supplied with a precharge signal φpc generated at the beginning of a memory cycle to its gate, as will be described in detail later with reference to a timing diagram. As a result, in the previous operation cycle, the high level and low level of the complementary data line D are short-circuited by the amplification operation of the sense amplifier SA, which will be described later, and the complementary data line D is set to a precharge voltage of approximately Vcc/2. do. Note that before the RAM is brought into the chip selection state and the precharge MOS FETQ5 and the like are turned on, the sense amplifier SA is rendered inactive. As a result, the complementary data line D maintains a high level and a low level in a high impedance state. Furthermore, the precharge MO3FETQ5 and the like are turned off before the sense amplifier SA is put into operation. As a result, the complementary data line D maintains the above-mentioned half precharge level in a high impedance state.

In such a half precharge method, since the complementary data line D is formed by simply shorting the high level and low level of D, power consumption can be reduced. In addition, in the amplification operation of the sense amplifier SA, the complementary data line D changes in common mode, such as high level and low level, centering on the precharge level, so it is possible to reduce the noise level generated by capacitive coupling. becomes.

The unit circuit USA of the sense amplifier SA is shown as an example, and includes a P-channel MOS FETQ7. Q9
and N-channel MO3FETQ6゜Q8.
It is composed of a MOS latch circuit, and its pair of input/output nodes are the complementary data lines.

It is connected to D. The launch circuit may include, but is not limited to, a parallel P-channel MO3FET.
QI 2. Power supply voltage Vcc is supplied through Ql3, and N-channel MO3FETs QIO and Qll in parallel form
The ground voltage Vss of the circuit is supplied through the circuit. These power switches MO3FF.

TQI O, Ql 1 and MO3FETQ12. Q13
is commonly used for latch circuits (unit circuits) provided in other similar rows within the same memory array or memory mat.

A complementary timing pulse φpal I φpal that activates the sense amplifier SA is applied to the gates of the MO3FETQI O, Ql 2 in the operation cycle,
MO3FETQI 1. Complementary timing pulses φpa2 and φpa2, which are delayed from the timing pulses φpal and φpal, are applied to the gate of Ql3. By doing this, the sense amplifier SA
The operation can be divided into two stages. timing pulse φpa
When l, φpal is generated, that is, in the first stage, MO3FE with relatively small conductance
Due to the current limiting effect of TQ, io, and Q12, the minute read voltage applied between the pair of data lines from the memory cell is amplified without undergoing undesired level fluctuations. After the difference in complementary data line potential is increased by the amplification operation in the sense amplifier SA, the timing pulse φpa2. When φpa2 is generated, that is, when it enters the second stage, MO3F with a relatively large conductance
ETQI 1. Ql 3 is turned on.

The amplification operation of the sense amplifier SA is performed using MOS FETQl.
1 and Q13 are turned on. By performing the amplification operation of the sense amplifier SA in two stages in this way, undesired level changes in the complementary data line can be prevented. Data can be read at high speed.

Although not particularly limited, the row decoder R-DCR is configured by a combination of two divided row decoders R-DCR1 and R-DCR2.

In the figure, a unit circuit (corresponding to four word lines) UDCR of the second row decoder R-DCR2 is shown as a representative. According to the illustrated configuration, the address signals a2 to d9 are connected to N-channel drive MO3FETMO in series configuration.
Supplied to the gates of 3FETs Q32 to Q34. The gate of the P-channel type load MO3FETQ35 is supplied with a control signal XDP, which is set to a low level in an operating state, although this is not particularly limited. As a result, only when the RAM is activated, the NAND gate circuit consisting of the MO3FETs Q32 to Q35 is activated, and the four word line selection signals are generated. The output of the above NAND gate circuit is, on the one hand,
The N-channel type transmission gate MO3FETQ as a switch circuit is inverted by the CMOS inverter IVI and passed through the N-channel type cut MO3FETQ28 to Q31.
It will be sent to gates 24-Q27.

The first row decoder R-DCRI, although its specific circuit is not shown, performs the same transmission as described above, selected by a decode signal formed by decoding 2-bit internal complementary address signals aQ and al, which will be described later. Gate MO3FET
Four types of word line selection timing signals φXOO to φxll are formed from the word line selection timing signal φX through a switch circuit including a cut MO3FET and a cut MO3FET. These word line selection timing signals φx00 to φx
11 is the MO3FET Q24 to Q of the transmission case.
27 to each word line. Note that, although not particularly limited, the row decoder R-DCR1 and the row decoder R-DCR2 may be completely CMOS static type decoders.

Incidentally, when the eight drive MO5FETs are connected in series according to the address signals a2 to i9 as described above, it is necessary to set their combined conductance sufficiently large with respect to the load MO3FET Q35. Therefore, the drive MO3FETs Q32 to Q34 need to be relatively large in size. Therefore, the address signal T instructing the selection of the memory array is
The other address signals a2 to a8 except for 9 are once decoded by another decoder circuit, and then the drive MO3F
It may also be something that reduces the number of ETs. For example, a 1/8 decode output signal is formed by decoding a 3-bit address signal consisting of address signals 12 to 4, and a 1/4 decode output signal is formed by decoding address signals 5 and 16. MO3F which constitutes the above-mentioned Nant gate circuit
It may also be supplied to ETQ32 or Q33. In this case, a total of four drive MOSFETs receive the three decoded output signals and the address signal τ9.
Thus, a Nant gate circuit can be constructed.

Although not particularly limited, timing signal φxOO is set when address signals aQ and al are at low level.
It is set to high level in synchronization with the timing signal φX. Similarly, timing signals φxOI, φxlO and φxll
are set to high level in synchronization with timing signal φX when address signals aO and al, aO and τ1, and TO and τ1 are set to low level, respectively.

As a result, the address signals al and al are transmitted to the word line group (WO, Wl, hereinafter referred to as the first word line group) corresponding to the memory cell coupled to the data %%D among the plurality of word lines. , is regarded as a kind of word line group selection signal for identifying a word line group (W2, W3, hereinafter referred to as a second word line group) corresponding to a memory cell coupled to a data line.

As mentioned above, in the write operation to the Guinami Soku type memory cell consisting of the address selection MOS F ETQm and the information storage capacitor Cs, in order to fully write to the information storage capacitor Cs, in other words, the address selection MOS F In order to prevent level loss of the high level written to the information storage capacitor C3 due to the threshold voltage of ETQm, etc., a word line bootstrap circuit (not shown) activated by the word line selection timing signal φX is installed. provided. This word line bootstrap circuit uses the word line selection timing signal φ
Using X and its delayed signal, the high level of the word line selection timing signal φX is set to a high level higher than the power supply voltage VCC.

By dividing the row decoder into two like row decoders R-DCR1 and R-DCR2, the row decoder R-
The pitch (interval) of DCR2 and the pitch of word lines can be matched. As a result, no wasted space is created on the semiconductor substrate. Between each word line and ground potential, MO
3FETs Q20 to Q23 are provided, and by applying the output of the NAND circuit to their gates, the word line is fixed at the ground potential when not selected.

Although not particularly limited, the word line may have a far end side (
N-channel MO3FETs QI to Q4 for reset are provided at the end opposite to the decoder side, and when these MO3FETs QI to Q4 are turned on in response to the reset pulse φp-, the selected word line is turned on. Reset to ground level from both ends.

The column switch CWI (CW2) is connected to the complementary data line D and the common complementary data vACD, like the N-channel MO3FET Q42°Q43 shown as a representative.
, selectively binds CDs. These MO3FETQ
42. A column decoder C, which will be described later, is connected to the gate of Q43.
- A selection signal from the DCR is provided.

The row address buffer R-ADH is put into an operating state when a chip enable signal GE, which will be described later, is set to a low level, and in that operating state, it takes in and holds address signals AO to A9 supplied from an external terminal. An internal complementary address signal aO-a9 is formed and transmitted to the row decoders R-DCR1 and R-DCR2.

Here, address signal AO supplied from the external terminal
The internal address signal aO having the same phase and the internal address signal aO having the opposite phase are collectively expressed as a complementary address signal aO (the same applies hereinafter). Row decoder R-DCR1 and R
-DCR2 is the complementary address signal 10 as described above.
~Sat9 is decoded and a word line selection operation is performed in synchronization with the word line selection timing signal φX.

On the other hand, the column address buffer C-ADH is put into an operating state when a chip enable signal CB, which will be described later, is set to a low level, and in that operating state takes in address signals AIO to A16 supplied from an external terminal and holds them. and internal complementary address signal on 1
0-16 to form the column address decoder C-
Tell DCR.

The column decoder C-DCR is the address decoder R mentioned above.
Complementary address signals 310 to 31 are constructed by an address decoder circuit similar to -DCR2 and are composed of address signals alO to a16 in opposite phase to internal address signals alo to a16 supplied from column address buffer C-ADB.
6 is decoded to form a selection signal to be supplied to the column switch CWI (CW2) in synchronization with the data line selection timing signal φy.

An N-channel precharge MO3FETQ44 constituting a similar precharge circuit as described above is provided between the common complementary data lines CD and CD. The common complementary data lines CD and CD are connected to the sense amplifier US of the above unit.
A pair of input/output nodes of main amplifier MA having the same circuit configuration as A are coupled. The output signal of this main amplifier is sent to the external terminal Dou via the data output buffer DOB.
is sent to t. In the case of a read operation, the data output buffer DOB is activated by the timing signal φr-, amplifies the output signal of the main amplifier MA, and sends it out from the external terminal I10. In addition, in the case of a write operation,
The output of the data output buffer DOB is placed in a high impedance state by the timing signal φr.

The common complementary data lines CD, CD are coupled to the output terminals of the data input cover sofa I)rB. In the case of a write operation, the data input cover sofa DIB uses its timing signal φ
rh, and writes into the selected memory cell by transmitting a complementary write signal in accordance with the write signal supplied from the external terminal Din to the common complementary data lines CD, CD. Note that in the case of a read operation, the output of the data input buffer sofa DIB is brought into a high impedance state by the timing signal φrw.

The various timing signals mentioned above are generated by the following internal control signal generation circuit TG. Internal control signal generation circuit TG
are two external control signals CE (chip enable signal)
, WE (write enable signal) and an address signal change detection signal φ formed by an address signal change detection circuit ATD provided therein and receiving the address signal ao-a16, various types necessary for memory operation are performed. Forms and sends a timing signal. Although not particularly limited, the address signal change detection circuit ATD can be configured to detect address signal a.
0 to 16 and their delayed signals, and an OR circuit that receives the output signals of these exclusive OR circuits. This address signal change detection circuit ATD detects the address signals aO to A1.
If the level of any one of 6 changes,
An address signal change detection pulse φ is formed in synchronization with the change timing. As a result, the RAM is operated by an internally generated timing signal, so the I
From outside C, it can be operated in the same way as a static RAM (pseudo static RAM).

Further, the internal control signal generation circuit TG receives the address signal a9 and a signal srf supplied from the automatic refresh control circuit REFC, which will be described later, and receives the address signal a9 from the memory array M-
Sense amplifier SAI compatible with ARY1 and M-ARY2
, SA2 operation timing signal φpa (φpa1.φp
al and φpa2. φpa) is generated as described below.

The circuit designated by the circuit symbol REFC is an automatic refresh circuit, which includes a timer circuit, a refresh address counter, etc., as will be described later. Although this automatic refresh circuit REFC is not particularly limited, when the refresh control signal REF supplied from an external terminal is kept at a high level for a relatively long time of one memory cycle or more, the timer circuit detects this and performs a self-refresh. Start the sosh operation. That is, in the self-refresh operation, while the signal REF is at a low level, a continuous refresh operation is performed by an address increment operation according to a cycle set by the timer circuit. Furthermore, when the signal REF is brought to a low level for a short period of time such as the 1 cycle, an auto-refresh operation is performed. That is, each time the signal REF is set to low level, the refresh address is incremented. The address counter circuit generates refresh address signals aQl to a9''. These refresh address signals aQl to a
91 is 1:l"77)' and 7!, 7' via the row address buffer R-ADB with multiplexer function.
The data is transmitted to the D-da R-DCRI and R-DCR2, and a refresh operation is performed by a row-related selection operation.

In order to reduce the peak current value in the self-refresh operation, in this embodiment, in the self-refresh operation mode, the automatic refresh control plate circuit RE
Ha [signal sr] indicating self-refresh operation from FC
f is formed. Although this signal is not particularly limited, the unit circuit UDC constituting the row decoder R-DCR2
MO3FE provided in the Nant gate circuit in R2
Supplied to the gate of TQ36. This MO3FETQ3
6 is provided in parallel with MO3FETQ34 which receives address signal T9 instructing selection of a memory array or memory mat. The signal srf instructs whether the address signal 9 is valid or invalid. That is, when the signal srf is set to high level, the MO3FET
Since Q36 is turned on, other address signals a are
2 to a8 determine the output signal of the Nant gate circuit. On the other hand, when the signal srf is set to a low level, the MO3FET Q36 is turned off, so when the inverted address signal a9 is at a high level,
A row selection operation on the memory array M-ARYl side is performed. At this time, the row selection operation of memory array M-ARY2 is not performed due to the low level of non-inverted address signal a9. Accordingly, memory array M-ARY2
The sense amplifier SA2 is also rendered inactive.

In other words, the operation timing signal φ of the sense amplifier SA2
paLφpa2 is kept at low level, and timing signals φpal and φpa2 are kept at high level. Conversely, when the non-inverted address signal a9 is at a high level, the row selection operation on the memory array M-ARY2 side is performed. At this time, the selection operation of the row system of the memory array M-ARY1 is not performed due to the low level of the inverted address (No. 8 a9).

In response, sense amplifier SAI of memory array M-ARY1 is also rendered inactive. That is, the operation timing signal φpal of the sense amplifier SAI.

φpa2 is kept at a low level, and the timing signal φpaLφpa2 is kept at a high level.

From the above, although not shown, the internal complementary address signal 9 is the operation timing signal φpaLφp of the sense amplifiers SAI and SA2 according to the signal srf.
It also controls the generation of al and φp a 2 +φpa2.

FIG. 2 shows a circuit diagram of an embodiment of the automatic refresh control circuit REFC.

The refresh control signal REF supplied from the external terminal is not particularly limited, but on the one hand, the P-channel MO3FF in parallel form, TQ50 and Q51, and the N in series form.
Channel MOS FET Q MO3 serves as one input terminal of the first input circuit TBI consisting of a CMOS NAND gate circuit consisting of 52 and Q53.
It is transmitted to the gates of FETQ50 and Q53. On the other hand, the signal REF is connected to a P-channel MOS in parallel form.
FETQ54 and Q55 and N-channel MO3FETQ56 in series form. The signal is transmitted to the gates of MO3FETQ54 and Q57, which serve as one input terminal of the second input circuit TB2, which is a CMOS Nant gate circuit consisting of Q57. Note that an electrostatic breakdown prevention circuit is provided between the input terminals of each of the input circuits TB1 and IB2 and the external terminal, but it is omitted in the figure because it is not directly related to this invention. .

Each MO3FETQ that constitutes the first input circuit IBI
50 to Q53 are formed relatively large in size to speed up the auto-refresh operation, so that they have a relatively large current driving capability. On the other hand, each M constituting the second input circuit IB2
The O3FETs Q54 to Q57 are formed relatively small in size in order to reduce power consumption in self-refresh operation, so that they have only a relatively small current driving capability.

The output signal ref of the first input circuit TBI is supplied on one side to the internal control signal generation circuit TO, and on the other hand to the set terminal S of the timer circuit TM of the refresh control circuit. The output signal ref' of the second input circuit TB2 is supplied to the reset terminal R of the timer circuit TM.

The timer circuit TM receives the internal signal re as described later.
When f is at a high level for more than a predetermined time such as one memory cycle (refresh control signal REF is at a low level), this is detected and the self-refresh signal srf is set at a high level. This self-refresh signal srr
In response to the high level of the address counter circuit ADC, the address counter circuit ADC starts counting pulse signals generated by, for example, a built-in oscillation circuit, and outputs the refresh address signal a.
Forms Ql to a9°. Although not shown, the refresh signal ref performs a switching operation to the row address eight sofa R-ADB multiplexer circuit shown in FIG. It is transmitted to the decoder R-DCR. by this,
A refresh operation according to the refresh address signals aO" to a9" is started.

Further, the self-refresh signal srf is the second
The signal is transmitted to the gates of MO3FETs Q55 and Q56, which are the other input terminals of the Nant gate circuit that constitutes the input circuit IB2. As a result, the second input circuit IB2 turns on the N-channel MO3FET Q56, so that the second input circuit IB2 is changed from a substantially inactive state to an active state at the same time as the refresh starts. That is, the internal signal ref corresponds to the control signal REF supplied from the external terminal.
'. The self-refresh control signal srf is applied to the M○5FETQ51. This will be communicated to the gate of Q52.

As a result, the first input circuit IBI is substantially rendered inactive since its N-channel MO3FET Q52 is turned off by the low level of the self-refresh signal 5rfO, which is inverted by the start of the self-refresh operation. That is, the first input circuit IBI is
A high-level internal signal ref that does not respond to the signal REF supplied from the external terminal is formed.

By substantially switching the operation of the two input circuits IBI and IB2, during the self-refresh period, the control signal REF is applied to the MO3FETQ5 at a low level of TTL level (approximately 0.8■) to the first input circuit IBI.
Even if 3 is turned on weekly, it does not consume DC current, and only a small amount of DC current is consumed in the second input circuit IB2. This makes it possible to reduce power consumption during the self-refresh period.

At the end of the self-refresh operation, the control signal REF
changes from low level to high level.

The second input circuit IB2 changes the internal signal srf' from high level to low level in response to the change in the signal REF. As a result, the timer circuit TM is placed in a reset state, and the self-refresh signal srf is brought to a low level to complete the self-refresh operation. By the low level of the self-refresh signal srf, the first input circuit IBI is switched to a substantially operating state, and the second input circuit IB2 is switched to a substantially non-operating state.

During the self-refresh operation as described above, the row-related address selection circuits of the memory arrays M-ARYI and M-ARY2 are selectively activated as described above in response to the self-refresh signal srf, and the selection operation is performed. Sense amplifiers SA1 and SA2 are selectively activated in response to this. Therefore, as mentioned above, memory array M-A
Two memory arrays (such as RY1 and M-ARY2)
(memory mat), the current consumption (peak current) during self-refresh operation can be halved. Therefore, the power supply circuit can be simplified by reducing the peak current in self-refresh, which is often used mainly during battery bank-up operation. In other words, the bank-up power source can be configured with a battery having a relatively small current supply capacity and a capacitor having a relatively small capacity value.

Note that if the signal REF is set to low level for a period shorter than the time set by the timer circuit, the signal RE
In response to f, the address counter circuit ADC performs an increment operation of +1, and an auto-refresh operation is performed one step at a time. At this time, the self-refresh signal s
rf is not formed, both memory arrays M-
ARY1 and M-ARY2 perform refresh operations at the same time. As a result, the refresh time can be shortened, so writing/reading can be performed at high speed. In other words, responsiveness to write/read access can be increased.

Further, the timer circuit TM may be provided with an oscillation function. That is, the refresh control signal R
If you keep EF at low level, at each set time,
The timer circuit may generate one pulse signal to form the step pulse of the address counter circuit ADC. In this case, the self-refresh signal srf may be generated by a latch circuit that is set in response to the output signal of the timer circuit.

FIG. 3 shows a timing diagram for explaining an example of the operation of this embodiment circuit.

When the refresh control signal REF becomes low level, it is regarded as an auto-refresh operation as described above, and the address counter circuit ADC performs a +1 increment operation. As a result, at least one address signal ai changes, and an address signal change detection detection pulse φ is formed by the address signal change detection circuit ATD. The internal control signal generation circuit TG generates memory arrays M-ARY1, M-A in synchronization with this address signal change detection pulse φ.
Reset the selection circuit of RY2 once.

That is, due to the address signal change detection pulse φ,
Sense amplifier SA timing pulse φpa (φpa
l, φpa2) to low level (timing pulse φpaLφpa2 is set to high level, although not shown)
The power switch MO3FET of the sense amplifier SA is turned off, and the complementary data! l, 'iD, D to high level (Vcc level) according to previous operation.

The low level (Vss level) is held in a floating state. By setting the word line selection timing signal φX to a low level, the selected word line WL is drawn from a high level to a low level (not shown), and the word line is inserted.

Next, set the precharge pulse φpc to high level,
By turning on the precharge MO3FE'[', the complementary data line D is short-circuited and precharged to the Vcc/2 level. Both D of the above complementary data line are V
After waiting for the time to reach the precharge level of cc/2, the precharge pulse φpc is set to low level. Then, the word line selection timing signal φX is raised to a high level.

In synchronization with the rise of this word line selection timing signal φX, one word line WL determined by the complementary address signal 0-18 (initially, only an auto-refresh operation is performed, so the address signal a9 is invalidated) goes high. It rises to a level (not shown) and is placed in a selected state. As a result, a plurality of memory cells coupled to the selected word line are selected, and the information storage capacitor of each memory cell is coupled to the data line D (or D) via the address selection MOS FET. . That is, the input/output node of one memory cell of each complementary data line D is coupled to one data line D (or D). As a result, a read level appears in the data fiD (or D) due to charge dispersion between the accumulated charge of the memory cell and the precharged charge of the data line. Note that the other data line D (or D) remains at the above precharge level since no memory cell is coupled thereto.

Next, timing pulse φpa is generated to operate sense amplifiers SAI and SA2. As a result, the complementary data line D is at a low level according to the storage charge of the information storage capacitor Cs.

amplified to a high level. This kind of sense amplifier SA
Since the amplified signal resulting from the operation of I and SA2 is transmitted to the memory cell, the memory information that is about to be lost is rewritten (refresh operation).

Note that if the signal REF continues to be at a low level from then on, the timer circuit TM detects this and generates the self-refresh signal srf.

As a result, the refresh address signals aQl to a9' formed by the address counter circuit ADC
Since the address signal change detection pulse φ is formed in accordance with the change in (stepping operation), the internal control signal generation circuit TG is activated again, and a self-refresh operation is performed by the operation of the row-related address selection circuit. At this time, address signal 9 is enabled, so depending on its level, memory array M-ARYI or M
- Refresh operation is performed only for ARY2.

The effects obtained from the above examples are as follows. That is, (1) An address signal that instructs the selection of one of a plurality of memory arrays made up of dynamic memory cells arranged in a matrix is disabled during write/read operations, and enabled during refresh operations. By selecting the address of the system, only the sense amplifiers provided in the selected memory array are activated during refresh operation, which reduces the number of sense amplifiers that operate in one refresh cycle. , an effect can be obtained in that battery back amplifier can be easily performed using a simple @source circuit.

(2) Among the above refresh operations, by refreshing each memory array during self-refresh operation, the above-mentioned battery bank amplifier can be easily performed, and all memory arrays are simultaneously refreshed during auto-refresh. This provides the effect of increasing responsiveness during writing/reading.

(3) By providing the above self-refresh function to an internally synchronized dynamic RAM (pseudo-static RAM), it can be treated in the same way as a static RAM. As a result, it is possible to obtain a semiconductor memory device that has both the large storage capacity of a dynamic RAM and the ease of handling of a static RAM.

(1) The first input circuit, which has a relatively large drive current, serves as an input circuit that receives a control signal that instructs self-refresh operation.
input circuit and a second circuit with a relatively small drive current.
an input circuit, and by rendering the first input circuit substantially inactive and causing the second input circuit to be substantially operational during the self-refresh period.
Current consumption in refresh mode can be reduced even under a TL level control signal. As a result, (1) above
Combined with this effect, it is possible to obtain the effect that battery backup can be performed even more easily.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, a refresh operation may be performed for each memory array even during an auto-refresh operation. Further, the reference voltage required for the read operation of the memory cell of the dynamic RAM may be formed using a dummy cell. Furthermore, the specific circuit configurations of other peripheral circuits constituting the dynamic RAM can take various embodiments. For example, the number of memory arrays or memory mats may be greater than the above two, such as four or more. In this case, the address signal indicating the selected memory array or memory mat consists of 2 or 3 bits.
The circuit that selects row-related addresses in response to these address signals can take various embodiments, such as one that selectively generates a word line selection timing signal. Alternatively, the row-related and column-related address signals may be supplied in time series from a common external terminal in synchronization with the address strobe signal. Further, the control signal instructing the refresh operation may be one that causes the self-refresh operation to be performed by keeping the substantial chip enable signal, for example, the chip enable signal CE, at a low level, or a combination of two address strobe signals ( Row address strobe signal RA
Column address strobe signal C before the falling edge of S.
AS) or by combining these substantial chip selection signals with other control signals such as the write enable signal WE.

The present invention can be widely used in semiconductor memory devices using dynamic memory cells.

〔Effect of the invention〕

A brief description of the effects obtained by typical inventions disclosed in this application is as follows. In other words, the address signal that instructs the selection of one of a plurality of memory arrays consisting of dynamic memory cells arranged in a matrix is disabled during a write/read operation, and enabled during a refresh operation, and the address signal for the row system is disabled. By allowing us to make choices;
During a refresh operation, only the sense amplifiers provided in the selected memory array are in operation, so the number of sense amplifiers operating in one refresh cycle can be reduced, making it easy to perform battery hack-up.

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
FIG. 2 is a circuit diagram showing an embodiment of the automatic refresh control circuit, and FIG. 3 is a timing diagram for explaining its operation. M-ARYI (M-ARY2) ・・Memory array, PCI (PO2) ・・Precharge circuit,
SAl (SA2)...Sense amplifier, USA...
・Unit circuit, CWl (SW2) ・・Column switch, R-ADB ・・Row address buffer, C-ADB
・・Column address buffer, R-DCR1゜R-DC
R2...Row decoder, UDCR2...Unit circuit, C-
DCR: Column decoder, MA: Main amplifier, D
OB...data output cover sofa, DIB...data person cover sofa, VBG...board via, large generation circuit, TG...
Internal control signal generation circuit, ATD...address signal change detection circuit. Automatic refresh control circuit REFC, TM...Timer circuit, ADC...Address counter circuit, IBI,
IB2...Input circuit

Claims (1)

[Claims] 1. A plurality of memory arrays configured by dynamic memory cells arranged in a matrix, and an address signal instructing selection of one of the plurality of memory arrays are invalidated during write/read operations. 1. A semiconductor memory device comprising: a row-related address selection circuit that is enabled during a refresh operation. 2. The above refresh operation is performed by an automatic refresh control circuit having a self-refresh function based on an internally generated refresh address signal when a control signal supplied from an external terminal is at a predetermined level for a certain period of time or more. A semiconductor memory device according to claim 1, characterized in that: 3. The semiconductor memory device is an internally synchronized dynamic RAM in which a time-series operation timing signal necessary for internal operations is formed according to a change detection signal of an address signal.
The first or second claim characterized in that
The semiconductor storage device described in 1.