JPH035992A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To equivalently improve speed for the amplifying operation of a main amplifier by providing the amplifier circuit of a latch style to be activated by a prescribed timing signal to a common complementary data line to be connected to a complementary data line to which a memory cell is coupled through a column switch circuit. CONSTITUTION:The input of a main amplifier MA and an amplifier circuit AMP including an amplifier MOSFET of the latch style to be activated by the prescribed timing signal are connected to the common complementary data line to be connected through the column switch circuit to the complementary data line to which the memory cell is coupled. Accordingly, a read signal, which is transmitted to the common complementary data line, is amplified in the manner of a direct current as well by the amplifier circuit AMP of the latch style. Thus, the speed for the amplifying operation of the main amplifier MA can be equivalently improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and relates to a technique effective for use in, for example, a dynamic RAM (random access memory).

[Conventional technology]

Signals read from the dynamic memory cells arranged in a matrix are transmitted to the input of the main amplifier, which is the front stage of the output circuit, where they are amplified and sent out from the external terminal through the output circuit. Regarding dynamic RAM, there is, for example, ``Very LSI Device Handbook,'' published by Sanence Forum Publishing, November 28, 1981, pages 1, 291 to 305.

[Problem to be solved by the invention]

The stored information from the selected memory cell appears on the data line as a minute potential difference. This minute potential difference is amplified by a sense amplifier coupled to the data line and transmitted to the common complementary data line via the column switch circuit. Here, the common complementary data line is a switch M that constitutes a column switch circuit.

・Has a relatively large parasitic capacitance due to the combination of 5 FETs. Therefore, the read signal amplified by the sense amplifier is brought to a relatively small level at the input section of the main amplifier by operating the column switch circuit and coupling the complementary data line and the common complementary data line with the above-mentioned large parasitic capacitance. Become. At the same time, when the common complementary data line is coupled to the complementary data line due to the above column selection operation, they constitute a heavy load on the sense amplifier. A problem arises in that the expansion by the sense amplifier becomes slow and the amplification operation in the main amplifier section takes time.

Furthermore, in a one-transistor type dynamic memory cell, stored charges are destructively read out by a word line selection operation. Therefore, due to the amplification operation of the sense amplifier,
A rewrite operation is required to return the storage capacitor to its original charge state. In this rewrite operation, the load on the sense amplifier becomes heavy due to the coupling of the common complementary data line to the complementary data line in conjunction with the column selection operation, and if the amplification operation takes time as described above, the load on the sense amplifier increases accordingly. The rewriting operation of the memory cell also becomes slower.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of speeding up read operations.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a latch-type amplification MOSFET activated by the input of the main amplifier and a predetermined timing signal is connected to a common complementary data line connected to a complementary data line to which memory cells are coupled via a column switch circuit. and an amplifier circuit including.

[For production]

According to the above-mentioned means, the read signal transmitted to the common complementary data line is also DC-amplified by the latch-type amplifier circuit, so that the speed of the amplification operation of the main amplifier is equivalently increased.

〔Example〕

FIG. 1 shows a dynamic RA to which this invention is applied.
A schematic circuit diagram of one embodiment of M is shown. Each circuit element in the figure is formed on a single semiconductor substrate, such as single crystal silicon, by a known CMO5 integrated circuit manufacturing technique. In the figure, MOSFETs whose channel portions (back gates) are marked with arrows are P-channel type.

Although not particularly specific, integrated circuits are formed on semiconductor substrates consisting of single crystal P-type silicon. N channel MOS
An FET consists of an N-type source region, a drain region formed on the surface of a semiconductor substrate, and a polysilicon film formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. It consists of a gate electrode consisting of: P-channel MOSFET
is formed in an N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOSFET, ie, the N-type well region, is coupled to the power supply terminal VCC of FIG.

Substrate bias voltage generation circuit BG is operated by a positive power supply voltage such as +5V supplied between the power supply terminal Vcc and the reference potential terminal (ground terminal) Vss, and generates a negative back bias to be supplied to the semiconductor substrate. Generates voltage -vbb. As a result, N-channel MOS F E
A back bias voltage is applied to the substrate gate of T, and as a result, the parasitic capacitance value between the source and drain of the N-channel MOSFET and the substrate is reduced, and faster operation of the circuit is achieved. In addition, minority carriers generated in the substrate are absorbed into the back bias power supply side, which reduces the leakage current of circuit elements and reduces the loss of information charges accumulated in the information storage capacitor. The cycle can be lengthened.

The more specific structure of an integrated circuit can be roughly explained as follows.

That is, out of the surface portion of the semiconductor substrate made of single crystal P-type silicon and on which the N-type well region is formed, the surface portion other than the surface portion that is used as the active region, that is, the semiconductor wiring region, the capacitor formation region, and the N-channel and P-channel region A relatively thick field insulating film formed by a known selective oxidation method is formed in areas other than the surface portions used as the source, drain, and channel formation region (GaI/formation region) of the SFET. ing. Although the capacitor formation region is not particularly limited, a first polysilicon layer is formed via a relatively thin insulating film (oxide film) as a dielectric film for the capacitor. The first polysilicon layer extends over the field insulating film. A thin oxide film formed by thermal oxidation of the first polysilicon layer is formed on the surface of the first polysilicon layer. A channel is formed on the surface of the semiconductor substrate in the capacitor formation region by forming an N-type region by ion implantation or by supplying a predetermined voltage. As a result, a capacitor consisting of an IN-th polysilicon layer, a thin insulating film, and a channel region is formed. The first polysilicon layer on the field oxide film is regarded as a type of wiring.

A second polysilicon layer is formed as a gate electrode on the channel forming region with a thin gate oxide film interposed therebetween. This second polysilicon layer extends over the field insulating film and over the first polysilicon layer. Although not particularly limited, word lines and dummy word lines in a memory array, which will be described later, are constructed from a second polysilicon layer.

Source, drain, and semiconductor wiring regions are formed on the surface of the active region not covered by the field insulating film and the first and second polysilicon layers by a known impurity doping technique that uses them as an impurity doping mask. .

A relatively thick glabellar insulating film is formed on the surface of the semiconductor substrate including the first and second polysilicon layers, and a conductor layer made of aluminum is formed on this glabellar insulating film. . The conductor layer is electrically coupled to the polysilicon layer and the semiconductor region through a contact hole provided in the insulating film below. A data line in a memory array, which will be described later, is composed of a conductor layer extending on this glabella insulating film, although it is not particularly limited.

The surface of the semiconductor substrate including the top of the glabella insulating film and the top of the conductor layer is covered with a final passivation film made of a silicon nitride film and a phosphosilicade glass film.

Although not particularly limited, the memory array MARY is of a two-intersection (folded-pitch 14') type. A pair of rows is specifically shown in FIG. 1.

A pair of parallel arranged complementary data lines (also referred to as bit lines or digit lines) DO, DO
Input/output nodes of each of a plurality of memory cells constituted by an address selection MOSFET Qm and an information storage capacitor Cs are distributed and coupled with a predetermined regularity as shown in the figure.

The precharge circuit PC is a MOSF shown as a representative.
Complementary data line DO, like ETQ5.

It is composed of a switch MO5FET provided between 00 and 00. MOSFET Q5 is turned on by a precharge signal φpc supplied to its gate when the chip is not selected or before the memory cell is selected. As a result, the complementary data lines Do, which have shifted to high and low levels due to the amplification operation in the previous operation cycle of the sense amplifier SA, which will be described later, become
Since they will be short-circuited via SFETQ5, both will be at a precharge voltage level of approximately Vcc/2 (HVC). Note that when the chip is left in a non-selected state for a relatively long time, the precharge level is reduced due to leakage current or the like. Therefore, although not particularly limited, in this embodiment, the switch MO, which is operated by the precharge signal φpc together with the MOSFET Q5,
SFETs Q45 and Q45 are provided to supply half precharge voltage HVC to complementary data lines Do, Do. Although the specific circuit is not shown, the voltage generation circuit that forms this half precharge voltage HVC is
It is composed of a voltage dividing circuit in which an SFET is used as a voltage dividing resistor. It is sufficient for the voltage generation circuit to have a relatively small current supply capacity to compensate for the leakage current, etc., and the MOS FET as a voltage dividing resistor is designed to have a relatively small conductance. This suppresses an increase in power consumption due to the voltage generation circuit.

Note that the sense amplifier SA is brought into a non-operating state before the precharge MOSFET Q5 and the like are turned on due to transition of the RAM to a chip non-selected state or the like. As a result, the complementary data lines DO, Do maintain a high level and a low level in a high impedance state. The sense amplifier SA is activated when the RAM is activated. The precharge MOSFETs Q5, Q45, Q46, etc. are turned off before the sense amplifier SA is operated. As a result, the complementary data lines DO, Do maintain the above half precharge level in a high impedance state.

In such a half precharge method, since the complementary data lines DO and DO are formed by simply shorting the high level and low level, power consumption can be reduced. In addition, in the amplification operation of the sense amplifier SA, the complementary data lines DO, Do
It is possible to reduce the noise level generated by capacitive coupling when the voltage is changed in a differential mode such as between a high level and a low level.

Sense amplifier SA is composed of a plurality of unit circuits each having a one-to-one correspondence with complementary data lines of memory array MARY. Each unit circuit USA includes a P-channel MOSFET Q7, one of which is exemplarily shown in FIG.
．． Q9 and N-channel MOSFET Q6. A pair of input/output nodes thereof are coupled to corresponding complementary data lines Do, Do. The latch circuit may include, but is not particularly limited to, a parallel P-channel MOSFET QI as a power switch or operation control element.2. A power supply voltage Vcc is supplied through Ql3, and a parallel N-channel MOSFET QI is used as a power switch or an operation control element.
The ground voltage Vss of the circuit is supplied through O and Ql. These power switch MOSFETQI O,
Ql 1 and MOSFET Q42. Ql 3 is a latch circuit (
Commonly used for unit circuits). In other words, the sources PS and SN of the P-channel MO8FET and N-channel MO8FET in the latch circuit in the same memory array are commonly connected. Although not particularly limited, MOSFETs QI0 and Q12 are made to have relatively small conductance, and MOSFETs QI0 and Q12 are
TQI 1 and Q13 are made to have relatively large conductance.

Complementary timing pulses φpal and φpal that are set to high and low levels to activate the sense amplifier SA in the operation cycle are applied to the gates of the MOSFETs QI O and Ql 2, and the MOSFETs
QI 1. At the gate of Ql3, a complementary timing pulse φpa2 + which is brought to high level and low level with a delay from the timing pulse φpal r φpal is provided.
φpa2 is applied. By doing so, the operation of sense amplifier SA is divided into two stages. When the timing pulse φpal+φpal is generated, that is, in the first stage, the minute read voltage applied between the pair of data lines from the memory cell due to the current limiting effect of MOSFETs Q10 and Q12, which have relatively small conductance, is undesired. The signal is amplified without significant level fluctuations. After the difference in complementary data line potential is increased by the amplification operation in the sense amplifier SA,
Timing pulse φpa2. When φpa2 is generated,
That is, in the second stage, MOSFETQI with relatively large conductance 1. Ql3 is turned on. The amplification operation of the sense amplifier SA is performed using MOSFETQ.
I 1. This is speeded up by Ql 3 being turned on. In this way, the sense amplifier SA is divided into two stages.
By performing the amplification operation, data can be read out at high speed while preventing undesired level changes in the complementary data lines.

Although not particularly limited, row decoder R-DCR is configured to select a word line by a combination of two divided row decoders R-DCRI and RDCR2. The first row decoder R-DCRI receives 0. Decode Sat1, timing signal φX
The decode output φ at the timing determined by
x00 to φxll are formed. The second row decoder R-DCR2 includes a plurality of unit circuits UDCR, one for each of four word lines. However, in FIG. 1, one unit circuit of the second row decoder R-DCR2 (four word lines) is shown as a representative. According to the illustrated configuration, although not particularly limited, address signals 12 to 12 are connected to N-channel drive MOSFs connected in series.
It is supplied to the gates of ETMOSFETs Q32 to Q34. The gate of the P-channel type load MOSFET Q35 is supplied with a one-shot pulse φ that is temporarily brought to a low level during its operation. This one shot pulse φ is
For example, the row address strobe (low level of No. 1 RAs causes the row address buffer R-ADB (although not essential, in FIG. 1, the row address buffer R-ADB
DB and column address buffers C-ADB (shown together) are kept at a low level from the time when the operation timing signal φa is generated until the word line selection timing signal φX is generated. Therefore, the one shot pulse φ is generated by the logic circuit within the timing generation circuit TG that receives these timing signals. The above load MOSFET Q35 and drive MOSFET Q32 to Q3
4 constitutes a NAND gate circuit, and the four word line selection signals are formed. On the one hand, the output of the Nant gate circuit is inverted by a CMOS inverter IVI and output to an N-channel cut MOSFE.
The signal is transmitted through TQ28 to Q31 to the gates of N-channel transmission gate MOSFETs Q24 to Q27 as switch circuits. Since the Nant gate circuit is driven by a one-shot pulse φ to perform dynamic operation, the P-channel gate circuit receives the output of the inverter circuit IV1 at its gate so as to maintain the output level statically. Type MOSFETQ36
are combined. Above inverter circuit IVI and MOS
FETQ36 constitutes a substantial latch circuit. The operation of such a latch circuit is as follows. That is,
CMOS inverter circuit IVI that sends out the above output signal
The output signal of the P-channel type second load MOSFETQ, which is connected in parallel with the load MOSFETQ35,
It will be returned to Gate 36. As a result, when the output signal of the Nant gate circuit is set to high level, the second load MOSFET Q36 is turned on by the low level of the output signal of the CMOS inverter circuit TVI, and the output signal is maintained at high level. Become. In addition, if the output signal of the Nant gate circuit is low level, in other words, all the address signals 12 to 12
MOSFETQ32~Q driven by the high level of am
34 are all in the on state, the output signal of the CMOS inverter circuit IVI is set to high level in response to this, and the load MOSFET Q36 is turned off. As a result, in the Nant gate circuit, no direct current is consumed through the drive MOSFETs Q32 to Q34 turned on after the one shot pulse φ is set to high level. Note that the second row decoder R
-DCR2 may be a complete CMOS static decoder instead of the above configuration.

The first row decoder R-DCR1 receives 2-bit complementary address signals aQ, al, although its specific circuit is not shown.
a decoder for decoding the MOS FETQ24., and the MOS FETQ24. Four types of word line selection timing signals φ×00 are output from the word line selection timing signal φX through a switch circuit consisting of a transmission game (similar to Q28, etc.) MOSFET and cut MOSFET.
to φxll are formed. These word line selection timing signals φxOO to φxll are transmitted to each word line via the transmission gate and the MOSFETs Q24 to Q27. Note that, although not particularly limited, the row decoder R-
Like the row decoder R-DCR2, the DCR1 may perform a word line selection operation in response to one shot pulse φ, or may be a completely CMOS static type decoder as described above.

Although not particularly limited, the timing signal φxoO is set to a high level in synchronization with the timing signal φX when both address signals aO and al are set to a low level. Similarly, timing signals φx01, φxlO and φ+
dl are address signals aO and al, and aO
and al, and when aO and al are set to low level, they are respectively set to high level in synchronization with timing signal φX.

As a result, the address signal al (and al) is coupled to the data line of the plurality of word lines, and the word line group (WO2W1, hereinafter referred to as the first word line group) corresponding to the memory cell is connected to the data line of the plurality of word lines. and the word line groups (W2) and W3) corresponding to the memory cells coupled to the data line, and the second
It is regarded as a kind of word line group selection signal for identifying a word line group (referred to as a word line group).

A MOSFET Q20 is connected between each word line and the ground potential.
~Q23 is provided, and by applying the output of the NAND circuit to its gate, the word line is fixed at the ground potential when not selected. Although not particularly limited, switches M○5FETs Q38 to Q41 are provided at the far end side of each word line (the end opposite to the decoder side).

The gates of these MOSFETs Q38 to Q41 are supplied with a timing signal -COO-WCII having an opposite phase to the timing signals φx00 to φxll. This allows unselected word lines to be fixed at the circuit's ground potential, thereby preventing unselected word lines from rising to an intermediate potential in response to the rise of the selected word line due to capacitive coupling between word lines. .

Row decoder R-DCR with R-DCRI and R-DCR2
In the case of dividing the row decoder R-DCR2 into two parts as shown in FIG. It becomes easy to match the pitch.

Column switch C-5W is shown as a representative N
Channel MOSFETQ42. Like Q43, it consists of a switch MOSFET provided between the complementary data lines DO, Do and the common complementary data lines CD, CD. Selection signals from column decoders C- and DCR, which will be described later, are supplied to the gates of these MOSFETs Q42) and Q43.

The operation of the row address buffer R-ADB is controlled by a timing signal φax generated by a timing generation circuit TG, which will be described later, based on a row address strobe signal RAS supplied from an external terminal, and the timing signal φax is generated. At this time, the address signal AOxAm supplied to the external terminal is taken in as a row address signal, and the row address decoder R-DCR
1 and R-DCR2. Note that for convenience, the internal address signal in phase with the address signal AO supplied from the external terminal and the internal address signal in opposite phase are collectively referred to as a complementary address signal aO (the same applies hereafter).

The row address buffer R-ADB is also made to have a multiplexer function. When a control signal φrf is output from a refresh control circuit REFC, which will be described later, the row address buffer R-ADB takes in address signals ol-am' from the refresh control circuit REFC instead of an address signal from an external terminal.

Row address decoders R-DCRI and R-DCR2 are
As described above, the complementary address signals aO-am are decoded and a word line selection operation is performed in synchronization with the word line selection timing signal φX.

The operation of the column address buffer C-ADB is controlled by a timing signal φay generated by a timing generation circuit TG based on a column address strobe signal CAS supplied from an external terminal. Address signal AO=An supplied to the terminal is taken in as a column address signal to form internal complementary address signal aQxan to be supplied to column address decoder C-DCR.

The column decoder C-DCR is basically constituted by an address decoder circuit similar to the address decoder R-DCR2 described above, and decodes the complementary address signal a□-an supplied from the column address buffer C-ADB to output the data line. A selection signal to be supplied to the column switch C-5W is formed in synchronization with the selection timing signal φy.

As mentioned above, in this figure, for convenience, the row address buffer R-ADB and the column address buffer C-A are
DB are collectively represented as address buffers R and C-ADB.

Between the common complementary data lines CD and CD is an N-channel precharge MOSF constituting a precharge circuit.
ETQ44 is provided. This common complementary data line C
D and CD are coupled to a pair of input/output nodes of an amplifier circuit AMP having a circuit configuration similar to that of the sense amplifier USA of the unit described above, and an input terminal of a main amplifier MA as described later.

The amplifier circuit AMP is activated by the timing pulse φρa', and the main amplifier MA is activated by the timing pulse φρa'.
activated by ma. The amplified output signal of main amplifier MA is supplied to the input terminal of data output buffer DOB. The operation of data output buffer DOB is controlled by timing signal φrw.

In the case of a read operation in normal operation, the data output buffer DOB is activated by the timing signal φr-, and sends a data signal corresponding to the output signal of the main amplifier MA to the external terminal Dout. Note that in the case of a write operation in the normal operation mode, the output (Dout) of the data output buffer DOB is placed in a high impedance state by the timing signal φrw at that time.

The common complementary data lines CD, CD are connected to the output terminal of the data input sofa DrB.

In the case of a write operation, the data input cover sofa DrB is activated by the timing signal φr-, and the external terminal D
A complementary write signal according to the write signal supplied from in is transmitted to the common complementary data lines CD, CD. As a result, writing to the selected memory cell is performed. Note that in the case of a read operation, the output of the data driver sofa DrB is brought into a high impedance state by the timing signal φrw. In order to support high-speed readout tests,
Although not particularly limited, the amplifier circuit AMP is operated also during a write operation, and operates together with the data buffer sofa DIB to have a large current capacity capable of driving a plurality of complementary data lines. That is, multiple complementary data lines are selected to enable simultaneous writing of the same write signal to all memory cells coupled to one word line.

In a write operation to a dynamic memory cell consisting of an address selection MOSFET Qm and an information storage capacitor Cs, full writing is performed to the information storage capacitor Cs.
In order to prevent the high level written to the information storage capacitor Cs from decreasing due to the threshold voltage of FTQm, etc., a word line bootstrap circuit BST activated by the word line selection timing signal φX is provided. It will be done. This word line bootstrap circuit BST
receives the word line selection timing signal φX and sets the high level of the word line selection timing signal φX to the power supply voltage Vcc.
or higher level.

The various timing signals described above are generated by the following timing generation circuit TG. The timing generation circuit TO is
The main timing signals etc. shown as the representative above are formed. That is, this timing generation circuit TG receives address strobe signals RAS and CAS supplied from external terminals and a write enable signal WE, and forms the series of various timing pulses described above.

The circuit symbol REFC is an automatic refresh circuit and includes a refresh address counter and the like. This automatic refresh circuit REFC is connected to address slope signals RAS and CAS, although not particularly limited.
This logic circuit determines that when the column address strobe signal CAS is set to low level before the row address strobe signal RAS is set to low level, it is a refresh mode. The address counter circuit receives the row address strobe signal RAS as a counting clock and forms refresh address signals aQl to am'. The refresh address signals aO° to am' are transmitted to the row address decoder circuits R-DCRI and R-DCR2 via the row address buffer R-ADB. Therefore, in the refresh mode, the refresh control circuit REFC controls the address buffer R-AD.
A control signal φrf for switching B is generated.

This causes the refresh address signal aO.

A refresh operation is performed by selecting one word line corresponding to ~am' (CAS before-RAS refresh).

FIG. 2 shows a circuit diagram of an embodiment of the data input and output circuit in the dynamic RAM. Although some of the circuit symbols shown in this figure are the same as those given to the circuit elements in FIG. 1 above, it should be understood that they are different from each other.

Common complementary data lines CD, CD are coupled to the input terminal of main amplifier MA. Main amplifier MA is composed of a pair of first-stage differential amplifier circuit DFAI and second-stage differential amplifier circuit DFA2, although this is not particularly limited. One of the pair of first-stage differential amplifier circuits DFAI is an N-channel differential amplifier MOSFETQ? , Q8, and a P-channel load MOS F provided between its drain and power supply voltage Vcc.
ETQ5. N-channel power switch MOSFET Q13 provided between the common source of Q6 and the differential amplification MOSFET Q7゜Q8 and the ground potential point of the circuit.
It is composed of The above load MOSFET Q5. Q6
constitutes an active load circuit by being placed in a current mirror configuration. The other side of the first stage differential amplifier circuit DFAL is an N-channel differential amplifier MOSFETQ similar to the above.
II, Q12 and P-channel load MOSFET Q9. Q
The above differential amplification MOSFETQ11
, Q12's common source is one of the above differential amplification MOSFs.
ETQ7. It is shared with the common source of Q8, and its operation is controlled by the power switch MOSFET Q13.

The gate of N-channel MOSFET Q7 as an inverting input terminal in one differential amplifier circuit and the gate of N-channel MOSFET QI1 as a non-inverting input terminal in the other differential amplifier circuit are connected to a common complementary data line C.
It is connected to D.

Furthermore, the gate of N-channel MOSFET Q8 as a non-inverting input terminal in one differential amplifier circuit and the gate of N-channel MO3FBTQI 2 as an inverting input terminal in the other differential amplifier circuit are connected to the common complementary data line CD. combined.

A pair of output signals are formed by the pair of first-stage differential amplifier circuits DFAI. This pair of output signals is supplied to a pair of input terminals of a second-stage differential amplifier circuit DFA2 configured by a circuit similar to the first-stage differential amplifier circuit. Each circuit element in this second stage differential amplifier circuit DFA2 is as follows:
Since it is similar to that of the first stage amplifier circuit DFA1, the circuit symbol and its explanation will be omitted.

The main amplifier MA above has its power switch MOSF
Timing signal φI supplied to the gate of ETQ13 etc.
Activated by IIa.

Although not particularly restricted, the data output circuit DOB is provided with a latch circuit constituted by NAND gate circuits C1 and G2. A P-channel precharge MOSFET controlled by the timing signal φma is connected between the pair of input terminals and the power supply voltage Vcc.
Q14. Q15 is provided. Above MOSFETQ14
and G15 are turned on by the timing signal φma when the main amplifier MA is in the non-operating state, and set the input terminal to a high level (logic "1""). Therefore,
The latch circuit is placed in an information holding state. The output signals of the latch circuit are Nant gate circuit G3 and CMOS, respectively.
Inverter circuit IVI and Nant gate circuit G4 and CM
The signals are transmitted via the OS inverter circuit IV2 to the gates of push-pull type N-channel output MOSFETs Q16 and G17, respectively. The above Nant gate circuit G3.
The output timing signal φr- is supplied to the other input of G4. This signal φr- is at high level (logic “1”)
In response to this, the Nant gate circuit G3. G4 opens the gate and CMOS inverter circuit IVI.

IV2 and output MOSFET QI 6. The input signal is sent to the external terminal Dout via Ql7.

Note that if the timing signal φrW is at a low level such as the ground potential of the circuit, the outputs of the Nant gate circuits G3 and G4 will both be at a high level, and the inverter circuits IVI and I
Both outputs of V2 are set to low level. This turns both output MOSFETs QI 6 and G17 off, causing their outputs to go into a high impedance state. In addition,
The external output terminal Dout may be shared with an external input terminal Din to which an input terminal of a data input circuit DIB, which will be described later, is coupled.

External input terminal Din is connected to an input terminal of data input circuit DIB. This data input circuit DIB is activated by the timing signal φr-, and the external input terminal Din
A write signal that is in phase with the write data signal supplied to the write data signal and a write signal that is in opposite phase are formed. The complementary write data signals are supplied to the common complementary data lines CD and CD via N-channel transmission gate MOSFETs QI and G2 forming a multiplexer.

Transmission gate MOSFET that constitutes the above multiplexer
Q1. Q2 is turned on in write mode by a write control signal W supplied to its gate. In the write operation mode, the data input circuit D
A write signal generated by IB is transmitted to the complementary data line through the common complementary data lines CD and the column switch circuit selected at this time, and a write operation is performed on the memory cell whose word line is in the selected state. It will be done.

The common complementary data lines CD, CD are provided with an amplifier circuit AMP consisting of a latch circuit.

Like the sense amplifier SA, the amplifier circuit AMP has P
Channel MOSFET Q20. G22 and N-channel MO5FETQ21. The input and output nodes of the CMOS inverter circuit G23 are cross-connected to form a latch circuit, and the input/output node of the pair is connected to the common complementary data line CD.

Combined with CD. The latch circuit also includes a P-channel MOS to control its operation timing.
Power supply voltage Vcc is supplied through FETQ24, and circuit ground voltage V is supplied through N-channel MOSFETQ25.
ss is supplied. These buses”)−4+MOS
FETQ24. A low level signal is applied to the gate of G25 to activate the amplifier circuit AMP during the operation cycle.
Complementary timing pulses φpal, φ set to high level
pa' is applied. This complementary timing pulse φp
For example, a'φpa° is a signal whose change start timing is delayed with respect to timing pulses φpa2 and φpa2 of the sense amplifier. By setting an appropriate delay time, the complementary timing pulse φpa''
, φpa' are set to a level that activates the amplifier circuit AMP after a read signal from the selected data line is transmitted to the common complementary data lines CD, CD by the selection operation of the column switch circuit.

In this embodiment, the data read speed can be made sufficiently high for the reasons explained below.

First, the read signal supplied to the input of the main amplifier MA is also DC-amplified by the latch-type amplifier circuit AMP. Therefore, the level of the input signal increases with the amplification operation of the amplifier circuit AMP, equivalently speeding up the amplification operation of the main amplifier MA. This makes it possible to speed up the read operation.

Furthermore, since latch-type amplifier circuits are provided for the common complementary data lines CD and CD as described above, the column selection timing can be made faster. That is,
In a conventional dynamic RAM, it was necessary to perform a column selection operation after the level difference between the complementary data lines was made sufficiently large by the amplification operation of the sense amplifier SA, but in this embodiment, the common complementary data lines CD, CD Since an amplifier circuit AMP similar to the sense amplifier is provided on the side as well, the column selection operation can be performed immediately after the level necessary for the amplification operation is established.Furthermore, the complementary data line and Since the signals on the common complementary data line are each amplified by a latch-type amplifier circuit, the data line and the complementary data line expand to high level and low level at high speed.As a result, the main amplifier MA Coupled with the shortening of the amplification time,
It becomes possible to speed up the read operation.

Furthermore, noise is a factor that limits the speed of data readout; if the noise is large, readout cannot be performed until the signal level becomes sufficiently large compared to the noise; however, in the case of this example, the noise is small. This enables high-speed reading. That is, when using the CMOS latch circuit as described above as the sense amplifier SA and the amplifier circuit AMP, the levels of the complementary data line and the common complementary data line change rapidly between high level and low level, so the N-channel MOSFET and P The time period during which a relatively large through current flows through the channel MOS FET can be shortened. As a result, the noise level generated in the power supply line and the ground line is reduced, and power consumption can be reduced.

Furthermore, in the configuration in which the latch-type amplifier circuit AMP is provided on the common complementary data lines CD, CD, the amplifier circuit AMP is kept in the operating state even during a write operation, and the data input cover sofa D
It is possible to provide a function to assist the write driving ability of the IB. This makes it possible to provide a function to write the same data all at once to a plurality of data lines in preparation for a test mode without increasing the size of the elements constituting the data driver sofa DIB.

The effects obtained from the above examples are as follows. That is, (1) By providing a latch-type amplifier circuit activated by a predetermined timing signal for a common complementary data line connected to a complementary data line to which memory cells are coupled via a column switch circuit. Since the read signal transmitted to the common complementary data line is also amplified in direct current terms by the amplifying circuit, an effect can be obtained that the amplifying operation of the main amplifier can equivalently be speeded up.

(2) Corresponding to the fact that a latch-type amplifier circuit is provided for the common complementary data lines CD and CD as described above, the column selection timing can be made faster, and the data lines and complementary data lines can go high at high speed. In combination with the amplification time in the main amplifier MA being shortened by expanding the signal to the low level and the low level, the effect of increasing the speed of the read operation can be obtained.

(3) Since the levels of the complementary data line and the common complementary data line change rapidly between high and low levels, the N-channel MOS F that constitutes the sense amplifier and amplifier circuit
The time period during which a relatively large through current flows through the ET and the P-channel MOSFET can be shortened. As a result, it is possible to reduce noise generated in the power supply line and the ground line and to reduce power consumption.

(4) In the configuration in which the latch-type amplifier circuit AMP is provided on the common complementary data lines CD, CD, the amplifier circuit AMP is kept in the operating state even during a write operation, and the data input cover sofa D
Since it is possible to provide a function to assist the writing drive capacity of the IB, it is possible to write the same data all at once to multiple data lines in preparation for test mode without increasing the size of the elements that make up the data input cover sofa DIB. The effect is that a writing function can be added.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, the sense amplifier may be a unit circuit of MOSFETs whose gates and drains are cross-coupled, in addition to the CMO3 circuit. In this case, the complementary data line is provided with an active restore circuit. The read reference voltage of the memory cell is
In addition to using the half precharge voltage as described above, the reference voltage may be formed using a dummy cell. The address signal may be supplied from independent terminals for the row system and the column system. As described above, the specific configuration of each circuit configuring the dynamic RAM can take various embodiments.

The present invention can be widely used in semiconductor memory devices that employ a read method such as the dynamic RAM described above.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by providing a latch-type amplifier circuit activated by a predetermined timing signal for a common complementary data line connected to a complementary data line to which memory cells are coupled via a column switch circuit, a common complementary Since the read signal transmitted to the data line is also amplified in direct current terms by the amplification circuit, the amplification operation of the main amplifier can equivalently be speeded up.

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
Circuit Diagram Showing One Embodiment FIG. 2 is a circuit diagram showing one embodiment of the main amplifier, data output circuit, and data input circuit. MARY...Memory array, PC...Precharge circuit, USA...Unit circuit, SA...Sense amplifier, AMP
・・Amplification circuit, MA・・Main amplifier, C-5W・・Column switch, R, C-ADB・・Address buffer,
R-DCR...Row address decoder, C-DCR...
Column address decoder, TG...timing generation circuit, REFC...automatic refresh circuit, DOB...data output huffer, DIB...data person cover sofa, VB
G...Substrate bias generation circuit Figure 2

Claims (1)

[Claims] 1) A common complementary data line connected to the complementary data line to which memory cells are coupled via a column switch circuit, and a main amplifier that amplifies the signal of this common complementary data line and transmits it to the output circuit. and an amplifier circuit including a latch-type amplification MOSFET whose input/output nodes are coupled to the common complementary data line and which is activated by a predetermined timing signal. 2) The complementary data line is provided with a sense amplifier including an input/output node of a plurality of dynamic memory cells and a latch-type amplification MOSFET that amplifies the stored information. The semiconductor memory device according to item 1. 3) The above amplifier circuit and sense amplifier are latch type CMs.
3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device includes an OS inverter circuit.