JPS63151018A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63151018A JPS63151018A JP29943686A JP29943686A JPS63151018A JP S63151018 A JPS63151018 A JP S63151018A JP 29943686 A JP29943686 A JP 29943686A JP 29943686 A JP29943686 A JP 29943686A JP S63151018 A JPS63151018 A JP S63151018A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- atoms
- polycrystalline
- conductivity type
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010409 thin film Substances 0.000 claims abstract description 43
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 29
- 238000009826 distribution Methods 0.000 abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 16
- 238000010438 heat treatment Methods 0.000 abstract description 12
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 3
- -1 Silicon ions Chemical class 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 3
- 239000002245 particle Substances 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法に関するもので、特に集
積回路等の熱拡散工程における不純物拡散源の不純物含
有の均一性を改良した製造方法に係るものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device that improves the uniformity of impurity content in an impurity diffusion source in a thermal diffusion process for integrated circuits, etc. It is.
従来の技術
半導体装置において高性能な素子を得るためには、浅い
不純物拡散による接合の形成を必要とする。たとえば、
半導体基板上に多結晶半導体薄膜を堆積し、この薄膜中
に不純物をイオン注入後、熱処理して不純物を半導体基
板内に拡散し、所望の浅い不純物拡散領域を形成するこ
とが一般的手法になってきている。In order to obtain a high-performance element in a conventional semiconductor device, it is necessary to form a junction by shallow impurity diffusion. for example,
A common method is to deposit a polycrystalline semiconductor thin film on a semiconductor substrate, implant ions of impurities into this thin film, and then perform heat treatment to diffuse the impurities into the semiconductor substrate to form a desired shallow impurity diffusion region. It's coming.
発明が解決しようとする問題点
一般的に、多結晶半導体薄膜を堆積する時、反応部の温
度分布の不均一性や、半導体基板面での赤外線反射等の
原因により、堆積した多結晶半導体薄膜の結晶粒の大き
さが半導体基板面内で不均一となりやすい。このような
多結晶半導体薄膜に注入された不純物原子の一部は、注
入後の熱処理によって結晶粒と結晶粒との境界、すなわ
ち結晶粒界に取り込まれ不活性化する。結晶粒の小さい
部分では結晶粒界が大きく、多くの不純物原子が不活性
化し、結晶粒の大きい部分では結晶粒界が小さく、多（
の不純物原子が結晶粒内で活性化する。従って、多結晶
半導体薄膜の結晶粒の大きさが不均一であると、この膜
から半導体基板内に拡散される不純物の濃度分布に不均
一を生じる。すなわち、均質性の悪い接合が形成される
。このことが製造上のの歩留と製品の品質を低下させて
いた。例えば、導電型を決める原子のイオン注入の前に
多結晶半導体薄膜を熱処理して結晶粒の大きさを均一化
するブリアニール法が、１９８４年、ジャーナルオブエ
レクトロケミカルソサエティー（Ｊｏｕｒｎａｌ ｏｆ
Ｅｌｅｃｔｒｏｃｈｅｍｉｃａｌ ５ｏｃｉｅｔｙ）
、第１３１巻、１号、２１６〜２１７頁に記載されてい
るが、充分な均一性を得るためには１０００℃以上の高
温での熱処理が必要であり、実際の半導体素子の製造工
程に応用することは必ずしも好ましくない。また、熱処
理した多結晶半導体薄膜において、表面に近い部分はど
結晶粒の大きさは大きくなり、均一化することが、１９
８４年、ジャーナルオブバキュームサイエンステクノロ
ジー（Ｊｏｕｒｎａｌ ｏｆ ＶａｃｕｕＩ！１Ｓｃｉ
ｅｎｃｅ Ｔｅｃｈｎｏｌｏｇｙ）、Ｂ、第２巻、第４
号、６９８〜７０６頁に記載されている。もし、このよ
うな結晶状態を想定するならば、イオン注入によって多
結晶半導体薄膜表面を非晶質化すると、その後の熱処理
で多結晶半導体薄膜表面下層部の小さな結晶粒が種とな
って表面が再結晶化するために、結晶粒の大きさは不均
一となり、従って高均一性の拡散源を形成しに（いと考
えられる。Problems to be Solved by the Invention Generally, when depositing a polycrystalline semiconductor thin film, the deposited polycrystalline semiconductor thin film may be damaged due to non-uniform temperature distribution in the reaction area, infrared reflection on the semiconductor substrate surface, etc. The size of crystal grains tends to be non-uniform within the plane of the semiconductor substrate. Some of the impurity atoms implanted into such a polycrystalline semiconductor thin film are incorporated into the boundaries between crystal grains, that is, grain boundaries, and are inactivated by heat treatment after implantation. In the small part of the crystal grain, the grain boundary is large and many impurity atoms are inactivated, and in the large part of the crystal grain, the grain boundary is small and many impurity atoms are inactivated.
impurity atoms become activated within the crystal grains. Therefore, if the crystal grain size of the polycrystalline semiconductor thin film is non-uniform, the concentration distribution of impurities diffused from the film into the semiconductor substrate will be non-uniform. That is, a bond with poor homogeneity is formed. This reduced manufacturing yield and product quality. For example, in 1984, the Brian Annealing method, in which polycrystalline semiconductor thin films are heat-treated to uniformize the size of crystal grains before ion implantation of atoms that determine the conductivity type, was published in the Journal of Electrochemical Society.
Electrochemical 5ociety)
, Vol. 131, No. 1, pp. 216-217, heat treatment at a high temperature of 1000°C or higher is necessary to obtain sufficient uniformity, making it difficult to apply it to actual semiconductor device manufacturing processes. It is not necessarily desirable to do so. In addition, in a heat-treated polycrystalline semiconductor thin film, the size of crystal grains becomes larger and more uniform near the surface.
1984, Journal of Vacuum Science Technology
ence Technology), B, Volume 2, No. 4
No., pp. 698-706. If such a crystalline state is assumed, if the surface of the polycrystalline semiconductor thin film is made amorphous by ion implantation, the small crystal grains in the lower layer of the surface of the polycrystalline semiconductor thin film will become seeds in the subsequent heat treatment, and the surface will become amorphous. Due to recrystallization, the grain size becomes non-uniform, thus forming a highly uniform diffusion source.
本発明はこのような問題点を解決するもので、多結晶半
導体の結晶粒の大きさの不均一を緩和することで多結晶
半導体内の不純物濃度分布の均一性を高め熱拡散工程に
おける不純物拡散領域の不純物濃度分布の均一性の改良
と品質の改善をめざした半導体装置の製造方法を提供す
るものである。The present invention solves these problems by alleviating the non-uniformity of the crystal grain size of polycrystalline semiconductors, improving the uniformity of the impurity concentration distribution within the polycrystalline semiconductor, and improving impurity diffusion during the thermal diffusion process. The present invention provides a method for manufacturing a semiconductor device that aims to improve the uniformity of impurity concentration distribution in a region and improve quality.
問題点を解決するための手段
この問題点を解決するために本発明は、半導体基板主面
上に多結晶半導体薄膜を堆積する工程と、前記多結晶半
導体薄膜中に、表面を非晶質化せずに導電型を決めない
原子をイオン注入する工程と、前記導電型を決めない原
子を含む半導体薄膜を熱処理する工程と、前記熱処理さ
れた半導体薄膜中に、導電型を決める原子をイオン注入
する工程と、前記導電型を決める原子を含む半導体薄膜
を熱処理する工程とを備えた半導体装置の製造方法を提
供する。Means for Solving the Problem In order to solve this problem, the present invention includes a step of depositing a polycrystalline semiconductor thin film on the main surface of a semiconductor substrate, and a step of making the surface of the polycrystalline semiconductor thin film amorphous. a step of ion-implanting atoms that do not determine the conductivity type, a step of heat-treating the semiconductor thin film containing the atoms that do not determine the conductivity type, and ion-implanting atoms that determine the conductivity type into the heat-treated semiconductor thin film. and a step of heat treating a semiconductor thin film containing atoms that determine the conductivity type.
作用
本発明の方法により、多結晶半導体の結晶粒の大きさの
不均一性を緩和するために、多結晶半導体薄膜堆積後、
表面を非晶質化せずに導電型を決めない原子をイオン注
入して下層部を非晶質化してから熱処理を行った後、導
電型を決める原子をイオン注入し、再度熱処理すること
によって多結晶半導体薄膜全体の結晶粒を表面の大きな
結晶粒に統一化することで、多結晶半導体内の不純物濃
度分布の均一性を高め熱拡散工程における不純物拡散領
域の不純物濃度分布の良好な均一性を実現した、高歩留
高品質の半導体装置の提供が可能となった。さらには、
表面を非晶質化せずに導電型を決める原子をイオン注入
することにより、より高い均一性を得ることが可能とな
った。Operation According to the method of the present invention, in order to alleviate the non-uniformity of the crystal grain size of a polycrystalline semiconductor, after depositing a polycrystalline semiconductor thin film,
By ion-implanting atoms that do not determine the conductivity type without making the surface amorphous, making the lower layer amorphous, and then performing heat treatment, then ion-implanting atoms that determine the conductivity type, and heat-treating again. By unifying the crystal grains of the entire polycrystalline semiconductor thin film into large crystal grains on the surface, the uniformity of the impurity concentration distribution within the polycrystalline semiconductor is improved, resulting in good uniformity of the impurity concentration distribution in the impurity diffusion region during the thermal diffusion process. It has become possible to provide high-yield, high-quality semiconductor devices that have achieved this. Furthermore,
By ion-implanting atoms that determine the conductivity type without making the surface amorphous, it has become possible to obtain higher uniformity.
実施例
以下、本発明の製造方法を多結晶シリコンによる実施例
を参照して詳細に説明する。EXAMPLE Hereinafter, the manufacturing method of the present invention will be explained in detail with reference to an example using polycrystalline silicon.
半導体基板上に反応温度６１０℃の減圧ＣＶＤ法により
約３０００ Ａの多結晶シリコン薄膜を堆積し、この多
結晶シリコン薄膜に加速電圧７０ｋＶで１×１０’５ｃ
ｍ−２のシリコンをイオン注入した。次いでシリコンを
イオン注入した多結晶シリコン薄膜を窒素雰囲気中で８
００℃〜１０００℃の温度で３０分間熱処理（ブリアニ
ール）した。次いでこの多結晶シリコン薄膜に加速電圧
４０ｋＶでｌ Ｘ １０ ” ｃｍ−２のポロン、ある
いは加速電圧 １６０ｋＶでＩＸＩＯＩ６ｃｍ−”のヒ
素を注入した。以上の一連の工程によって、所望する不
純物拡散源が形成された。しかる後窒素雰囲気中９５０
℃の温度で３０分間熱処理した。以上の一連の工程によ
って、所望する不純物拡散領域が形成された。A polycrystalline silicon thin film of approximately 3000 A was deposited on a semiconductor substrate by low pressure CVD at a reaction temperature of 610°C, and a 1×10'5 cm film was deposited on this polycrystalline silicon thin film at an accelerating voltage of 70 kV.
m-2 silicon ions were implanted. Next, the polycrystalline silicon thin film into which silicon was ion-implanted was heated for 8 hours in a nitrogen atmosphere.
Heat treatment (briannealing) was performed at a temperature of 00°C to 1000°C for 30 minutes. Then, l x 10" cm-2 of poron was implanted at an accelerating voltage of 40 kV, or IXIOI 6 cm-2 of arsenic was implanted at an accelerating voltage of 160 kV into this polycrystalline silicon thin film. Through the above series of steps, a desired impurity diffusion source was formed. After that, 950℃ in nitrogen atmosphere.
Heat treatment was performed for 30 minutes at a temperature of .degree. Through the above series of steps, a desired impurity diffusion region was formed.
一方従来例を示す試料として、半導体基板上に反応温度
６１０℃の減圧ＣＶＤ法により約３０００ Ａの多結晶
シリコン薄膜を堆積した後ただちに、この多結晶シリコ
ン薄膜に加速電圧２５ｋＶで１×ＩＯ” ｃｍ−”のボ
ロン、あるいは加速電圧６０ｋＶでｌ Ｘ １０ ”
ｃｍ−２のヒ素を注入し、しかる後窒素雰囲気中で９５
０℃の温度で３０分間熱処理した。On the other hand, as a sample showing a conventional example, a polycrystalline silicon thin film of about 3000 A was deposited on a semiconductor substrate by low pressure CVD method at a reaction temperature of 610°C, and immediately after that, a 1×IO" cm was applied to this polycrystalline silicon thin film at an accelerating voltage of 25 kV. -" boron, or l x 10" at an accelerating voltage of 60 kV
cm-2 of arsenic was implanted, and then 95 cm-2 of arsenic was implanted in a nitrogen atmosphere.
Heat treatment was performed at a temperature of 0° C. for 30 minutes.
前記試料の不純物濃度分布の均一性を、多結晶シリコン
薄膜上の４５点のシート抵抗を測定しその分布の偏差に
よって評価した。第１図に、ボロン注入した試料におけ
る、従来例と本発明の実施例との多結晶シリコン薄膜内
での抵抗値分布の偏差を示す。また第２図にヒ素注入し
た試料における、従来例と本発明の実施例との多結晶シ
リコン薄膜内での抵抗値分布の偏差を示す。何れの場合
においても抵抗値の基板面内での偏差の減少は明らかで
ある。特に１０００℃のプリアニールを行ったものは、
偏差が・約２分の１から３分の１となっている。The uniformity of the impurity concentration distribution of the sample was evaluated by measuring the sheet resistance at 45 points on the polycrystalline silicon thin film and determining the deviation of the distribution. FIG. 1 shows the deviation in resistance value distribution within a polycrystalline silicon thin film between a conventional example and an example of the present invention in a boron-implanted sample. Furthermore, FIG. 2 shows the deviation of the resistance value distribution within the polycrystalline silicon thin film between the conventional example and the example of the present invention in the arsenic-implanted sample. In either case, it is clear that the deviation of the resistance value within the substrate plane is reduced. Especially those that have been pre-annealed at 1000℃,
The deviation is approximately 1/2 to 1/3.
発明の効果
本発明による製造方法によって、多結晶半導体薄膜の粒
径の不均一性が緩和され、イオン注入した多結晶半導体
薄膜による熱拡散工程における不純物拡散領域の不純物
濃度分布の均一性が改良でき、高歩留高信頼の半導体装
置の提供が可能となる。Effects of the Invention The manufacturing method according to the present invention can alleviate the non-uniformity of the grain size of the polycrystalline semiconductor thin film and improve the uniformity of the impurity concentration distribution in the impurity diffusion region in the thermal diffusion process using the ion-implanted polycrystalline semiconductor thin film. , it becomes possible to provide semiconductor devices with high yield and high reliability.
第１図は、ボロン注入した試料における、従来例と本発
明の実施例との多結晶シリコン薄膜内での抵抗値分布の
偏差を示す曲線図、第２図は、ヒ素注入した試料におけ
る、従来例と本発明の実施例との多結晶シリコン薄膜内
での抵抗値分布の偏差を示す曲線図である。
第１図
プリ７二一ル濁度 （’ｃ）
［熱処理時間Ｘ分］
第２図
ｚｏｏ ｑｏｏ ｔｏｏ。
プリ７二−ル湿／Ｘ （’Ｃ）
〔熱処理時間Ｊ分１FIG. 1 is a curve diagram showing the deviation in resistance value distribution within a polycrystalline silicon thin film between a conventional example and an example of the present invention in a sample implanted with boron, and FIG. FIG. 3 is a curve diagram showing the deviation of resistance value distribution within a polycrystalline silicon thin film between an example and an example of the present invention. Figure 1 Pre-721 turbidity ('c) [Heat treatment time X minutes] Figure 2 zoo qoo too. Puri 7 Neal Moisture/X ('C) [Heat treatment time J minutes 1
Claims (4)
工程と、前記多結晶半導体薄膜中に、表面を非晶質化せ
ずに導電型を決めない原子をイオン注入する工程と、前
記導電型を決めない原子を含む半導体薄膜を熱処理する
工程と、前記熱処理された半導体薄膜中に、導電型を決
める原子をイオン注入する工程と、前記導電型を決める
原子を含む半導体薄膜を熱処理する工程を有し、前記半
導体薄膜を拡散源として使用することを特徴とする半導
体装置の製造方法。(1) a step of depositing a polycrystalline semiconductor thin film on the main surface of a semiconductor substrate; a step of ion-implanting atoms that do not determine the conductivity type without making the surface amorphous into the polycrystalline semiconductor thin film; a step of heat treating a semiconductor thin film containing atoms that do not determine the conductivity type; a step of ion-implanting atoms that determine the conductivity type into the heat-treated semiconductor thin film; and heat treating the semiconductor thin film containing atoms that determine the conductivity type. 1. A method of manufacturing a semiconductor device, comprising a step of using the semiconductor thin film as a diffusion source.
を非晶質化せずにイオン注入することを特徴とする特許
請求の範囲第１項記載の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation of atoms that determine the conductivity type is performed without making the surface amorphous.
原子を同一の原子とする特許請求の範囲第１項あるいは
第２項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the atoms constituting the polycrystalline semiconductor and the atoms that do not determine the conductivity type are the same atoms.
求の範囲第１項あるいは第２項記載の半導体装置の製造
方法。(4) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein atoms that do not determine the conductivity type are used as inert elements.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61299436A JPH07120636B2 (en) | 1986-12-16 | 1986-12-16 | Method for manufacturing semiconductor device |
| US07/374,608 US4954454A (en) | 1986-12-16 | 1989-06-30 | Method for fabricating a polycrystalline silicon resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61299436A JPH07120636B2 (en) | 1986-12-16 | 1986-12-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63151018A true JPS63151018A (en) | 1988-06-23 |
| JPH07120636B2 JPH07120636B2 (en) | 1995-12-20 |
Family
ID=17872550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61299436A Expired - Lifetime JPH07120636B2 (en) | 1986-12-16 | 1986-12-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120636B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003009534A (en) * | 2001-06-25 | 2003-01-10 | Diamond Electric Mfg Co Ltd | Power factor improving circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4959518B2 (en) * | 2007-11-16 | 2012-06-27 | 株式会社Ｎｙｋシステムズ | 3D CG object interference check program |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63124520A (en) * | 1986-11-14 | 1988-05-28 | Nec Corp | Manufacture of semiconductor device |
-
1986
- 1986-12-16 JP JP61299436A patent/JPH07120636B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63124520A (en) * | 1986-11-14 | 1988-05-28 | Nec Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003009534A (en) * | 2001-06-25 | 2003-01-10 | Diamond Electric Mfg Co Ltd | Power factor improving circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07120636B2 (en) | 1995-12-20 |
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