JPS63148629A - Method of forming position detection mark - Google Patents

Method of forming position detection mark

Info

Publication number
JPS63148629A
JPS63148629A JP61294662A JP29466286A JPS63148629A JP S63148629 A JPS63148629 A JP S63148629A JP 61294662 A JP61294662 A JP 61294662A JP 29466286 A JP29466286 A JP 29466286A JP S63148629 A JPS63148629 A JP S63148629A
Authority
JP
Japan
Prior art keywords
insulating film
mark
semiconductor substrate
ohmic
apertures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61294662A
Other languages
Japanese (ja)
Inventor
Masaya Murayama
村山 雅也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61294662A priority Critical patent/JPS63148629A/en
Publication of JPS63148629A publication Critical patent/JPS63148629A/en
Pending legal-status Critical Current

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  • Electron Beam Exposure (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE:To improve the accuracy of position detection by a method wherein apertures are drilled in an insulating film covering the surface of a semiconductor substrate so as to correspond to a pattern for a semiconductor element and a metal layer which is different from ohmic metal layers is applied so as to cover one of the apertures to form a mark. CONSTITUTION:Apertures 5 which are drilled in an insulating film 3 covering the surface of a semiconductor substrate 1 are covered with ohmic metal layers 6 and the metal layers 6 are contacted with the semiconductor substrate 1 in the apertures 5. A mark pattern composed of one of the apertures 5 formed in the insulating film 3 is not deformed even if it is subjected to a heat treatment at about 450 deg.C which is necessary to ensure the ohmic contacts between the ohmic metals 6 and the semiconductor substrate 1. Further, the mark-shape aperture 5 in the insulating film and the surroundings of the aperture 5 are covered with a metal layer 10 which is different from the ohmic metal layer 6. By the contact between the metal layer 10 and the semiconductor substrate 1, charging of the insulating film 3 can be avoided and the lowering of alignment accuracy can be avoided.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は位置検出マークの形成方法に関し、特に電子線
などの荷電粒子線を適用して描画する際に利用する位置
検出マークに好適するものである。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for forming a position detection mark, and in particular to a method for forming a position detection mark, particularly for position detection used when drawing using a charged particle beam such as an electron beam. It is suitable for marks.

(従来の技術) 最近の半導体素子は超LSIなどの集積回路ならびに高
周波半導体素子のような個別半導体装置にあっても高集
積化及び高機能化が促進されており。
(Prior Art) Recent semiconductor devices have become highly integrated and highly functional, even in integrated circuits such as VLSIs and individual semiconductor devices such as high-frequency semiconductor devices.

従って素子の寸法を微細化する試みが数多く行われてい
る。その−環として電子線を利用する直接描画法はフォ
トマスクと紫外線露光を使用するフォトリソグラフィに
比べて微細パターン形成に有利であり、更に位置合せ精
度も高いこともあって既に広く採用されているのが現状
である。
Therefore, many attempts have been made to miniaturize the dimensions of the elements. The direct writing method, which uses an electron beam as a link, is more advantageous in forming fine patterns than photolithography, which uses a photomask and ultraviolet light exposure, and has already been widely adopted due to its high alignment accuracy. is the current situation.

ところで、半導体基板表面を被覆する電子線感応レジス
トに電子線描画によってパターンを形成するにはこの半
導体基板に作成ずみのパターンに対して描画パターンを
位置合せすることが必要であり、このため半導体基板に
位置検出マーク(以後マークと省略する)を設けておき
、描画直前にこのマークを電子線で走査してその位置を
検出するのが一般的手法である。
By the way, in order to form a pattern by electron beam writing on the electron beam sensitive resist covering the surface of a semiconductor substrate, it is necessary to align the drawn pattern with the pattern already created on the semiconductor substrate. A common method is to provide a position detection mark (hereinafter abbreviated as "mark") on the image, and scan this mark with an electron beam to detect the position immediately before drawing.

このマークは多くの形状が知られており、断面形状とし
て凸形もしくは凹形をもち、上面形状としてL字形もし
くは十字形が多く使用され、その材質としては電子線照
射により帯電し難いために確実なマーク検出信号が得ら
れるように金属を使用することが多い。
This mark is known to have many shapes, with a convex or concave cross-sectional shape, an L-shape or a cross shape as the top surface, and the material is difficult to charge due to electron beam irradiation, so it is reliable. Metals are often used to obtain accurate mark detection signals.

その形成時期はこの電子線描画工程前であり、しかも基
準となる電極と同時に、しかも同じ材料を使用し、更に
形成したマーク表面やその周囲は成る可く平坦にして位
置検出精度を向上するように配慮する。
The mark is formed before this electron beam lithography process, and is made of the same material as the reference electrode, and the surface of the mark and its surroundings are made as flat as possible to improve position detection accuracy. be considerate.

こNで第2図イル口によってマーク形成プロセスを簡単
に説明すると、半絶縁性半導体基板20表面を被覆する
フォトレジスト層21に素子用電極ならびにマーク形成
予定位置に開孔22.22をもつパターンを形成する0
次にこのパターンにこの電極用金属を被着後フォトレジ
スト層21を溶除すると共に余分の電極用金属を除去す
るりフトオフ法により、開孔内に前記金属層を充愼して
電極23ならびにマーク24を設置する。
Now, to briefly explain the mark formation process using FIG. 0 forming
Next, after depositing the electrode metal on this pattern, the photoresist layer 21 is dissolved and the excess electrode metal is removed, and the openings are filled with the metal layer and the electrodes 23 and Mark 24 is installed.

(発明が解決しようとする問題点) ソース電極とドレイン電極に対するゲート電極の位置関
係が特性に大きく寄与する磁化ガリウム電界効果トラン
ジスタ(以後GaAsFETと省略する)に前述のマー
ク形成方法を適用すると下記の問題点が生じる。
(Problems to be Solved by the Invention) When the above-mentioned mark formation method is applied to a magnetized gallium field effect transistor (hereinafter abbreviated as GaAsFET) in which the positional relationship of the gate electrode with respect to the source and drain electrodes greatly contributes to the characteristics, the following will occur. A problem arises.

GaAsFETにあってはGaAs半導体基板表面から
内部に向けてSiを導入して動作層を設け、二Nに基準
となるソースならびにドレイン電極をマークと同時に形
成し、ゲートパターンを電子線により描画する際にはこ
のマーク位置を検出して位置合せを実施する。
For GaAsFETs, Si is introduced from the surface of the GaAs semiconductor substrate toward the inside to provide an active layer, and source and drain electrodes that serve as a reference are formed on 2N at the same time as marks, and the gate pattern is drawn using an electron beam. Then, the position of this mark is detected and alignment is performed.

このソース電極、ドレイン電極及びマークは前述のよう
に同一材料であるAuGe/Niにより形成し。
The source electrode, drain electrode, and mark are formed of the same material, AuGe/Ni, as described above.

更にソースならびにドレイン電極のオーム性接触を確保
するため水素雰囲気450℃で熱処理をゲートパターン
形成前に実施する。しかし、この熱処理によりマーク2
4が第2図ハ、二に示すように上面ならびに断面が変形
することが判明し、この結果位置検出精度が著るしく低
下する難点がある。
Further, in order to ensure ohmic contact between the source and drain electrodes, heat treatment is performed at 450° C. in a hydrogen atmosphere before forming the gate pattern. However, due to this heat treatment, Mark 2
It has been found that the upper surface and the cross section of the sensor 4 are deformed as shown in FIGS.

又、マークの変形を防ぐためにマークを絶縁膜により形
成する方法もあるが、ゲートパターンを電子線により描
画する際、絶縁膜が帯電して位置検出精度が低下する難
点もある。
There is also a method of forming the mark with an insulating film in order to prevent the mark from deforming, but there is a problem in that when drawing the gate pattern with an electron beam, the insulating film is charged and the position detection accuracy is reduced.

本発明はこの難点を除去する新規な位置検出マークの形
成方法を提供することを目的とする。
It is an object of the present invention to provide a novel method for forming position detection marks that eliminates this difficulty.

〔発明の構成〕[Structure of the invention]

(問題点を解決するための手段) この目的を達成するために、本発明では半導体基板表面
を被覆する絶縁膜を半導体素子用パターンに合せて開孔
し、開孔部を覆うようにオーミック金属と異なる金属層
を被着してマークを形成する手段を採用する。
(Means for solving the problem) In order to achieve this object, in the present invention, holes are formed in the insulating film covering the surface of the semiconductor substrate in accordance with the semiconductor element pattern, and ohmic metal is used to cover the holes. The mark is formed by depositing a metal layer different from the mark.

(作 用) 絶縁膜の開孔によるマークパターンは、オーミック金属
と半導体基板のオーム性接触を確保するのに必要な約4
50℃の熱処理を経ても、何等変形が発生しない知見を
基に、本発明は完成されたものであり、さらにマークパ
ターン形状の絶縁膜開孔部及び開孔部周辺はオーミック
金属とは異なる金属層で覆われているためにこの金属層
と半導体基板の接続によって絶縁膜への帯電が防止可能
となって位置合せ精度の低下を阻止するものである。
(Function) The mark pattern formed by the openings in the insulating film is approximately
The present invention was completed based on the knowledge that no deformation occurs even after heat treatment at 50°C, and furthermore, the mark pattern-shaped insulating film opening and the vicinity of the opening are made of a metal different from the ohmic metal. Since it is covered with a layer, the connection between the metal layer and the semiconductor substrate makes it possible to prevent the insulating film from being charged, thereby preventing a decrease in alignment accuracy.

(実施例) 本発明に係る実施例を第1図イ〜ホにより詳述する。(Example) Embodiments according to the present invention will be described in detail with reference to FIGS.

この実施例は本発明方法をGaAsFETへの適用例を
示すもので、 GaAs半導体基板1の表面からSiな
どを内部に導入してn形動作層2を設けてから、厚さ5
ooo人の酸化珪素膜3を被覆後、フォトレジスト層4
を重ねて被着して第1図イに示す断面構造とする。次に
公知のフォトリソグラフィによってFETのソース電極
、ドレイン電極ならびにマークの形成予定位置に開孔を
同時に形成し、引続きこの開孔に露出する酸化珪素膜3
をこの開孔を通じてエツチングして開孔5・・・を設け
て動作層2ならびにGaAs半導体基板を露出する。(
第1図口)こ−でFETに必要なオーミック金属6とし
てAuGeを2000人更にNiを500人 この順に
被着してから、アセトンでこのフォトレジスト層を溶解
して開孔部・・以外のフォトレジスト層に被着するオー
ミック金属層を除去して第1図ハとして、 FETに必
要なソース電極7ならびにドレイン電極8を設けると共
にマークとなる開孔5にもこのオーミック金属層6が充
填される。
This example shows an example in which the method of the present invention is applied to a GaAs FET. After introducing Si or the like into the inside of a GaAs semiconductor substrate 1 from the surface thereof to form an n-type active layer 2,
ooo After coating the silicon oxide film 3, photoresist layer 4
The cross-sectional structure shown in FIG. Next, holes are simultaneously formed at the positions where the source electrode, drain electrode, and mark of the FET are to be formed by known photolithography, and the silicon oxide film 3 is subsequently exposed to the holes.
is etched through the openings to form openings 5 . . . to expose the active layer 2 and the GaAs semiconductor substrate. (
(Figure 1) After depositing 2,000 layers of AuGe and 500 layers of Ni as the ohmic metal 6 necessary for the FET in this order, dissolve this photoresist layer with acetone and remove the areas other than the openings. The ohmic metal layer adhering to the photoresist layer is removed, and the source electrode 7 and drain electrode 8 necessary for the FET are provided as shown in FIG. Ru.

次に再びフォトレジスト層9を全面に塗布した後前述の
ようにフォトリソグラフィ工程によりフォトレジスト9
のマーク形成予定位置を開孔し、露出したオーミック金
属6を溶除することによって新に開孔11として第1図
二に示す断面構造とする。引続き厚さ1000人程度O
7i1Oを蒸着法によって被着後、フォトレジスト層9
を溶除することによって二\に堆積するTi層を共に除
去して第1図ホに示すように酸化珪素膜の開孔部がTi
層で覆われている凹形の断面構造を持つマークが完成す
る。
Next, the photoresist layer 9 is coated on the entire surface again, and then the photoresist layer 9 is coated by the photolithography process as described above.
A hole is opened at the position where the mark is to be formed, and the exposed ohmic metal 6 is dissolved away to create a new hole 11 with the cross-sectional structure shown in FIG. 12. The thickness will continue to be around 1,000 people.
After depositing 7i1O by vapor deposition, a photoresist layer 9 is formed.
By dissolving the Ti layer, the Ti layer deposited on the second layer is removed, and as shown in Figure 1E, the openings in the silicon oxide film are filled with Ti.
A mark with a concave cross-sectional structure covered with layers is completed.

上記実施例では絶縁膜3として酸化珪素を適用している
が、窒化珪素や窒化アルミニウム等も適用可能である。
In the above embodiment, silicon oxide is used as the insulating film 3, but silicon nitride, aluminum nitride, etc. can also be used.

GaAsFET素子を完成するには前述のように約45
0℃に維持した水素雰囲気中で、オーミック金属層既ち
ソース電極7ならびにドレイン電極のオーミック接触を
確実にする熱処理やゲート電極形成等の工程を施すのは
勿論である。
To complete a GaAsFET device, as mentioned above, approximately 45
Of course, steps such as heat treatment and gate electrode formation are performed to ensure ohmic contact between the ohmic metal layer, the source electrode 7, and the drain electrode in a hydrogen atmosphere maintained at 0°C.

〔発明の効果〕〔Effect of the invention〕

このように本発明に係る位置検出マークの形成方法では
マークとして半導体基板表面を被覆する絶縁膜に形成し
た開孔を金属層で覆った構造をとり、この金属層は開孔
部で半導体基板と接続しているので、電子線照射によっ
て生じる絶縁膜の帯電を防止できる。よって位置検出精
度の向上をもたらしひいては量産上の効果をもたらすも
のである。
As described above, in the method for forming a position detection mark according to the present invention, the mark has a structure in which an opening formed in an insulating film covering the surface of a semiconductor substrate is covered with a metal layer, and this metal layer is connected to the semiconductor substrate at the opening. Since they are connected, charging of the insulating film caused by electron beam irradiation can be prevented. Therefore, the position detection accuracy is improved, which in turn brings about an effect on mass production.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図イ〜ホは本発明の工程を示す断面図第2図イル二
は従来工程を示す断面図である。 1・・・半導体基板、   3・・・絶縁膜4・・・フ
ォトレジスト層、5・・・開 孔6・・・オーミック、
    9・・・フォトレジスト層10・・・Ti層
FIGS. 1A to 1E are cross-sectional views showing the process of the present invention, and FIG. 2I is a cross-sectional view showing the conventional process. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 3... Insulating film 4... Photoresist layer, 5... Opening 6... Ohmic,
9... Photoresist layer 10... Ti layer

Claims (1)

【特許請求の範囲】[Claims] 半導体基板表面に絶縁膜を形成する工程と、この絶縁膜
にフォトレジスト層を被覆する工程と、前記半導体基板
に設ける検出マークならびに素子の形成予定位置に対応
する前記フォトレジスト層を開孔する工程と、この開孔
に露出する前記絶縁膜を除去してパターンを設ける工程
と、このフォトレジストパターンにオーミック金属を被
着する工程と、このフォトレジスト層を溶除する工程と
、マーク形成予定位置の前記絶縁膜パターンから前記オ
ーミック金属を除去する工程と、この絶縁膜開孔部を覆
う他の金属を被着する工程とを具備することを特徴とす
る位置検出マークの形成方法。
A step of forming an insulating film on the surface of the semiconductor substrate, a step of coating the insulating film with a photoresist layer, and a step of opening holes in the photoresist layer corresponding to the positions where detection marks and elements are to be formed on the semiconductor substrate. a step of forming a pattern by removing the insulating film exposed in the opening; a step of depositing an ohmic metal on the photoresist pattern; a step of dissolving the photoresist layer; and a step of forming a mark at a planned position. A method for forming a position detection mark, comprising the steps of: removing the ohmic metal from the insulating film pattern; and depositing another metal to cover the insulating film opening.
JP61294662A 1986-12-12 1986-12-12 Method of forming position detection mark Pending JPS63148629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61294662A JPS63148629A (en) 1986-12-12 1986-12-12 Method of forming position detection mark

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61294662A JPS63148629A (en) 1986-12-12 1986-12-12 Method of forming position detection mark

Publications (1)

Publication Number Publication Date
JPS63148629A true JPS63148629A (en) 1988-06-21

Family

ID=17810672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61294662A Pending JPS63148629A (en) 1986-12-12 1986-12-12 Method of forming position detection mark

Country Status (1)

Country Link
JP (1) JPS63148629A (en)

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