JPS63148325A - Finite state machine - Google Patents

Abstract

PURPOSE:To reduce the area and to improve the performance by connecting plural PLAs (programmable logic arrays) in parallel to realize a single PLA where it is sufficient if a signal passes only one PLA. CONSTITUTION:PLAs 1 are connected in series and parallel in a combinational circuit 10. An input signal 3 to a limited state machine is inputted to the combinational circuit 10 after inputted to an input-side register 2a. The output signal of the finite state machine generated by the combinational circuit 10 and the next state signal are stored in an output-side register 2b and are outputted as an output signal 4 and a state signal 5. The state signal 5 is fed back to the input-side register 2a.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a finite state machine, and particularly to a finite state machine in which a combinational circuit portion is constructed from a PLA (programmable logic array).

[Conventional technology]

Conventionally, this type of finite B machine has been provided with registers 2a and 2b on the input side and output side of a single PLAI, respectively, as shown in the block diagram of FIG. 5, and the status signal 5 is sent to the output side register 2b. It was constructed by feeding back a part of the output to the input of the input side register 2a.

[Problem that the invention seeks to solve]

In the above-described conventional finite state machine using PLA, the combinational circuit portion is composed of a single PLAI. P.L.A.
I basically consists of an AND of n inputs and m outputs, and an OR of m inputs and q outputs, and as the scale increases, problems arise such as an increase in occupied area due to a decrease in area utilization rate and a decrease in speed. arise. When constructing this large-scale finite state machine using a single PLA, there are disadvantages of increased area and decreased performance.

An object of the present invention is to provide a finite BtR machine using PLA with improved performance and integration.

In contrast to the above-described conventional finite state machine using a PLA, the present invention has an original content in that the area can be reduced and performance can be improved by realizing the logic of a single PLA with a plurality of PLAs.

[Means for solving problems]

A finite state machine using a PLA of the present invention is constructed by providing registers on the input side and output side of a combinational circuit, and feeding back a part of the output of the output side register to the input of the input side register. In the finite state machine, the combinational circuit is configured by series/parallel connection, series connection, or parallel connection of a plurality of PLAs.

[Effect]

When trying to implement a certain logic using a PLA, when the depth of the logic increases, the number of product terms, which has a large effect on the area of the PLA, increases rapidly.

Therefore, if a single PLA is realized by connecting a plurality of PLAs in series so as to reduce the logic depth, an increase in area can be prevented. The speed of PLA is proportional to its scale. Therefore, the method of realizing a single PLA by connecting multiple PLAs in parallel, which can be made smaller in size and requires the signal to pass through only one PLA, is as follows.
The present invention, which is effective in improving performance, is based on this principle.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. 1 is a PLA, each of which is connected in series and parallel to form a combinational circuit 10.

2a is an input side register of the combinational circuit 10, 2b is an output side register of the combinational circuit 10, 3 is an input signal line, 4 is an output signal line, and 5 is a part of the output of the output side register 2b to the input side of the input side register. The applied status signal lines 6a and 6b are clock signal lines to registers 2a and 2b. below,
A signal line and a signal will be explained using the same reference numerals. The input signal 3 to the finite state machine is input to the register 2a on the input side, and the output of this register 2a is input to the combinational circuit 10 made up of a plurality of PLAs. In the combinational circuit 10, an output signal as a finite state machine and a state signal of the next state are generated from the input signal 3 and the current state. The generated output signal and status signal are stored in the output side register 2b and output signal 4. It is output as a status signal 5. This output signal 4 becomes the output signal of the finite state machine, and the state signal 5 is fed back from the output side register 2b to the input side register 2a. Note that the respective registers 2a and 2b operate in synchronization with clock signals 6a and 6b, respectively.

FIG. 2 is a block diagram showing a second embodiment of the invention. In this embodiment, a plurality of PLAIs are connected in series to form a combinational circuit 20. The other configurations are the same as in FIG. 1. PLA area increases dramatically as logic depth increases
It is effective in reducing the area of

FIG. 3 is a block diagram showing a third embodiment of the present invention. In this embodiment, a plurality of PLAs are connected in parallel to form a combinational circuit 30. The other configurations are the same as in FIG. 1.

This is effective in improving the performance of PLA, whose speed decreases as the scale increases.

〔Effect of the invention〕

As explained above, the present invention reduces the area by configuring the combinational circuit unit, which is the logic generation unit of a finite state machine using PLA, from a plurality of PLAs.

This has the effect of improving performance.

The effects will be specifically explained using figures. FIG. 4 is a block diagram showing an example where the ALU is used as a combinational circuit. FIG. 5(a) is a block diagram of a case where the device is configured with one PLA, and FIG. 6(b) is a block diagram of a case where the device is configured with three PLAs. The scale of one PLA in the same figure (a> is 1 input
4. Number of outputs 7. The number of product terms is 474. On the other hand, in order to realize the same function, the scale of each PLA in FIG. Number of outputs: 8. Number of product terms 2
0. PLA102 has 10 degrees of input and 5 degrees of output. Number of product terms: 19
．． PLA103 has 13 inputs and 5 outputs. The number of product terms is 19. Since the area of a PLA can be considered to be proportional to the number of product terms x (number of inputs + number of outputs), if the unit area is A, the area of each PLA is as follows. In the case of (a) in the same figure, - number of PLA: 474X (14+7)XA=9
954A, in the case of the same figure (b), PLAIOI: 20X
(12+8)XA=400A, PLAIO2: 19X
(10+5)XA+285A, PLAl 03:
19X (13+5)A=342A Therefore, the same figure (b
) is composed of three PLAs, the area is PLAIOl
, PLA102. The total amount of PLA 103 is 1027A. From the above, if the ALU is configured with three PLAs, it is approximately 1/1 compared to the case where it is configured with one PLA''?
The area can be reduced to 0. In addition, three PLA
Even if we assume that the interconnection area is equal to the area of the PLA section, it will be approximately 1
A reduction of 15 is possible.

The speed of PLA depends on its scale.

The speed of - PLA in the same figure (a) is compared with the speed of the same figure (b).
The speed of each PLA is about 115.

Therefore, in FIG. 2B, the signal passes through three PLAs, so the speed is approximately 315.

Although an example is shown here using an ALU, the same can be said for combinational circuits of similar scale.

In the PLA design support system, PLA program patterns can be easily generated from logical formulas, state transition diagrams, etc.
766-769 (Koski, Y.
, T, Yamada; Proc, 22nd DACp
p766-769.1985), the finite state machine using PLA of the present invention corresponds to a PLA program pattern created from a state transition diagram. If this created PL
If the scale of A is large and problems such as large area and low performance occur, it is necessary to disassemble the state transition diagram and design timing between finite state machines using PLA created by disassembling it. be. For this reason, the design period becomes longer, but in the present invention, we focus only on the PLA of the created finite state machine, and because it is easier to decompose a logical formula than a state transition diagram, we decompose the state transition diagram into a logical formula. By replacing it with decomposition, the design becomes easier. As described above, great effects can be obtained by the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a block diagram showing a second embodiment of the invention, and FIG. 3 is a block diagram showing a third embodiment of the invention. FIGS. 4(a) and 4(b) are block diagrams showing an example of a combinational circuit, and FIG. 5 is a block diagram showing an example of a conventional finite state machine. 1.101,102,103-PLA, 2a. 2b...Register, 3...Input signal, 4...Output signal, 5...Status signal, 6a, 6b...Clock signal, 10°20.30...Combination circuit. 3-Iruka Hanagata 4: Ikafu G No. 2I! 1 spear 3ffJ ((L) (L) $ 4 醊3: Input 葎名＄ 5 Figure

Claims (1)

[Claims] In a finite state machine configured by providing registers on the input side and output side of a combinational circuit, and feeding back a part of the output of the output side register to the input of the input side register, the combinational circuit is connected to a plurality of PLAs.
A finite state machine using PLA, characterized in that it is configured by series/parallel connection, series connection, or parallel connection.