JPS63148310A - Sample value controller - Google Patents

Abstract

PURPOSE:To improve the response characteristic by forcibly driving a sample switch if a measured value or a set value is changed by a certain extent or more and stopping forcible driving for a certain time after the switch is forcibly driven or an operation output is changed by a certain extent or more. CONSTITUTION:The time chart of a sampling pulse Ps is as shown in a figure (A), and a set value SV is changed step-wise at a time t1 as shown in a figure (B). Then, a forcible reset pulse Pc due to a pulse output P1 of a comparator 8 is generated as shown in a figure (E), and a counter 4 is forcibly reset and a sample switch 2 is driven. Since a timer 13 is started at the time t1 by the pulse Pc, a timer output Pt is generated as shown in a figure (C) to stop generation of the forcible reset pulse for a time T1. Consequently, the forcible reset pulse is not generated even if a pulse output P2 shown in a figure (D) is outputted at a time t2 during the time T1.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to improving the response characteristics of a sample value controller.

<Prior Art> An example of the prior art will be explained based on FIGS. 3 and 4. Figure 3 is a diagram showing the principle configuration of the sample value controller, and shows the measured value P.
The deviation e between V and the set value S is led to a proportional calculation means 1, the output of which is sampled by a sample switch 2 which is periodically turned on for a certain period of time, and a manipulated output MV is transmitted via an integral calculation means 3. The integral calculation means 3 holds the manipulated output according to its integral characteristic while the sample switch is off.

FIG. 4 is an explanatory diagram of the operation, and when the deviation e exists, the proportional and integral operations are performed only during the sampling time Tc that occurs every sampling period Ts. Therefore, when there is a deviation, the operation output increases in a stepwise manner as shown in the figure.

A sample value controller that operates in this manner is effective when applied to processes with long dead times, and is effective for processes with long dead times. ! The feature is that once a corrective action is performed, nothing is done for a certain period of time, and the next corrective action is performed only after the results of the corrective action have been sufficiently used. Therefore, it is common to set the sampling period (the period during which nothing is done) to be relatively long compared to the response time of the process.

<Problems to be solved by the invention> However, since the sampling period is set for a long time in this way, there is a problem that even if settings are changed or disturbances occur during that time, nothing will be done until the next sampling time comes. Yes, it is a drawback.

It is an object of the present invention to provide a sample value controller that solves these problems of the prior art.

<Means for Solving the Problems> The structural feature of the present invention is that normally, in a sampling PI controller having the above-mentioned sample switch means, a certain constant value is periodically set for a certain period of time in synchronization with the reset of a timer. a reset means for forcibly resetting the timer by detecting the occurrence of a disturbance or a change in set value having a rate of change greater than or equal to the above; and a reset means for forcibly resetting the timer; The present invention is characterized in that it is provided with a reset prevention means that prevents the T1 timer from being forcibly reset for a certain period of time after a rate of change exceeding the value is detected.

According to the present invention, when the measured value or the set value changes by more than a certain value, the sample switch is forcibly driven, and after this forced driving or the operation output changes by more than the certain value, the sample switch is forcibly driven. If there is, forced drive is blocked for a certain period of time.

Embodiments> The present invention will be explained in detail based on FIG. Components that are the same as those explained in FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted.

4 is a counter forming a timer for periodically generating sample pulses, which counts a certain number of clock pulses CP and generates a count-up pulse P having a pulse width Tc.
generate s. This pulse is input to its own reset terminal R8 via the first input terminal of the OR gate 5, and resets this counter. Assuming that the period of this reset is Ts, the pulse Ps becomes a periodic signal having the period Ts+pulse width Tc, so this is used as an opening/closing signal for the sample switch 2.

6.7 is the first. A second change rate detector monitors the change rate of the set value Sv and measured value PV, respectively, and continuously transmits the change rate output to the comparator 8.9.

The comparator 8.9 sends pulse outputs P+ and P2 to the OR gate 10 when the input change rate signal exceeds a certain value. The OR gate 10 turns on when one or both of the pulse outputs P+ and P2 is input, and its output is transmitted to one input terminal of the OR gate 11. This OR gate 11 has negative logic and logic input terminals, and when this input is zero, the input from the OR gate 10 side is passed through, and is applied to the other input terminal of the OR gate 5 as a forced reset pulse Pc. Counter 4 is forcibly reset via .

The forced reset pulse Pc is further inputted to one terminal of the OR gate 12 and starts the timer 13.

This timer operates for a longer time than the sampling period Ts.
A timer output Pt having a value of 0 is generated and applied to the negative logic input terminal of the OR gate 11.

Therefore, the logic input terminal of the OR gate 11 is positive for a certain period T1 from the timing when the forced reset pulse Pc is generated, so even if a pulse is output from the OR gate 10 during this period, it does not function as a forced reset pulse.

A third change rate detector 15 continuously monitors the change rate of the operation output MV of the sample value controller and transmits a detected output to the comparator 15. Comparator 15 emits a pulse output P3 when the rate of change is above a certain value. This pulse output is applied to the other input terminal of OR gate 12, and starts timer 13 via this OR gate.

Therefore, the forced reset pulse Pc is prevented from being generated during the operation time of the timer even if a change in the operation output exceeds a certain level.

FIG. 2 is an explanatory diagram of the operation, and (A) shows the sampling pulse Ps. (B) shows the case where the set value SV changes in a step manner at time t1, and as shown in (E), a forced reset pulse Pc is generated by the pulse output P1 of the comparator 8, and the counter 4 is forced to reset to approx. sample switch 2 is driven.

Furthermore, this time 1. Since the timer 13 is activated by Pc in synchronization with , a timer output Pt is generated as shown in (C), and the generation of the forced reset pulse is prevented for a time T+. Therefore, even if there is a pulse output P2 due to a change of more than a certain value in the measured value PV as shown in FIG. A normal operation mode is entered in which a reset pulse is generated after counting a predetermined number of times. Such a forced reset pulse blocking operation is the same even when the rate of change of the manipulated output MV is equal to or higher than a certain value.

<Effects of the Invention> As explained above, according to the present invention, when the rate of change in fluctuations in measured values due to setting value changes or process disturbances exceeds a certain value, the normal sampling period is forcibly intervened. It is possible to drive the sample switch, and furthermore, it is possible to prevent forced intervention for a certain period of time when forced intervention occurs or when the rate of change of the manipulated output exceeds a certain value. A sample value controller with improved response characteristics compared to the above can be realized with a relatively simple configuration.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram showing an embodiment of the present invention, Fig. 2 is an explanatory diagram of its operation, Fig. 3 is a configuration diagram showing an example of the conventional technology, and Fig. 4
The figure is an explanatory diagram of the operation. 1... Proportional calculation means 2... Sample switch means 3... Calculation and minute calculation means 4... Counter 5
,10゜11.12...Or Gate 6,7.14
・・・1st゜2nd. Third rate of change detector 8.9.15
...Comparator 13...Timer

Claims (1)

[Claims] Usually, the sampling P has a sample switch means that operates periodically for a certain period of time in accordance with the reset of the timer.
In the I controller, a reset means for forcibly resetting the timer by detecting the occurrence of a disturbance or a change in set value having a rate of change of a certain value or more; A sample value controller comprising a reset prevention means for preventing forced reset of the timer for a certain period of time after detecting a rate of change of the operation output of the value controller that is equal to or higher than a certain value.