JPH0216808A - Duty controller - Google Patents

Abstract

PURPOSE:To detect duties before the interval of a specified time and to control the duties a value below a prescribed value by cancelling the existence period of pulse signals before the specified time in the existence period of the pulse signals which have contributed to counting up. CONSTITUTION:The period of the pulse signals 31 from a pulse generator 11 is counted up 15 as an up signal 34A, and it is counted down 15 as a down signal 34B after the specified time that a delay circuit 12 has delayed. When the signals 31 are furthermore outputted in the middle of counting down, the signals 34B stop. The signals 31 are effective only for the delay time by the circuit 12, and they turn into the signals 34B. A value which is counted in the signals 34A is cancelled and when the signals 31 are outputted in the process, the value at that time is maintained. Consequently, continuous duties are controlled while said delay time is set to be a unit, and the period of a clock pulse 36 is set to be resolution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a duty control device. More specifically, by controlling the duty, which is the percentage of time that a pulse exists within a certain period of time, never exceeds a predetermined value, the device that uses the pulse can be used up to its performance limit. The purpose of the present invention is to provide a duty control device that can perform the following functions.

[Prior Art] The circuit configuration of a conventional pulse generating circuit equipped with a duty control device that keeps the duty, which is the proportion of time during which pulse output exists, to a predetermined value or less, is shown in FIG. 2A and will be described.

11 is a pulse generator for generating a pulse signal 31;
16 is a clock generator for generating a tarok pulse 36; 22 is a pulse signal 31 from the pulse generator 11;
is ANDed with the clock pulse 36 from the ΔND gate 22 during the presence of the pulse signal 31 (AND gate 23 passes the gated clock pulse 36 from the ΔND gate 22). When the counter 23 counts for a certain period of time, a reset signal 44 is sent to the counter 23.
A timer 17 is a comparison circuit which receives from a register 18 a count value 43 from a counter 23 and a set value 38 instructed by a CPU (central processing unit), not shown, and compares it. When the count value 43 exceeds the set point 38, a cutoff signal 37 is generated and the AN
The output of the gate signal 39 from the D gate 19 is cut off. Here, the register 18 has a set value 3B connected to the output of the AND gate 19, which corresponds to the standard value of the duty of a micro-parallel amplifier 29 using a traveling wave tube (DWT), for example. central processing unit (C
PU) and is registered.

The operation of the circuit will be explained with reference to FIG. 2B showing the output signals of each part of the circuit. Pulse signal 3 from pulse generator 11
1 (Fig. 2B (a)) is applied to one input of 22 to the AND game 1, and a clock pulse 36 (b) of period ∆ from the clock generator 11 is applied to the input of the input. The output of the gated clock signal 42(c) is counted by the counter 23 under the period of the reset signal 44(e) from the timer 24, and the output is ANDed. (d>N10N2
is sent to the comparison circuit 17. The duty of C here is △T, (N1 +N2)/T.

The comparator circuit 17 that receives the counter value 43 from the counter 23 compares it with the set value 38 from the register 1B, and when it reaches the set value 38 among the numbers 1 to 43,
A cutoff signal 37 (f) is output, and the gate signal 39 (g) output from the AND gate 19 is cut off. The period T3 during which the cutoff signal 37 (f) is sent is AND
Gate 19 cuts off its output and is connected to the next stage,
For example, it controls the duty of a microwave amplifier.

According to the conventional circuit configuration that controls the duty as described above, the pulse signal 31 from the pulse generator 11 is
When changing the interval at a preprogrammed interval during measurement, the timing at which the pulse signal 31(a) is output as shown in FIG. If the timings applied to the counter 23 overlap, or if the reset signal 44 is applied at the timing shown in (C), the pulse signal @31
(A case may occur that does not overlap with a>.

[Problem to be solved by the invention] For example, a microwave amplifier using a traveling wave tube used in an electron spin resonance (ESR) device continues to output in a duty over state mainly due to the problem of heat generation. Since the time is infinite, a circuit as shown in FIG. 2A is used to control the decoupling time so that it is less than a certain value.

However, according to the conventional example shown in FIG. 2A, since the period of the reset signal 44 applied to the counter 23 is constant, as shown in FIG. 2C, the pulse signal 3'l (a) from the pulse generator 11 is Duty over is detected when the timing at which the reset signal 44 (C) is applied does not overlap with the timing at which the reset signal 44 (C) is applied.
If 4 is input, there is a drawback that duty over cannot be detected. Moreover, in a microwave amplifier using a traveling wave tube, duty over may occur unexpectedly if there is a 1 to 1 trigger operation.

In particular, in electron spin resonance devices, the microwave pulse interval is increased by a small value for each pulse from a predetermined value (
For example, one measurement value is obtained using 1000 pulses.

In this way, when the pulse interval is changed every time a pulse is generated, as shown in FIG. 2C (b), the reset 1
It also happened that the signal 44 was located in the middle of the pulse signal 31 in (a). In many cases, the total value of the pulse width cannot necessarily be known on the pulse generator 11 side, and in that case, if heat generation or the limit is reached, the microwave amplifier using a traveling wave tube will not only stop operating, but also In the worst case, it could even be destroyed. Even if it stopped working, you had to wait several minutes to restart it. Furthermore, even if decoupling occurs, a duty over signal is normally not sent out from a microwave amplifier using a traveling wave tube, so the pulse generator can detect the duty over. Subsequently, a pulse is generated and the test measurement is continued assuming that a normal pulse has been applied to the measurement sample.

Therefore, in the conventional example shown in Fig. 2A, a microwave amplifier using a traveling wave tube is not used, leaving a certain margin for the set duty limit. There is a problem that needs to be solved that it cannot be used until the end.

[Means for Solving the Problems] The present invention has been made to solve these problems, and includes: a delay circuit that delays the pulse signal by a certain period of time that defines the duty of the pulse signal; a first gate that does not allow the output of the delay circuit to pass during the period when the pulse signal exists; a second gate that does not allow the output of the delay circuit to pass during the period when the pulse signal exists;
A counter that counts up and counts down according to the output of the second gate, and outputs a cutoff signal to cut off the pulse signal when the output of the counter is compared with a predetermined value and the output of the counter reaches a predetermined value. A comparison circuit is set up (j).

[Operation] With this configuration, the period of existence of the pulse signal that contributed to the count-up is counted down as the delay time of a certain time that defines the duty elapses, and the period of existence of the pulse signal that contributed to the count-up is counted down. If a new pulse signal is input in the middle of this countdown, the countdown is stopped and neither count up nor count down.1.

Because it operates in this way, it is possible to always detect decoupling for a certain period of time before the current moment and control the duty to below a predetermined value. Now you can use it to the limit.

Embodiment The circuit configuration of an embodiment of the present invention is shown in FIG. 1A and will be described. Here, the same symbols are used for components corresponding to FIG. 2A.

11 is a programmable pulse generator whose pulse width and pulse interval can be arbitrarily changed, and 12 is a delay for outputting the pulse signal 31 from the pulse generator 11 after being delayed by a certain period of time, which is the time that defines the duty. circuit, 13Δ is the delay output 32 from the delay circuit 12, 13B
14A is an inverter that outputs the pulse signal 31 from the pulse generator 11 with its polarity inverted, and 14A performs an AND operation between the pulse signal 31 and the inverter output 33A. counter 15
AN to output as up signal @34A to send to
D gate. 14.8 is an AND gate for ANDing the pulse signal 31 and the inverter output 33B, and outputting it as a down signal 34B when both are "todo", and the up/down counter 15 outputs the input up signal 34A and Obtain the addition/subtraction value from the down signal 34B.16
17 is a clock generator for generating a clock pulse 36 that gives timing to the up/down counter 15;
Compare the calculated count 1 shift (P) 35 with the set value (Q) 38 recorded in the register 18, and set the value 35 to callan 1.
This is a comparison circuit for sending out a cutoff signal 37 that cuts off the output of the AND gate 19 when the set value is 38 or more (P2O>), and the output of the device is applied to the register 18 (not shown). For example, a set value 38 corresponding to a duty limit standard value of a microwave amplifier using a traveling wave tube, etc. is registered by the CPU, and the AND gate 19 outputs a gate signal 39.

The operation of the circuit configured in this way will be explained with reference to FIG. 1B showing the output signals of each part of the circuit. The pulse signal 31 output from the pulse generator 11 (FIG.
l, applied to one input of JAND gate 14A,
To the other input, the delayed output 32 (b) from the delay circuit 12 delayed for a certain period of time is applied via the inverter 13A with its polarity inverted. The time delayed by the delay circuit 12 is determined by the standard value of the duty limit of the circuit to which the signal 39 is applied to the signal 39, or, for example, 1.
If the delay time is less than 5% during mS, the delay time is 1mS
is set to

When the input pulse signal 31 and the inverter output 33A are both 1'', the AND gate 14△ outputs an up signal M.
34A(C) to the up/down counter 15, and the up/down counter 15 outputs the output to the clock generator 16.
The clock pulse 36 from
34A period is counted up. a3 in Figure 1B
In the example shown in FIG. The period during which (f) is 3 -rs
At l, the comparator circuit 17 outputs a cutoff signal 37 (Cl)
As a result, the cutoff signal 37 from the comparator circuit 17
The AND gate 19, which receives the pulse signal 31 which is the output of the pulse generator 11, cuts off the output of the pulse signal 31 as shown by the broken line in (h) during period 1, and generates the signal 39 ( h) is output.

Furthermore, the inverter output 33B from the inverter 13B is applied to one input of the AND gate 14B, and the delay output 32 from the delay circuit 12 is applied to the other input, and both 11 HI! If that's the case, go down and say g34B.
(outputted to the up/down counter 15 as d>,
The up/down counter 15 counts down the clock pulse 36 (e) from the clock generator 16 for the period of the input down signal 34B.

Here, in FIG. 1B, the pulse width of the up signal 34A in (C), which is the pulse width of the pulse signal 31 from the T1 pulse generator 11, is set to 1.
, (e) If the interval of the clock pulse 36 is set to be longer than the Δt1 delay time T, then the values 1 to 35 of (f) output from the up-down quanta 15 of 1 change are as follows. , T, T1 and Δ. That is, count 1 shift 35 of (f) after time - 1 is
/Δ, and after time T, the down signal 34B of (d)
is input to the up/down counter 5, so the value 1 to 35 of (f>) is (T/Δ↑)
-((lower, -d)/Δt).

Therefore, in FIG. 1B, the up signal 3 in (C)
The value 1 to 35 of (f) obtained by counting up the period of 4A is the set value 38 of register 8, Q=
3, if the cutoff signal 37 in (g) is sent (period TS1>), after time T, the down signal 3 in (d) is sent.
4B is input and counted down, and the count 1 in (f) becomes a value lower than the set value 38 of the register 8, so the comparator circuit 17 stops sending out the cutoff signal 37, and the AND gate 19 Return to a state where it can output again.

In this state, if the pulse signal 31 (a) is output from the pulse generator 11, the AND gate 1
The down signal 34B(d) from 4.8 is not output, and the up/down counter 50 count value 25(f) does not decrease.

In this way, the comparator circuit 17 inputs the numbers 1 to 35 and register 1 obtained by the up/down counter 5.
If the value 35 is greater than or equal to the set value 38, the three gate signals from the AND gate 19 are output by sending the cutoff signal 37 to the AND gate 19. Block it out.

In this way, the period of the pulse signal 31 output from the pulse generator 11 is counted up as the up signal 34A, and after a certain period of time set by the delay circuit 12, the period of the pulse signal 31 outputted from the pulse generator 11 is counted up as the down signal 34B. However, if the pulse signal 31 is further output from the pulse generator 11 during the count i~, the down signal 34B is no longer output at that point. The pulse signal 31 from the pulse generator 11 becomes the source of the signal forming the duty cycle, but it is valid from the current moment to the delay time T (FIG. 1B (b)) caused by the delay circuit 12. , after time T, it is output as the down signal 34B, so the up signal 3/1 . The value counted up during A is canceled out, and in the process, the pulse signal 31
When this is output, neither the count-up signal nor the count-down signal is output, and the value at that point is maintained. The difference between the up signal 34A and the down signal 34-B is obtained in units of delay time for each cycle of the tarok pulse 36 from the clock generator 1G, and the cycle of the clock pulse 36 can be resolved. As a result, continuous duty control is realized.

Note that the count value 3 by the up/down counter 15
The resolution of the clock pulse 5 can be easily changed by changing the period of the clock pulse 36 from the tarock generator 16, and the unit time of duty control can be changed easily by changing the delay time of the delay circuit 12. What can you do?

FIG. 1C shows a variation of the device shown in FIG. 1A, in which the pulse generator 11 and the AN
The only difference is that a pulse generator 11B with an integrated D gate 19 is used. The waveforms of each part of the device shown in FIG. 1C are as shown in FIG. 1D, which corresponds to FIG. 1B, and is the output of the pulse generator 11B (a).
The pulse signal 31 of (q) has a cutoff signal 37 of “L +
Since it becomes <i L ++ at the same time as it becomes +, it is output as it is as the gate signal 39 (h). The other waveforms are the same as those shown in FIG. 1B.

[Effects of the Invention] As is clear from the above explanation, according to the present invention, the duty can be continuously controlled in units of a fixed period of time, which limits the performance of microwave amplifiers using traveling wave tubes. The effect of the present invention is extremely large.

[Brief explanation of the drawing]

FIG. 1A is a circuit configuration diagram of one embodiment of the present invention, FIG. 1B is a waveform diagram of signals of each part of the circuit shown in FIG. 1A, and FIG. 1C is a circuit diagram of another embodiment of the present invention. Figure 1D is a waveform diagram of signals in each part of the circuit shown in Figure 1C, Figure 2A is a circuit configuration diagram of a conventional example, Figure 2B is a waveform diagram of signals in each part of the circuit shown in Figure 2A, and Figure 2C is a diagram of signal waveforms in each part of the circuit shown in Figure 2A. 2B is a waveform diagram for explaining the timing of the pulse signal and reset signal shown in FIG. 2B. FIG. 11.11B...Pulse generator 12...Delay circuits 13A, 13B...Inverters 14A, 14. B...AND gate 15...Up/down counter 16...Clock generator 17...Comparison circuit 18...
...Register 19...AND gate 22...
・AND gate 23...Counter 24...Timer 29...Microwave amplifier 31...Pulse signal 32...Delay output 33A
, 33B... Inverter output 34A... Up signal 34.8... Down signal 35... Count 1 round 36... Clock pulse 37... Cutoff signal 38... Set value 39
...Gate signal 42...Goo! Clock signal 43...Count value 44...Reset signal.

Claims (1)

[Claims] Delay means (12) for delaying the pulse signal by a certain period of time that defines the duty of the pulse signal; and first gate means (13A, 14A), and second gate means (13B, 14B) that do not allow the output from the delay means to pass during the period in which the pulse signal exists.
); counter means (15) for counting up clock pulses based on the output from the first gate means and counting down the clock pulses based on the output from the second gate means; and comparing means for outputting a cutoff signal for cutting off the pulse signal when the output from the counter means reaches the predetermined value.