JPH04105551A - Phase control circuit - Google Patents

Abstract

PURPOSE:To effectively supply electric power from an AC power source to a load by phase-controlling a semiconductor switching element with the predetermined maximum phase angle when a phase angle phase-controlled by an input signal exceeds the predetermined phase angle. CONSTITUTION:The level of a signal to inspect whether or not an input signal is within the level of a saw-tooth wave exceeds the maximum level of the input signal in time W1 and becomes as high as the maximum voltage level of the saw-tooth wave when a first comparison circuit 5 becomes active. When the level of the input signal exceeds the maximum output level of the saw-tooth wave, a second comparison circuit 6 draws a latch signal, which is a detection signal to latch a latch circuit 7 through a line l6, and the first comparison circuit 5 draws a low-level signal. Therefore, the latch circuit 7 is latched at a low level and draws low-level output to emit light continuously from the LED 9 of a photocoupler 8.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a circuit for controlling the phase of power supplied from an AC power source to a load.

Prior art The electrical configuration of a conventional phase control circuit is shown in FIG.
A waveform diagram for explaining the operation is shown in FIG. The power supplied from the AC power supply 51 to the load 52 is
1 and a load 52 in series with a bidirectional three-terminal thyristor 53 .

For phase control of the bidirectional three-terminal thyristor 53, a sawtooth wave generating circuit 54, a comparison diagram FI@55, and a photocoupler 56 are provided. The sawtooth wave generation circuit 54 generates a sawtooth wave as shown on line N61 in FIG. 7(2) in synchronization with the voltage waveform of the AC power supply 51 as shown in FIG. 7(1). This generated sawtooth wave is
Each zero cross point θ50 of the AC power supply 51. It suddenly rises around θ60 and reaches the next zero cross point θ60. It falls linearly to around θ70. This sawtooth wave is line n51
The signal is applied to one input terminal of the comparator circuit 55 via. The other input terminal of the comparator circuit 55 is supplied with an input signal for phase control of the bidirectional three-terminal sirisk 53 via a line p52.

Comparison circuit 55 compares the level of the sawtooth wave with the level of the input signal for phase control, and derives a low level output when the sawtooth wave level becomes equal to or lower than the level of the input signal. When the comparison circuit 55 derives a low level output, the light emitting diode 57 included in the photocoupler 56 emits light, and the photothyristor 58 of the photocoupler 56 is activated.

When the photothyristor 58 is activated, a trigger current for firing the bidirectional three-terminal thyristor 53 flows through the resistor 59 and the photothyristor 58 to the gate of the bidirectional three-terminal thyristor 53 .

For example, when an input signal for phase control as shown on line 162 in FIG. 7(2) is given, the period from the phase angle θ52, which is below the level of the sawtooth wave shown on line N61, to the next zero cross point θ60. Then, the bidirectional three-terminal thyristor 53 is fired. The period during which the bidirectional three-terminal thyristor 53 is turned on in this manner is indicated by diagonal lines in FIG. 7(1).

Problem to be solved by the invention In the conventional phase control circuit, the cello cross point θ5
0. At around θ60, the output of the comparator circuit 55 is forced to a high level, and the signal for firing the bidirectional three-terminal cyrisk 53 is no longer generated. In other words, Figure 7 (1)
During the period from θ51 to θ53, W 5 in Figure 7 (2)
Phase control is possible only within the period indicated by 2. however,
Phase angle θ5 between θ51 and θ53 in Fig. 7 (1)
2. When the bidirectional thyristor 53 is fired, the firing state continues until the next zero cross point θ60.

This is because, once the bidirectional three-terminal thyristor 53 enters the firing state, the firing state is self-maintained until the voltage across both ends becomes zero.

A signal for firing the gate of the bidirectional three-terminal thyristor 53 is transmitted at the zero cross point θ50. If the power supply voltage waveform continues past θ60 until the next half cycle, the next half cycle will be in the ignition state from the beginning, making it impossible to perform phase control. Therefore, the zero cross point θ50. θ6
In the vicinity of 0, the generation of the signal for firing the bidirectional three-terminal thyristor 53 is inhibited by the signal from line N53. This range W51 is set relatively large in order to avoid variations in circuit constants and the influence of power supply noise. Therefore, although a half cycle of the AC power supply 51 is originally expressed as a phase angle of 180°, it can only be fired within a maximum range of about 145°. When the effective value voltage of the AC power supply 51 is 100V, the effective value voltage supplied to the load 52 is about 97 to 98V. That is, the AC power supply 51
The power effectively supplied to the load 52 decreases.

An object of the present invention is to provide a phase control circuit that can effectively supply power from an AC power source to a load.

Means for Solving the Problems In the present invention, an AC power source, a load, and a semiconductor switching element are connected in series to form a closed loop, and the power supplied from the AC power source to the load is phase-shifted by the semiconductor switching element. responds to input signals to control;
Means for generating a control signal corresponding to an input signal in synchronization with a voltage waveform of an AC power supply, and responding to the input signal when a phase angle controlled by the input signal exceeds a predetermined phase angle. , in response to signals from the detection signal generation means, the control signal generation means, and the detection signal generation means, and when the detection signal is not generated, the phase of the semiconductor switching element is controlled by the control signal, and the detection signal is generated. This is a phase control circuit characterized by controlling the phase of a semiconductor switching element at a predetermined maximum phase angle when

Function According to the present invention, the semiconductor switching element is connected in series to the AC power source and the load to form a closed loop. The semiconductor switching element performs phase control in response to the human input signal when the phase angle controlled by the input signal in the C1γ phase is one step below the predetermined phase angle. When the phase angle controlled by input No. 13 exceeds the predetermined phase angle, the semiconductor switching element is phase controlled at the predetermined maximum phase angle. Therefore, power can be effectively supplied to the load from the AC power source.

Embodiment FIG. 1 is a block diagram showing the electrical configuration of an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the embodiment shown in FIG. AC power supply 1, load 2, and bidirectional three-terminal thyristor 3, which is a semiconductor switching element, are connected in series to form a closed loop. The power supplied from the AC power supply 1 to the load 2 is phase-controlled by a bidirectional three-terminal thyristor 3.

In relation to the gate circuit of the bidirectional three-terminal thyristor 3,
Sawtooth wave generation circuit 4, first and second comparison circuits 5.6
, a latch circuit 7 and a photocoupler 8 are provided.

The sawtooth wave generating port B4 synchronizes with the voltage waveform of the AC power supply 1 shown in FIG.
11 generates a sawtooth wave. This sawtooth wave is applied to one input terminal of the first comparator circuit 5 via the line 11. A bidirectional three-terminal thyristor 3 is connected to the other input terminal of the first comparator circuit 5 via a line 12.
An input signal for phase control is given. This input signal has a level ranging from 0 to IOV, representing a dimming level of 0 to 100%. The zero cross point θ0 of the voltage waveform of the AC power supply 1 shown in FIG. 2 (1). θ10. Near θ20, during the period Wl shown in FIG.
3. From the sawtooth wave generation circuit 4,
A signal for detecting whether the level of the input signal is within the level range of the sawtooth wave applied to one input terminal of the first comparator circuit 5 is also derived. This signal is applied to one input terminal of the second comparison circuit 6 via the line 14. This signal has a level exceeding the maximum level of the input signal when the signal via line 13 forces the output level of the first comparison circuit FI@5 to a high level, and the first
This is the signal that is at the maximum voltage level of the sawtooth wave when the comparator circuit 5 is activated. An input signal is applied to the other input terminal of the second comparator circuit 6 via a line 12. Therefore, when the level of the input signal from the second comparison circuit 6 exceeds the maximum output level of the sawtooth wave, the line 16
A latch signal, which is a detection signal to be latched by the latch circuit 7, is derived through the latch circuit 7.

When a signal is applied to the control input terminal via line 16, the latch circuit 7 stores the data input signal at the time when the signal is applied, and continuously derives it as a data output signal. When no signal is applied to the control input terminal of the latch circuit 7, the signal applied to the data input terminal is directly derived from the output terminal. When a signal to be latched by the latch circuit 7 is derived via the line β6, a low level signal is derived from the first comparison circuit 5. therefore,
The latch circuit 7 is latched at low level, and the photocoupler 8
A low level output is derived that causes the light emitting diode 9 of the light emitting diode 9 to continuously emit light. When the light emitting diode 9 emits light continuously, the photothyristor 10 causes current to flow through the resistor 11 to the gate of the bidirectional three-terminal thyristor 3 every half cycle of the AC power supply 1, and the bidirectional three-terminal thyristor 3 is fired.

In this way, as shown by hatching in FIG. 2(1), once the bidirectional three-terminal thyristor 3 is fired at the phase angle θ1, the bidirectional three-terminal thyristor 3 is fired every half period.

FIG. 3 is a block diagram showing the electrical configuration of another embodiment of the present invention, and FIG. 4 is a waveform diagram for explaining the operation of the embodiment shown in FIG. This embodiment is similar to the embodiment shown in the first figure, and corresponding parts are provided with the same reference numerals. It should be noted that the input signal for phase control is provided via line 17 as a digital signal.

In relation to the gate circuit of the bidirectional three-terminal thyristor 3,
power supply synchronization circuit 12, counter 13, clock circuit 14,
A monostable circuit 15, a latch circuit 17, and a photocoupler 8 are provided. The power synchronization circuit 12 derives the signal shown in FIG. 4(2) via the line 18 in synchronization with the voltage waveform of the AC power source 1 shown in FIG. 4(1). Figure 4 (2)
The signal shown in FIG. This is a signal indicating that it is near θ40. This signal is line 1
8 to a counter 13 and a monostable circuit 15.

The counter 13 uses an input signal given through a line 17 as a preset value for the count value, latches it when a signal is given through a line 18, and counts in a direction in which the count value decreases according to a signal given from the clock circuit 14. do. When the count value of the counter 13 becomes zero, a signal is derived from the counter 13 via one line.

Monostable circuit 15 is responsive to signals on lines 18 and 19 such that the output from counter 13 is connected to power synchronization circuit 12.
When the output rises during the high level period, the low level output is transferred to the latch circuit 17 as shown in FIG. 4 (4).
Give the control input terminal ζ2. The latch circuit 17 latches the signal that has changed to high level from the counter 13 via one line, and the output ζjA of the latch circuit 17 becomes low level. In this way, as shown in FIG. 4 (5), after time t2, the output of the latch circuit 17 becomes high level. Around time t3, the output of the Sochi circuit 17 momentarily goes low. The signal applied to the monostable circuit 15 via the line p9 from the output power (which is derived from the counter 13, i.e., the output from the counter 13) that is instantaneously at a low level until it reaches the level ζ is, for example, The input from the power supply synchronization circuit 12 via the line 18 is given to the reset/soto terminal of a monostable circuit realized by a standard product 74HC123 (trade name: Texas Instruments Inc.) as a logic integrated circuit. , is given to the B input terminal.The output level number of the latch circuit 17 is the logical inversion of the input level.In other words, for a low level input, an output of 1 level, and an input of S level The output will be low level.

When a low-level output is derived from the latch circuit 17, the light emitting diode 9 is lit and the bidirectional three-terminal thyristor 3 is fired 6. When the bidirectional three-terminal thyristor 3 is fired - degree , the ignition state continues until the voltage between the pair of output terminals becomes zero. Therefore, in FIG. 4(5), the light from the light emitting diode 9 momentarily hits the photodiode 1 at around 3 on the clock.
Even if it is not given zero, the bidirectional three-terminal thyristor 3 maintains the firing state.

The clock circuit 14 generates a predetermined number of pulses, for example 100, within a half period of the power supply voltage of the AC power supply 1. As an input signal for phase control, for example, 10
To perform 0% phase control, a value of 1 is given so that one pulse is counted. If a value of zero is given, the counter 13 will count up to the maximum count value, so the minimum count value of 1 is given. When the value of the phase angle to be phase controlled is small, a large number is given as the input signal.

Such conversion of an input signal into a complement can be performed by simple arithmetic processing in a light control device or the like that provides the input signal.

FIG. 5 shows the voltage applied to the cathode of the light emitting diode 57.9 in the conventional phase control circuit and the phase control circuit according to the above-described embodiment. As shown in FIG. 5(1), in the conventional phase control circuit, even if the phase angle to be controlled is maximized, there is a long period in which the light emitting diode 57 cannot be turned on. Therefore, the amount of power supplied from the AC power supply 51 to the load 52 decreases. FIG. 5(2) shows the latch circuit 7°17 according to the embodiment described above.
Shows the output from When the phase angle is maximized, the output from the latch circuit 7.17 is continuously at a low level and only momentarily becomes a high level.

Effects of the Invention As described above, according to the present invention, when the phase angle controlled by the input signal exceeds a predetermined phase angle,
Since the phase is controlled at a predetermined maximum phase angle, it is possible to effectively supply power from an AC power supply to a load.

Further, according to the present invention, when performing phase control on the semiconductor switching element at a predetermined maximum phase angle, the phase control is started when the amplitude of the power supply voltage of the AC GL power supply is small. Since power is not suddenly supplied, it is possible to reduce the occurrence of high frequency noise.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the electrical configuration of one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 3, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 3, and FIG. 5 is a waveform diagram for explaining the effects of the embodiment shown in FIGS. FIG. 6 is a block diagram showing the electrical configuration of a conventional phase control device, and FIG. 7 is a waveform diagram for explaining the operation of the conventional phase control device. 1. AC power supply, 2. Load, 3. Bidirectional three-terminal sirisk, 4. Sawtooth wave generation circuit, 5. First comparison circuit.
6. Second comparison circuit, 7, 17 Latch circuit, 8. Photocoupler, 9. Light emitting diode, 10. Ho1-thyristor, ] 2. Power synchronization circuit, 13. Counter, 14. Clock circuit, 15. Monostable circuit agent, patent attorney, Keiichi Strokazu. Part chart chart chart chart chart

Claims (1)

[Claims] The AC power supply, the load, and the semiconductor switching element are connected in series to form a closed loop, and the phase of the power supplied from the AC power supply to the load is controlled by the semiconductor switching element. means for generating a control signal corresponding to the input signal in response to an input signal of the AC power supply in synchronization with the voltage waveform of the AC power supply; means for generating a detection signal when the phase angle exceeds a predetermined phase angle; and in response to signals from the control signal generation means and the detection signal generation means, when the detection signal is not generated, the semiconductor 1. A phase control circuit comprising: controlling the phase of a switching element, and controlling the phase of the semiconductor switching element at a predetermined maximum phase angle when the detection signal is generated.