JPS63147018U - - Google Patents

Info

Publication number
JPS63147018U
JPS63147018U JP3980987U JP3980987U JPS63147018U JP S63147018 U JPS63147018 U JP S63147018U JP 3980987 U JP3980987 U JP 3980987U JP 3980987 U JP3980987 U JP 3980987U JP S63147018 U JPS63147018 U JP S63147018U
Authority
JP
Japan
Prior art keywords
transistor
collector
mixed
emitter
injected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3980987U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3980987U priority Critical patent/JPS63147018U/ja
Publication of JPS63147018U publication Critical patent/JPS63147018U/ja
Pending legal-status Critical Current

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Landscapes

  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Superheterodyne Receivers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例の構成を示す回路
図、第2図は同実施例における合成トランジスタ
′のエミツタ回路を示す回路図、第3図はサ
テライト信号のスペクトラムを示す図、第4図は
周波数変換を行う受信回路の構成を示すブロツク
図、第5図は従来の周波数変換回路の構成を示す
回路図である。 Q…発振トランジスタ、Q′…混合トラン
ジスタ(ベース接地された混合トランジスタ)、
11…コレクタ抵抗、R12…結合抵抗。
FIG. 1 is a circuit diagram showing the configuration of an embodiment of this invention, FIG. 2 is a circuit diagram showing the emitter circuit of the composite transistor Q 2 ' in the same embodiment, and FIG. 3 is a diagram showing the spectrum of a satellite signal. FIG. 4 is a block diagram showing the configuration of a receiving circuit that performs frequency conversion, and FIG. 5 is a circuit diagram showing the configuration of a conventional frequency conversion circuit. Q1 ...Oscillation transistor, Q2 ' ...Mixed transistor (base-grounded mixed transistor),
R11 ...Collector resistance, R12 ...Coupling resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 局部発振回路を構成する発振トランジスタのコ
レクタにコレクタ抵抗を設け、前記コレクタ抵抗
に得られる発振出力信号を結合抵抗を介して混合
トランジスタのエミツタに注入するとともに、前
記混合トランジスタのベースを接地し、かつ、周
波数変換されるべき入力信号を前記混合トランジ
スタのエミツタに注入したことを特徴とする周波
数変換回路。
A collector resistor is provided in the collector of an oscillation transistor constituting a local oscillation circuit, an oscillation output signal obtained at the collector resistor is injected into the emitter of the mixed transistor via a coupling resistor, and the base of the mixed transistor is grounded, and . A frequency conversion circuit, characterized in that an input signal to be frequency converted is injected into the emitter of the mixed transistor.
JP3980987U 1987-03-18 1987-03-18 Pending JPS63147018U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3980987U JPS63147018U (en) 1987-03-18 1987-03-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3980987U JPS63147018U (en) 1987-03-18 1987-03-18

Publications (1)

Publication Number Publication Date
JPS63147018U true JPS63147018U (en) 1988-09-28

Family

ID=30853329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3980987U Pending JPS63147018U (en) 1987-03-18 1987-03-18

Country Status (1)

Country Link
JP (1) JPS63147018U (en)

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