JPH01167771U - - Google Patents
Info
- Publication number
- JPH01167771U JPH01167771U JP1988063147U JP6314788U JPH01167771U JP H01167771 U JPH01167771 U JP H01167771U JP 1988063147 U JP1988063147 U JP 1988063147U JP 6314788 U JP6314788 U JP 6314788U JP H01167771 U JPH01167771 U JP H01167771U
- Authority
- JP
- Japan
- Prior art keywords
- mixer
- circuit
- double
- tuner
- convergence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims 2
- 230000000903 blocking effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 1
Description
第１図は、この考案の一実施例によるダブルバ
ランスドミキサ回路の構成を示す回路図、第２図
は、第１図の高周波領域における等価回路図、第
３図は、第２図の等価回路の周波数特性を示す図
、第４図は、ＣＡＴＶに用いられるダブルコンバ
ージヨンチユーナの構成例を示すブロツク図、第
５図は、第４図の第１のミキサ回路４の詳細を示
す回路図、第６図は、第５図の高周波領域におけ
る等価回路図、第７図は、第６図の等価回路の周
波数特性を示す図である。
４……第１のミキサ回路、８……第２のミキサ
回路、１６……混合部、２３，２４……トラツプ
回路。
Fig. 1 is a circuit diagram showing the configuration of a double balanced mixer circuit according to an embodiment of this invention, Fig. 2 is an equivalent circuit diagram in the high frequency region of Fig. 1, and Fig. 3 is an equivalent circuit diagram of Fig. 2. 4 is a block diagram showing a configuration example of a double conversion tuner used in CATV; FIG. 5 is a circuit showing details of the first mixer circuit 4 in FIG. 4. 6 is an equivalent circuit diagram in a high frequency region of FIG. 5, and FIG. 7 is a diagram showing frequency characteristics of the equivalent circuit of FIG. 6. 4...first mixer circuit, 8...second mixer circuit, 16...mixing section, 23, 24...trap circuit.
Claims (1)
回路にダブルバランスドミキサを用いたダブルコ
ンバージヨンチユーナにおいて、前記ダブルバラ
ンスドミキサの平行出力線に第１のミキサ回路へ
注入される第２の局部発振回路の発振周波数を阻
止するトラツプ回路を介挿したことを特徴とする
ダブルコンバージヨンチユーナにおけるミキサ回
路。 In a double convergence tuner having first and second mixer circuits and using a double balanced mixer in the first mixer circuit, the parallel output line of the double balanced mixer is injected into the first mixer circuit. 1. A mixer circuit for a double convergence tuner, characterized in that a trap circuit is inserted for blocking the oscillation frequency of a second local oscillation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988063147U JPH01167771U (en) | 1988-05-13 | 1988-05-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988063147U JPH01167771U (en) | 1988-05-13 | 1988-05-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01167771U true JPH01167771U (en) | 1989-11-27 |
Family
ID=31288658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988063147U Pending JPH01167771U (en) | 1988-05-13 | 1988-05-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01167771U (en) |
-
1988
- 1988-05-13 JP JP1988063147U patent/JPH01167771U/ja active Pending
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