JPH01124707U - - Google Patents
Info
- Publication number
- JPH01124707U JPH01124707U JP2025688U JP2025688U JPH01124707U JP H01124707 U JPH01124707 U JP H01124707U JP 2025688 U JP2025688 U JP 2025688U JP 2025688 U JP2025688 U JP 2025688U JP H01124707 U JPH01124707 U JP H01124707U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- locked loop
- frequency
- signal
- conversion circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Superheterodyne Receivers (AREA)
Description
第１図はこの考案の一実施例による周波数変換
回路の構成を示すブロツクダイヤグラム、第２図
は従来の周波数変換回路の構成を示すブロツクダ
イヤグラム、第３図はこの考案の一実施例および
従来の周波数変換回路において用いられている増
幅回路の入出力特性を示す図である。
２１……高域ろ波器、２２……低域ろ波器、９
……混合器。
Figure 1 is a block diagram showing the configuration of a frequency conversion circuit according to an embodiment of this invention, Figure 2 is a block diagram showing the configuration of a conventional frequency conversion circuit, and Figure 3 is a block diagram showing the configuration of a conventional frequency conversion circuit. FIG. 3 is a diagram showing input/output characteristics of an amplifier circuit used in a frequency conversion circuit. 21...High-pass filter, 22...Low-pass filter, 9
...Mixer.
Claims (1)
器が第１の入力端に受ける入力信号の周波数と第
２の入力端に受ける前記位相同期ループの出力信
号の周波数との差の周波数を有する信号を出力す
る周波数変換回路において、前記位相同期ループ
の出力端と前記混合器の第２の入力端との間に介
挿され、前記位相同期ループの出力端に発生する
信号の基本波を前記混合器に供給する低域ろ波器
と、前記位相同期ループの出力端に発生する信号
の高調波を前記位相同期ループにフイードバツク
する高域ろ波器とを具備する事を特徴とする周波
数変換回路。 A signal comprising a phase-locked loop and a mixer, and having a frequency that is the difference between the frequency of an input signal received by the mixer at a first input terminal and the frequency of an output signal of the phase-locked loop received at a second input terminal. A frequency conversion circuit is inserted between the output end of the phase-locked loop and the second input end of the mixer, and the frequency conversion circuit outputs the A frequency conversion circuit comprising: a low-pass filter that supplies the signal to the phase-locked loop; and a high-pass filter that feeds back harmonics of a signal generated at the output end of the phase-locked loop to the phase-locked loop. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2025688U JPH01124707U (en) | 1988-02-18 | 1988-02-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2025688U JPH01124707U (en) | 1988-02-18 | 1988-02-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01124707U true JPH01124707U (en) | 1989-08-24 |
Family
ID=31236467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025688U Pending JPH01124707U (en) | 1988-02-18 | 1988-02-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01124707U (en) |
-
1988
- 1988-02-18 JP JP2025688U patent/JPH01124707U/ja active Pending
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