JPS63146583A - Electronic camera - Google Patents

Abstract

PURPOSE:To obtain an excellent electronic camera having the convenient of use of using a power supply means to store the picture information of a memory card in loading the memory card so as to constitute a camera without using a driver. CONSTITUTION:In detecting the loading of a memory card 15, the cell 23 of an electronic camera is supplied as the backup cell of the memory card 15. That is, the memory card 15 having the data storage backup cell is used for the means recording picture information and in loading the memory card 15 into the electronic camera, the cell 23 arranged in the electronic camera is used in common with the backup cell built in the memory card 15 to stop the power supply of the backup cell, then the service life of the back cell in the memory card 15 is improved remarkably in addition to the reliability and convenience of use of the memory card 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an electronic camera using a memory card for recording still images.

(Prior Art) Recently, an electronic camera using a solid-state image sensor such as a CCD and a rotating magnetic recording medium has been proposed as an alternative to a camera that utilizes the exposure of photographic film.

As shown in FIG. 15, the basic configuration of this electronic camera includes a lens 1501, an aperture 1502, and an optical shutter 150.
3, the image is photoelectrically converted by a CCD 15ρ4, the image signal is separated into a luminance signal and a color difference signal by a signal processing circuit 1505, and a recording circuit 1506 performs signal processing suitable for magnetic recording (FM modulation, etc.). It is configured to record on a rotating magnetic recording medium (magnetic sheet) 1508 via a head 1507. 1509 is the above magnetic sheet 150
9 is attached to the motor to rotate it. Furthermore, in order to reproduce this still image, a signal is read from a magnetic sheet, converted into a video signal by a reproduction circuit, and reproduced on a TV monitor. As is clear from this explanation, this method uses a magnetic sheet drive bag inside the camera! (Motor 1509
), however, cameras are often used under harsh environmental conditions such as vibration and temperature conditions.
There were many technical problems in rotating the magnetic sheet stably.

Therefore, there are electronic cameras configured without using such a drive device1, such as those with built-in magnetic bubble memory as seen in Japanese Patent Application Laid-Open No. 57-28480, and 5 Japanese Patent Application Laid-Open No. 57-123768. This is a magnetic bubble memory as seen in the above publication, which can be attached and detached like a film. In other words, these methods seem to be more reliable in terms of reliability because they do not use any moving parts such as rotating motors. Especially the latter (Unexamined Japanese Patent Publication No. 57-1237
68 Publication) seems to be superior in that it can be attached and detached once, but due to the structure of the magnetic bubble memory, it requires a large number of coils to transfer the recorded cylindrical magnetic domains (bubble magnetic domains), and the current Even in terms of technology, a package for magnetic bubble memory has a thickness of 6 mm. The former (Unexamined Japanese Patent Publication No. 1973)
7-213480), it doesn't really matter if it is built into the camera body, but if you want to attach and detach this magnetic bubble memory and use it like a film,
It's not easy to use at all. In other words.

It can be said that the technical challenge in this field is to realize an electronic camera that is highly reliable and easy to use.

(Problems to be Solved by the Invention) As described above, it has been a technical problem in this field to realize an electronic camera that is easy to use without using a driving device that causes problems with electronic cameras.

An object of the present invention is to provide a novel electronic camera that solves these technical problems.

[Structure of the invention]

(Means for Solving the Problems) This invention uses a memory card with a built-in backup battery for storing memory, and an electronic device that stores digital signals photoelectrically converted by a solid-state image sensor such as a CCD in the memory card. It is a camera, and when it detects that this memory card has been inserted, it supplies the battery of the electronic camera as a backup battery for the memory card.

(Function) The means for recording image information is a memory card with a backup battery for data storage, and when this memory card is inserted into an electronic camera, the battery installed in the electronic camera is activated by the built-in memory card. In order to double as a backup battery and stop the voltage supply of the backup battery,
In addition to the reliability and ease of use of the memory card, the lifespan of the backup battery inside the memory card can be greatly improved.

(Embodiment) An electronic still camera system according to the present invention is composed of an electronic camera section and an electronic album section.

The former is an electronic camera that uses a semiconductor memory card as a recording medium, and the latter is a playback device that reads the image information captured by the electronic camera and recorded on the memory card from the memory card and displays it on a monitor such as a TV receiver. It has a function to display image information on a large-capacity optical disk and to file image information on a large-capacity optical disk.

Hereinafter, an electronic camera according to an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, which is a perspective view of an electronic camera seen from the rear, 1. Although explanations of parts having the same functions as a normal camera will be omitted, there is a release (shutter) on the main body 10 of the electronic camera (hereinafter simply referred to as a camera). button) 11, retake) button 12 used when shooting fails
, a semiconductor memory card 15 unique to the electronic camera of the present invention is installed in the main body 10 in which the shot number display section 13 is arranged.
An insertion opening 14 is provided so that the can be inserted from the right side. An arrow 15a indicating the direction of insertion into the camera and a color display section 15b are provided on the surface of the memory card 15.

The color display section 15b is used to let the user confirm that the card is inserted into the camera. For this purpose, the camera body 10 is provided with a card confirmation window 16 corresponding to the color display section i5b. A strobe hot shoe 17 is provided above the viewfinder section of the camera in the same way as in a normal camera. Reference number 18 indicates a shutter speed selection dial.

FIG. 2 shows the basic configuration of an electronic camera according to the present invention. This camera system operates in a moving image mode and a still image mode. When photographing, the lens system 21 adjusts focusing, the shutter speed selection dial 18 adjusts the shutter speed, and the aperture 22 adjusts, as in a normal camera.

This electronic camera uses an electronic shutter system. According to this, the charge accumulation time of the CCD array on which the image of the subject is formed via the lens system 21 is controlled.

First, when the Raylies 11 is pressed halfway, the power supply (battery)
The power supply voltage from 23 is supplied to each electronic circuit, and the shutter control circuit 24 operates the drive circuit 25, thereby operating the camera in the video mode.

The drive circuit 25 receives a basic clock signal, a vertical synchronization signal and a horizontal synchronization signal of the television system, a vertical transfer pulse for driving the CCD, a horizontal transfer pulse, and a field shift pulse (superimposed on the vertical transfer pulse), and the CCD.
A control signal is generated for a preprocessing circuit 27 for processing the signal from 26.

In the video mode, the drive circuit 25 supplies the CCD 26 with real-time drive pulses (1/30 per frame of the TV system).
seconds). A preprocessing circuit 27 processes the output signal from the CCD 26 and supplies it to a monitor such as a liquid crystal display or a viewfinder 30 to display a moving image. The operation in video mode is the same as that of a normal video camera.

When the release 11 is fully pressed, the operation shifts to still image mode. In the still image mode, the shutter control circuit 24
generates a shutter pulse, and in response, the drive circuit 2
Reference numeral 5 indicates a control signal for the A/D conversion circuit 28 that converts the image information signal output from the preprocessing circuit 27 into a digital signal, and an address for the semiconductor memory card 15 that records the digital image information signal from the A/D conversion circuit 28. providing control signals including signals; As a result, the photographed still image information signal is converted into a digital signal and stored in the semiconductor memory card 15. In the still image mode, the drive circuit 25 controls the charge accumulation time of the C0D 26 according to the set shutter time (speed), and provides information regarding the shutter time to the shutter control circuit 24 via the shutter speed selection dial 18. It will be done. At the same time as the shutter is fully pressed, the aperture value and shutter speed value are read out from the shutter control circuit 24, and these can be recorded in the memory card 15 along with data such as date and time via the data recording circuit 29. Furthermore, during strobe photography, the drive circuit 25 sends the strobe light emission signal to the hot shoe 17.
is supplied to the strobe device, which emits a flash of light onto the subject. The supply of power supply voltage to each circuit in which data is recorded on the memory card is stopped.

Another feature of the camera of the present invention is that the readout speed of the image information signal from the CCD 26 is different between the moving image mode and the still image mode. That is, in the video mode, the drive circuit supplies real-time drive pulses (vertical synchronization signal, horizontal synchronization signal, vertical transfer pulse, horizontal transfer pulse) to read image information signals from the CCD at a speed specified by the TV system. On the other hand, in the still image mode, the drive circuit 25 reduces the frequency of the drive pulse supplied to the ccn, thereby reducing the COD
The image information signal representing a still image is read out at a slower speed than in the moving image mode, which means that the conversion speed of the A/D converter and the writing speed of the memory card can be low. This allows the use of low-speed A/D converters and semiconductor memories.

In the moving picture mode, the CCD 26 operates in the same way as in a normal video camera, but in the still picture mode, it operates as follows.

The shutter control circuit 24 generates a shutter pulse in synchronization with the vertical synchronization signal immediately after the release 11 is fully pressed, and the drive circuit 25 generates a first field shift in still image mode in synchronization with the falling edge of the shutter pulse. Generates a pulse. The charge of each pixel of the COD is read out to the vertical transfer section by this field shift pulse, and the read charge is swept out in synchronization with the number of vertical transfer pulses equal to the number of stages of the subsequent vertical transfer section. This swept-out charge is not used.Then, the drive circuit supplies a second field shift pulse to the CCD to read out the charge of each pixel to the vertical transfer section. Reduce the frequency of the signal by, for example, half. As a result, the drive circuit reduces the frequency of the drive pulse by half. Therefore, the still image information signal is read out from the CCD at half the speed of the moving image mode. At the same time, drive circuit A
The frequency of the drive signal for the /D converter 28 and memory card 15 is halved, thereby performing the /D conversion and writing to the memory card at low speed. The frequency of the drive pulse can be easily switched by using a switching pulse to switch the division ratio of a frequency divider that supplies the output signal of the crystal controlled oscillator to the drive circuit. During camera assembly or adjustment, the frequency of the clock pulse can be changed to confirm the appearance of a moving image, adjust the timing of the A/D converter and memory card, etc.

A semiconductor memory card, which constitutes one of the features of the present invention, includes a built-in backup battery for data storage. After the memory card is loaded into the camera body, the memory card 15 receives power supply voltage from a battery 23 built into the camera body. This can extend the life of the battery built into the memory card. The basic configuration of the memory card 15 will be described with reference to FIG.

Memory cards can be easily manufactured using IC card manufacturing technology that is currently being developed. This memory card has multiple static RMAs (RA) on the printed circuit board.
A power supply terminal 33 and an external terminal 32 including a data terminal, an address terminal, and a control terminal are provided at the end of the card. When the memory card is loaded into the camera body, it receives signals and power supply voltage through these terminals. The memory card has a built-in dedicated battery 34. A power switching circuit 35 is provided to switch the power supplied to the RAM chip 33 from the built-in battery 34 to the battery 23 of the camera body when the card 15 is loaded into the camera body.

An example of the power supply switching circuit 35 is shown in FIGS. 4(A) and 4(B). In the example of FIG. 4(A), when no memory card is loaded in the camera, the internal battery 34
A power supply voltage Va is coupled to the RAM chip 32 via the transistor 41. When a memory card is loaded into the car camera and a power supply voltage Vc (Va<Vc) is applied to the power supply terminal 33, Vc is coupled to the RAM chip 32 via the transistor 42, and as a result, the transistor 41 is closed. As a result, the RAM chip 32 is connected to the battery 2 of the camera body.
Receives voltage supply from 3.

FIG. 4(B) is an example of a configuration using MOS transistors, and when a memory card is not loaded in the camera, the RAM chip 32 is connected to the battery 3 through a transistor 43.
Receives voltage supply from 4. On the other hand, when the memory card is loaded into the camera, the power supply voltage Vc of the battery 23 of the camera is supplied to the RAM chip 32 via the power supply terminal 33 and the transistor 44. Which causes transistor 43 to close.

battery 2 when the memory card is securely loaded into the camera.
3 is coupled to the power supply terminal 33 of the memory card 15. The configuration for this purpose is shown in FIG. 5. When the memory card 15 is inserted in the direction of the arrow and is securely loaded into the connector 51 of the camera body, the light emitting diode 52 is connected to the light receiving diode 5.
Light irradiation to 3 is blocked.

In response, the light receiving diode 53 turns on the switch 54 between the battery 23 and the connector 51. As a result, the memory card receives power supply voltage from the battery 23. As a modification, a reflector may be provided on the memory card, and the switch 54 may be switched by detecting reflected light from the reflector with a photodetector.

Referring to FIG. 6, a solid-state imaging device using one interline transfer type CCD array will be described.

In this element, pixels 61 consisting of photoelectric conversion elements such as photodiodes are arranged two-dimensionally, and on each pixel are R (red), G (green), and B (blue).
One of the optical filters for separating the light components of e) is arranged. Although various configuration examples of optical filters are known, the arrangement of the optical filters in the camera of the present invention is not limited to any particular one. In the case of a camera, high image quality is required, so the CCD array of this embodiment is, for example, horizontally 80
It has a total of 400,000 pixels, including 0 pixels and 500 vertical pixels.

Each pixel accumulates charges according to the amount of incident light. The number of stages of the 0 overlapping transfer section 62, in which the vertical transfer section 6z is provided corresponding to the pixels of each row arranged in the vertical direction, is 250, which is half the number of pixels of each row.

A horizontal transfer section 63 is provided adjacent to the end of the vertical transfer section 62 . An output amplifier 64 is coupled to the horizontal transfer section 63 for sequentially reading out accumulated charges from the CCD array.

The vertical transfer section 62 is supplied with a vertical transfer pulse φV, and the horizontal transfer section 63 is supplied with a horizontal transfer pulse φH.

A field shift pulse FSP is superimposed on the vertical transfer pulse in synchronization with the vertical synchronization signal. The accumulated charge of each pixel is transferred to the corresponding vertical transfer section 62 in response to the field shift pulse FSP. The charge transferred to the vertical transfer section 62 is then transferred toward the horizontal transfer section 63 as shown by the arrow by 250 vertical transfer pulses φV. The charges transferred to the horizontal transfer section 63 are transferred to the horizontal transfer pulse φH.
is transferred through the horizontal transfer section by the output amplifier 64.
is read from. In reality, the vertical transfer pulse φV is 4
The horizontal transfer pulse φH is of two phases. Such a method of driving a CCD playback is not unique to the electronic camera of the present invention, but belongs to well-known techniques for video cameras. As shown in FIG. 2, the output electrical signal of the CCD array is applied to a monitor 30 provided in the camera body through a preprocessing circuit 27 to display a moving image, and is also applied to an A/D converter 28. Here, in still image mode, it is converted into a digital signal for recording on a memory card. This signal processing is shown in detail in Figure 7.
As shown in the figure.

In FIG. 7, when the drive circuit 25 supplies drive pulses (including vertical and horizontal transfer pulses, field system pulses, and reset pulses that reset the output amplifier 64) to the CCD array 26, the output signal of the CCD array 26 is output to the output amplifier 64. 64, and is applied to the C processing circuit 27b via the preamplifier 27a. This processing circuit 27b is an R
, G, and H color signals into R, G, and B signals, and has the function of performing white balance correction and gamma correction on these signals. It is led to a liquid crystal monitor 30 for displaying RD, GD, and BD double signal video images that have been subjected to white balance correction. monitor 30
A vertical synchronizing signal V and a horizontal synchronizing signal H are supplied from the drive circuit 25 to the vertical synchronizing signal V and the horizontal synchronizing signal H. The captured image can be monitored on the liquid crystal monitor 30, and the aperture value, angle of view, etc. for photographing a still image can be determined.

The above is the explanation for monitoring a video.

When the release is fully pressed, the drive circuit 25
The clock frequency applied to the drive circuit decreases, and the signal frequency output from the drive circuit decreases. Therefore, still image information is output from the CCD array 26.

As in the case of the moving picture mode, R2°G2. A B2 signal is taken out. These output signals are applied to a mixing circuit 27c to generate R, G, and B serial signals DI.
is converted to This serial signal is applied to the A/D converter 28, converted into, for example, an 8-bit digital signal, and applied to the data terminal of the memory card 15. Drive circuit 25
is R where the digital signal of the memory card 15 is to be stored.
Apply address information of the AM chip to the address terminal.

8 and 9 show the configurations of the processing circuit 27b and mixer 27c in FIG. 7, respectively, and the operations of the processing circuit 27b, mixer 27c, and A/D converter 28 in FIGS. 10 and 7. The timing chart is shown below.

In FIG. 8, the input signal ID is applied to sample/hold circuits 81a, 81b, 81c, and the drive circuit 25
The sequential sample pulses SPI shown in FIG.
SF3° Sampled and held by SF3.

The input signal ID is a negative polarity R as shown by diagonal lines in Figure 1O.
, G, and B signals in series, the output signals of the sample/hold circuits 81a-81c are inverting amplifiers 82a-82c.
As shown in FIG. 10, the positive polarity RO
, Go.

BO times signal is obtained. The RO, GO, and BO multiplied signals are applied to white balance circuits 83a to 83c, respectively, and amplitude correction is performed in consideration of the illumination light at the time of photographing to obtain the R1, Gl, and Bl signals shown in FIG. These color signals are applied to conventional liquid crystal displays. R1,G
l.

When a CRT display is used to reproduce still images, the Bl signals are sent to gamma correction circuits 848-84, respectively.
Output signals R2, G2 that are input to c and subjected to gamma correction
Obtain °B2. If the monitor 30 is a CRT display, the monitor includes R2, G2. B2 signal should be applied.

The R2, G2.82 signals are applied to mixer 27c shown in FIG. This mixer is an analog switch 91a -
91c. These analog switches are the first
It is switched by sequential switching pulses 501-5D3 shown in FIG. 0 to produce an output signal DI sequentially containing R, G, and B signal components as shown in FIG. Drive circuit 25
is the A/D sample clock CPS to the A/D converter 28.
A digital output signal DO containing R, G, and B component digital data DoR, DoG, and DoB in series as shown in FIG. 10 is generated.

A well-known liquid crystal display can be used as the liquid crystal monitor 30, and the configuration of this display is shown in FIG.
This will be explained in detail with reference to B). This liquid crystal display has an active matrix type liquid crystal display plate 110.

In this display, pixels are arranged in a matrix. A sample/hold circuit 111 and a vertical drive circuit 112 are used to drive each pixel of the liquid crystal display.
is provided. The output signals RD, GO, BD from the processing circuit 27b and the sample clock CPD horizontal synchronization signal H from the drive circuit 25 are applied to the sample/hold circuit 111. The vertical drive circuit 112 includes a drive circuit 2
FIG. 11(B) to which the horizontal synchronizing signal H and the vertical synchronizing signal V are applied from 5 to 5 shows the configuration of each pixel of the liquid crystal display. RD and GD from sample/hold circuit 111
, the corresponding color signal of the BD double signal is MOS)-
A timing pulse is applied to the drain of the transistor 113, and a timing pulse from the vertical drive circuit 112 is applied to the gate of the transistor 113. When the transistor 113 is turned on by a timing pulse, a color signal corresponding to the capacitor f114 of the liquid crystal 115 corresponding to each pixel connected to the source of the transistor is written.

Referring to FIG. 12, the structure of a semiconductor memory card 15, which is one of the features of the present invention, is shown. Memory cards can be easily manufactured using existing card-type electronic device manufacturing techniques. In the illustrated example, 24 256 Kbit static RAM chips 32. -32.4 is placed. RAM
As a chip, a Toshiba TC55257 chip can be used. The 24 RAM chips are used to capture two frames of still images. The RAM chips 32□-32□2 are used for recording image information of the first still image, and the RAM chips 3213-3224 are used for recording image information of the second still image. Furthermore, RAM chips 321-32. ;3
21. -32. , for recording image information of odd fields, and RAM chip 32. -32□, ;321. −
322. is applied to recording even field image information.

12 256Kbits to record one frame of still image
The reason why this RAM chip is necessary is as follows. C.C.
If the D array has 768 horizontally x 491 vertically valid pixels, and 8 bits are allocated to the signal per pixel, the video signal representing one frame of still image has 3.017
Mbitg is required. It is obvious that twelve 256Kbit RAM chips are required to record this amount of data.For example, if you use a large capacity RAM chip of 4 Mbits, you can record a larger number of still images. It is clear that it can be done.

An 8-bit data terminal 32 is located at the end of the memory card 15.
Address terminal 32 receiving address information AO-A18
3. A control terminal 323 and a power supply terminal 33 are formed.

A power switching circuit unit 35 shown in FIG. 4(A) is provided between the power terminal 33 and the battery 34 built into the memory card. The data terminal is commonly used for RAM chip 32□-3
28, is coupled to the data terminal of . The address terminal of AO-A14 is the RAM chip 32. -322. are commonly coupled to the address terminals of.

Address decoders 12ii and 12□2, which are used to select RAM chips, are connected to the address terminals of A15-Alg. Toshiba decoder 7 as address decoder
48C154 can be used. Address decoder 12□1
12 R in response to address information A15-A18
One of the AM chips 32□-32□2 is selected, while the address decoder 12□2 selects one of the RAM chips 32□3-322.
Select one of 4. Which of address decoders 1211 and 121□ is enabled is determined by the logic level of chip select signal C8 supplied from drive circuit 25. The drive circuit 25 sends a write signal WP and a card enable signal C to the RAM chip in common.
B is applied. That is, when the memory card is loaded into the camera, the RAM chip is enabled by the card enable signal CE, and is put into a write state by the write signal 11P generated in the still image mode.

Referring to FIG. 13, the configuration of the address generation circuit provided in the drive circuit 25 is shown. The address generation circuit is the first
and second counters 131 and 132, a flip-flop circuit 133, and an up/down counter 134. The first counter 131 is cleared by a synchronization signal H2 having the same frequency as the horizontal synchronization signal H1, and counts the clock CPU having the same frequency as the CCD driving clock applied to its clock terminal, and collects address information AO in the horizontal direction. - Generate A9. The second counter 132 is cleared by a synchronization signal v2 having the same frequency as the vertical synchronization signal v1, and counts the synchronization signal H2 that clears the first counter 131 to generate vertical address information Al0-A17.

Flip-flop 133 is cleared by write pulse ttp and clocked by vertical synchronization signal 2. Flip-flop 133 outputs address information A from its output Q.
Outputs 1g. Address information A1g is the first and second
Identify the field. Address information A18 is used to select the upper half group or the lower half group of the 12 RAM chips.
The n counter 134 is cleared by a clear pulse CLP generated when the memory card is loaded into the camera.
It is counted up by the write pulse vP generated in the still image mode, and counted down by the retake pulse generated by operating the retake button 12. As shown in FIG. 12, when the memory card 15 is used to take two still images, the counter 134 may be a binary counter.
A picture select) signal C5 is generated. By operating the reshoot button, the counter 134 is counted down and the same still image can be rerecorded on the same RAM chip.

Figure 14 shows the correspondence between the pixel arrangement of the CCD array and the address space on the memory card. H) X491(V) is used as an effective pixel area. Other pixel areas indicated by diagonal lines are optical black areas. Pixel data is recorded on the memory card in an order according to the arrangement of pixels in the effective pixel area. In order to store the pixel information of one frame in an integer multiple of 256Kbits to make effective use of the memory, and to simplify the configuration of the address generation circuit, the recording area of the memory card is 768 (H) x 512 (V). is set to The address information AO-A9 generated by the address generation circuit described above is stored in 768 horizontal rows (colu) of the memory card.
mn). Address information Al0-A17
selects one of the 512 vertical rows of the memory card. Address information AO-A17 corresponds to one frame of image. In the area of the memory card where image information is not recorded, photographing data such as date and shutter speed supplied from the data recording circuit 29 can be recorded. For this purpose, the output of the data recording circuit 29 and the output of the A/D converter 29 are coupled to the memory card 15 via a selector.
The selector is then controlled by the address signal. That is, when the address signal specifies the image recording area of the memory card, the selector selects the output of the A/D converter from the memory card 15.
controlled to bind to.

After the specified number of still images have been recorded, or in order to play back the recorded still images, the memory card 15 is transferred to the camera 10.
be extracted from. The image information stored in the RAM chip is stored by a battery 34 built into the memory card.

In order to play back still images recorded on the memory card 15, a dedicated playback device (electronic album) is used.

Referring to FIG. 15, a schematic structure of the electronic album is shown.

Once the memory card 15 is loaded into the regenerator 150, which has a memory card acceptance mechanism similar to a camera.

As in the case of a camera, voltage is supplied from a power supply (not shown) of the regenerator. The drive circuit 151 supplies a readout signal and an address signal to the memory card 15, and as a result, image information signals are sequentially read out from the memory card 15 for each pixel. The read image information signal is subjected to appropriate signal processing in a signal processing circuit 152, and then D/
The A converter 153 converts it into an analog signal. Analog format R, G, and B signals are sent to a CRT monitor 15 with R, G, and B terminals along with synchronizing signals from a drive circuit 151.
4, and the captured still image is displayed on the CRT screen. The regenerator 151 is an optical disk unit 155
The optical disc unit may also include a drive circuit 151 to transfer digital data output from the memory card 15 to the optical disc 1 in response to an optical disc control signal from the drive circuit 151.
55a. Further, if necessary, a print printing device 156 can be provided to output a hard copy of a still image.

FIG. 16 shows the signal processing circuit 152 of FIG. 15 in particular detail. The image information signal from the memory card 15 is R,
Output is in the order of G and B. R read out in series,
The G and B signals are sent to the latch circuit 161a by sequential latch control signals output from the drive circuit 151.

161b and 161c are sequentially latched, resulting in R and G.

The B signal is separated. These R, G, and B signals are stored in independent memories 162a, 162b, and 162c, respectively, and then all data of each of the R, G, and B signals that make up one still image is stored in the corresponding memory. be done.

Memories 162a, 162b, 162c are drive circuit 5
The read mode is set from 1. R, G read from memories 162a, L62b, 162c in response to a read clock.

The B signals are sent to D/A converters 153a, 153b, respectively.
153c, and outputs R, G, and B signals in analog format for application to the CRT monitor 154.

Next, the photographing method of the electronic camera of the present invention will be described with reference to FIGS. 17 and 18. In particular, FIG. 17 shows the drive circuit 2.
5 in detail, and FIG. 18 shows a timing chart for explaining the operation of the camera photographing method.

When the release 11 is pressed halfway to take a still image, power supply voltage is supplied from the power supply circuit to each circuit. The crystal controlled oscillator 171 generates 4XfSC (approximately 14.38Hz; f
The SC generates clock pulses at a frequency of 3.58 MHz (color subcarrier frequency). The frequency of this 4XfSC is determined by the frequency of the divider 172 connected to the 6 oscillator 171, which is necessary to display a moving image by driving the CCD array 26 of 800 x 500 pixels in real time (one frame is 1/605 ecan). An output clock pulse CP is provided to a signal generator 173. The frequency divider is set to a division ratio of 1 in video mode. The signal generator 173 generates a vertical synchronizing signal Vl (60 Hz), a horizontal synchronizing signal old (15,75 KHz), a field shift pulse FSP, and a clock for IMH2 for sweeping out charges in the CCD array in synchronization with the clock pulse CP. Field shift pulse FSP is generated in synchronization with the vertical synchronization signal.

The signal generator 173 also generates Vl, a synchronization signal V2°H2, etc. which is out of phase with the old one.

The frequency division ratio N of the frequency divider 172 is set to 1 in the video mode, so that the CCD 26 is driven in real time to output video image information. As will be described later, in the still image mode, the frequency division ratio is set to 2, whereby the frequencies of the clock pulse CP and various synchronization signals generated by the signal generator 173 are halved. As a result, CCD
The read speed of image information signals from array 26 is halved, allowing AID conversion and writing of image information to the memory card to occur at a slower speed.

The signal generator 173 outputs the vertical synchronization signal v1, the old horizontal synchronization signal, and the field shift pulse FSP to the vertical driver 77.
4 to generate a four-phase vertical transfer pulse φV.

The vertical transfer pulse φV has a train of 250 15.75 KHz pulses corresponding to 250 stages of the vertical transfer section of the CCD array 26 within one cycle of the vertical synchronizing signal v1. The field shift pulse FSP is superimposed on the first phase vertical transfer pulse φ■ in synchronization with the vertical synchronization pulse.

The signal generator 173 supplies the clock pulse CP and the horizontal synchronization signal H1 to the horizontal driver 175 to generate a two-phase horizontal transfer pulse φH. Horizontal transfer pulse φ! 1 is 4Xf
It is generated by gating the clock signal CP at the frequency of SC with a horizontal sync signal. That is, horizontal transfer pulse φH has the same frequency as clock signal CP.

After the release 11 is pressed halfway, the vertical transfer pulse φV and the horizontal transfer pulse φH generated by the vertical driver 174 and the horizontal driver 175 cause the C
The CD array 26 is driven to output a video information signal 601 (z).
7b, it is processed as described above and outputs R, G, and B signals. The R, G, and B signals are applied to a monitor (viewfinder) 30 of the camera to display a moving image of the subject.

The cameraman determines the angle of view while looking at the monitor, and if necessary, after focusing, he presses the release 11 all the way. Then, the shutter control circuit 24 responds to this by issuing a shutter pulse S.
The shutter control circuit 24 that generates TP includes a signal generator 1.
A vertical synchronizing signal v2 and a horizontal synchronizing signal H2 are applied from 73. As shown in FIG. 18, the shutter pulse ST
P is generated in synchronization with the first vertical synchronization signal i81 after the release 11 is fully pressed. At the same time, a field shift pulse 182 is generated. The pulse width tνl of the shutter pulse STP defines the electronic shutter time of the CCD array 26, and the pulse interval (63, 5
μsec). Shutter pulse S
TP is applied to the signal generator 173, which generates the field shift pulse 183 in response to the falling edge of the shutter pulse STP.

A field shift pulse 184 is generated in synchronization with the first vertical synchronization signal after the fall of the shutter pulse STP. The time interval between field shift pulses 183 and 184 is the electronic shutter time of the CCD array. The charges accumulated in the CCD array 26 during this shutter time are extracted as still image information. field shift pulse 1
Since the time interval between 82 and 184 is equal to one period (16.67 nsec) of the vertical synchronization signal, the shutter time is expressed as 16.67-twl m5ec.

For example, since twl is set to an integral multiple of the period of the horizontal synchronization signal, tvl=230 x 63.5 p see
In this case, the shutter time corresponds to approximately 2 m5ec, and the shutter speed corresponds to approximately 1/500. The time length ttzl of the shutter pulse STP is defined by the shutter control circuit 24 based on the setting value of the shutter dial.

The shutter control circuit 24 generates the division ratio switching pulse SwP and the write pulse VP in synchronization with the first vertical synchronization signal or field shift pulse 184 after the release 11 is fully pressed.The division ratio switching pulse SvP is gated. The frequency divider 1728 is applied through the frequency divider 176, thereby switching the frequency division ratio of the frequency divider 172 to 2. As a result, the frequency of the clock CP applied to the signal generator 173 is 4.
Switching from Xfsc to fsc, the frequency of the synchronization signal generated by the signal generator 173 is reduced by half.

Still image information is read out from the CCD array 26 at a low speed,
After being processed in the signal processing circuit 27 as described above, it is applied to the A/D converter 28. A/D clock generation circuit 177
is provided, which is clocked by write pulse vP
gating p A/D conversion clock cps
is supplied to the A/D converter 28. Address generation circuit 17
8 is constructed as shown in FIG. clock CP
.

Since the frequencies of the vertical synchronization signal V and the horizontal synchronization signal H are reduced by half, image information of still images is written to the memory card at a low speed. Write time, i.e. switching pulse SvP
The duration of the write pulse tp is set to four times the period of the vertical synchronization signal in the normal state.

Next, the discharge of charges in the CCD array 26 will be described. As shown in FIG. 18, the shutter pulse ST
A field shift pulse 182 is generated in synchronization with the rising edge of P.
is generated. As a result, the charges accumulated in each pixel of the CCD array 26 are transferred to the corresponding vertical transfer section. For example, the vertical transfer pulse φV (185) following the field shift pulse 182 is performed at a high speed 1 several tens of times higher than usual.
Set to IMHz. As a result, unnecessary charges are quickly swept out within time tl.

Since the vertical transfer section 62 has 250 stages, the time t1 required for sweeping out is 250 μsec. Sweeping out unnecessary charges means not using the charges read out from the horizontal transfer section. As described above, field shift pulse 183 is generated in synchronization with the falling edge of shutter pulse STP. The unnecessary charge accumulated in each pixel between field shift pulses 182 and 183 is removed by vertical transfer pulse φV.
(186), it is swept out just before the field shift pulse 184 is generated. To sweep out unnecessary charges, apply a vertical transfer pulse φV of 15.75KH at a predetermined timing.
This can be easily done by switching from z to IMHz.

Next, strobe photography will be explained.

The shutter control circuit 24 generates a strobe trigger pulse 187 immediately after the fall of the shutter pulse STP, as shown in FIG. In response to a strobe trigger pulse, an electronic flash mounted on the camera's hot shoe emits a powerful flash of light. At this time, the vertical transfer section 6 of the CCD array 26 is
Light leaks into 2. Therefore, unnecessary charges are accumulated in the vertical transfer section 26. This unnecessary charge is removed by sweeping out the charge by the vertical transfer pulse 186. In the camera of this example, the flash light emission time is 50 μm.
With SOC, strobe synchronized photography is possible up to a shutter speed of approximately 1/3000 seconds.

The configuration of the shutter control circuit 24 will be described with reference to FIG. 19.

As shown in FIG. 18, when the release 11 is pressed halfway, an "H" level control signal S1 is output until the release is released, and this is applied to the inhibit terminal of the flip-flop 191 in FIG. As a result, the inhibited state of the flip-flop 191 is released.

Subsequently, when the release 11 is fully pressed, the "H" level control signal S2 is output. This is flip flop 191
is applied to the set terminal S2 of the flip-flop 191
Set. As a result, a control pulse F is output from the terminal Q of the flip-flop 191. The control pulse F enables the NO gate 192. Vertical synchronization signal v2 is sent to ternary counter 1 via AND gate 192.
93 clock terminal. Vertical synchronization signal v2 is applied to latch circuit 198 via AND gate 194, which is enabled by control signal F, and is latched. As a result, the latch circuit 198 becomes high 1eve.
1 shutter pulse STP is generated. It is clear that the rise of the shutter pulse STP is synchronized with the first vertical synchronization pulse after the release is fully pressed. This first vertical synchronization signal is generated by the shutter dial which clears the counter 195 that counts the horizontal synchronization signal H2. Digital data regarding the set shutter speed is latched into latch circuit 196, which is coupled to comparator 197.

A count output of a counter 195 for counting horizontal synchronization signals is coupled to this comparator 197. The comparator 197 is
When a match is detected between the contents of the latch circuit 196 and the counter 195, the latch circuit 19a is cleared. As a result, the shutter pulse STP becomes RL'', the shutter pulse S
It is understood that the pulse width of TP is an integer multiple of the horizontal synchronization signal interval.

The ternary counter 193 outputs Ql, Q2. Q3, the output Q3 of which is coupled to the reset input H of the counter 191.

Therefore, as shown in FIG. 20, after the control signal F is generated, in other words, after the release is fully pressed, the reset is performed by the fourth vertical synchronizing signal.

The output Q2 of the counter 193 can be used as the frequency division ratio switching pulse SP and the write pulse vP.

As shown in FIG. 17, a test switch 179 is provided, which allows the division ratio switching signal to be applied to the gate 17 as necessary.
6 to the frequency divider 172,
This makes it possible to adjust the timing of the AID converter and memory by switching the frequency of the clock pulse during camera assembly or adjustment.

In the embodiments described so far, the image displayed on the finder is a moving image regardless of the shutter speed, and it is also possible to take a picture while checking the shutter speed and aperture. A timing chart of this embodiment will be explained with reference to FIG. The difference between this embodiment and the previous embodiment is that the shutter pulse STP is generated even in the moving image mode. That is, the shutter control circuit 24 generates a shutter pulse STP in response to the release signal S1. At the same time, the signal generation circuit 173 generates a field shift pulse FSP in response to the falling edge of the shutter pulse STP and also generates a high-speed sweep pulse to display an image on the finder according to the shutter speed, as in the previous embodiment. let

As is clear from the timing chart in Figure 2, unnecessary charges accumulated during the period of the shutter pulse STP (corresponding to the shutter speed) are swept away by the high-speed vertical transfer pulse φV just before the next shutter pulse. , and the charge accumulated from the fall of the shutter pulse to the rise of the next shutter pulse is read out, and based on this read charge, <R.

G and B signals are supplied to the finder. This results in
In video mode, images are displayed according to the shutter speed. This embodiment also operates in the same way as the previous embodiment after the release is fully pressed.

The embodiments described so far use an interline transfer type solid-state imaging device having the configuration shown in FIG. The current television standard system uses an interlaced system, so frame images are displayed at 1/30 seconds. Therefore, the number of stages of the vertical transfer section may be 250, which is half the number of pixels (500) in each column. Therefore, when the solid-state image sensor described above is used, a still image of a field image with half the vertical resolution can be obtained. A frame image can be formed by using a solid-state image sensor in which the number of stages of vertical transfer sections is equal to the number of pixels in each column.

A camera using a frame interline type CCD array to form frame images will be described below.

FIG. 22 shows an example of a frame interline type CCD. In this image sensor, pixels 221 each consisting of a photoelectric conversion element such as a photodiode are arranged two-dimensionally.

250 stages of vertical transfer sections 222 adjacent to pixels in each column
is provided, and the charge of each pixel is transferred to the corresponding vertical transfer section 222 by the field shift pulse, and then transferred to the charge storage section (frame memo 224) via the transfer gate 223.The signal charge of the storage section 224 is extracted as an electrical signal from the output circuit 226 via the horizontal transfer section 225.

There is an overflow section at the other end of the vertical transfer section.
drain) 227 is provided.

This CCD array has 800 columns x 50
It consists of 0rovs pixels, and each charge storage section 624
has a capacity to accumulate the charges of all pixels in the corresponding column.

The photographing operation of the camera using this image sensor will be explained with reference to the timing chart of FIG. 23.

When the receiver 11 is pressed halfway and the release signal St is output, the power circuit is turned on and the drive circuit 25 generates various pulses to drive the CCD array 26. The clock frequency supplied to the signal generator 173 at this time is 4Xfs
c, so the frequency of the vertical synchronization signal is 60) 1z
The frequency of the horizontal synchronizing signal is 15.75 KHz.

Also in this embodiment, a shutter pulse STP is generated in synchronization with the vertical synchronizing signal in the moving image mode, and falls after a time corresponding to the shutter speed has elapsed. A field shift pulse is generated in synchronization with the fall of the shutter pulse STP. In this embodiment, a field shift pulse FSP1 is used to read out the charges of pixels in odd numbered columns of the CCD array to the vertical transfer section, and a field shift pulse FTP is used to read out the charges of pixels in even numbered columns to the vertical transfer section.
2 is generated as shown.

A field pulse FSPI (231) is generated in synchronization with the falling edge of the shutter pulse STP, and the charges of pixels in odd-numbered columns are read out to the vertical transfer section. After a certain period of time, a vertical transfer pulse φVl (232) is generated and Charges in the transfer section are drained to the overflow drain 227.

If the frequency of the vertical transfer pulse φv1 at this time is, for example, 64 times the frequency of the horizontal synchronizing signal, approximately IM)12, the time t1 required for sweeping out is approximately 250 μsec (
The number of stages of the vertical transfer unit is 250), and after the sweep is completed, the field shift pulse FSIP (233) is generated again to read out the charges of the pixels in the odd numbered columns to the vertical transfer unit. Immediately after this, the vertical transfer pulse φVl (234) and the frame memory A transfer pulse φV2 (235) is generated to sequentially transfer the charges of pixels in odd-numbered columns to the frame memory 22 via the vertical transfer unit 222.
Transfer to 4. The frequency and number of vertical transfer pulse φv1 and frame memory transfer pulse φ■2 at this time are approximately IN)lz
In this case, the transfer time t2 is approximately 250 μsec.

15.75K in synchronization with the next vertical sync pulse (236)
A vertical transfer pulse φV2 (237) of Hz is generated, and the charge of the odd-numbered column pixels is transferred from the frame memory 224 to the horizontal transfer unit 2.
27, and therefore the charge of the odd-numbered column pixel is read out from the horizontal transfer section in synchronization with the horizontal transfer pulse φH. This read time is t3. The shutter pulse 5TP (
238) rises again and then falls after a certain period of time. Field shift pulse FS is synchronized with this falling edge.
P2 (239) is generated and the charges of the pixels in the even numbered columns are read out to the vertical transfer section.After a certain period of time, the vertical transfer section transfers to approximately IM.
Driven by the Hz vertical transfer pulse φVl (24), charges of pixels in even columns are swept to the overflow drain 227. After the sweep is completed, a field shift pulse FSP2 (24
1) is generated again and the charge of the pixels in the even numbered columns is read out to the vertical transfer section, and as in the case of the charge of the pixels in the odd numbered columns, the vertical transfer pulse φVl (242) and the frame memory transfer pulse φV2 (243) are used. Frame memory 224
Transfer to.

15.75K in synchronization with the next vertical sync pulse (244)
A frame memory transfer pulse φV2 (245) of Hz is generated to read out the charges of pixels in even columns from the frame memory to the horizontal transfer section.In this way, in the movie mode, image information of odd and even fields is transferred horizontally to the composition. Read from the transfer unit. One frame of video is displayed in the finder.

Now, after checking the angle of view, shutter speed, focus, etc.
When the release 11 is fully pressed, a release signal S2 is output. In synchronization with the release signal S2, a control pulse F is generated as in the previous embodiment.

A shutter pulse 5TP (241) is generated in synchronization with the first vertical synchronization pulse (244) after this. Let the pulse width of this shutter pulse be tw2. In synchronization with the falling edge of this pulse, field shift pulse FSPi (
247) is generated and the charges of the pixels in the odd numbered columns are read out to the vertical transfer section. The field shift pulse FSP2 (24
g) is generated and the charges of the pixels in the even numbered columns are read out to the vertical transfer section. After a certain period of time, a vertical transfer pulse φVl (249) is generated.
is supplied to the vertical transfer section, and the charges of the pixels in the odd and even columns read out first are swept out to the overflow drain 227. After that, the field shift pulse FSPI (250) is generated, and the charges of the pixels in the odd columns are sent to the vertical transfer section. reading,
Subsequently, a high-speed vertical transfer pulse φVl (251) and a frame memory transfer pulse φv2 (252) are generated to transfer the charges of odd-numbered column pixels to the frame memory 224. Approximately 250 μs from generation of field shift pulse FSP 1
After ec, the field shift pulse FSP2 (253) is generated again to read out the bridges of the pixels in the even numbered columns to the vertical transfer section, and then the pixels in the even numbered columns are read out by the vertical transfer pulse φVl (254) and the frame memory transfer pulse φV2 (255). charge is transferred to frame memory 224.

The pulse width tν2 of the shutter pulse STP at this time is
tv2=16.67+*5ac-(tl+2t2)-shutter time. Shutter time 2m5ac, tc
Since t2=250 μsec, tw2=13.92
m5ec, which is approximately 219 times the pulse width of the horizontal synchronization pulse.
It's double.

As described above, after the charges of all pixels are transferred to the frame memory 224, the division ratio switching pulse SwP is generated in synchronization with the vertical synchronization signal 256. As a result, as in the previous embodiment, the frequencies of the various signals generated by the signal generator 173 are halved, and as a result, the frame memory 224
The pixel charges accumulated in
2, and is read out from the horizontal transfer section 225 by a low-speed horizontal transfer pulse φH.

An example of changing the still image playback device will be described below.

For TV monitors that do not have R, G, and B terminals, the second
It is possible to use the playback device shown in FIG. That is, the image signal read from the memory card 15 is sent to the separation circuit 3.
After the signals are separated into R, G, and B signals by 01, they are combined into Y, RY, and BY signals by a matrix calculation circuit 302. These equal signal D/A converters 303a-303c
Each signal is converted into an analog signal and applied to the monitor.

Furthermore, as shown in FIG. 25, the R-Y signal, B-Y
The digital N750 circuit 304 modulates the signal with a color sub-transmission wave, and then the D/A converter 305 converts it into an analog signal, adds a synchronization signal, outputs it as a decoded video signal, and applies it to a TV receiver. It is also possible.

In the above-mentioned embodiment, the image information signals from the CCD array 26 were recorded on the memory card in the order of output, but as shown in FIG. 26, it is possible to divide the memory area for each color data and record the image information signals. You can also do it.

This makes the regeneration circuit simpler. This figure shows an area for recording data such as the shooting date and shutter speed. This data area corresponds to the area of the memory card shown in FIG. 14 where no image data is recorded.

〔Effect of the invention〕

According to the present invention, it is possible to provide an electronic camera that can be configured without using a drive device and is easy to use.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of an electronic still camera according to an embodiment of the present invention, FIG. 2 is a diagram showing a schematic configuration of the camera of FIG. 1, and FIG. 3 is a semiconductor memory used in the camera of the present invention. Figure 4 is a diagram for explaining the basic configuration of the card, Figure 4 is a diagram showing an example of the power switching circuit incorporated in the semiconductor memory card, and Figure 5 is the power switching circuit when the semiconductor memory card is loaded into the camera. 6 is a diagram showing an example of the solid-state imaging device used in the electronic camera of the present invention. FIG. 7 is a diagram showing the configuration of the signal processing circuit in FIG. 2. 9 shows the configuration of the processing circuit in FIG. 7, FIG. 9 shows the configuration of the mixing circuit in FIG. 7, and FIG.
Figure 7 is a diagram showing a timing chart for explaining the operation of the processing circuit, Figure 11 (A) is a diagram showing the configuration of a viewfinder built into the camera, and Figure 11 (B) is a diagram showing a timing chart for explaining the operation of the processing circuit.
is a diagram showing the configuration of one pixel in FIG. 11(A), FIG. 12 is a diagram showing an embodiment of the semiconductor memory card used in the electronic camera of the present invention, and FIG. 13 is a diagram showing the address provided in the drive circuit. FIG. 14 is a diagram showing the configuration of the generation circuit, FIG. 14 is a diagram showing the relationship between the pixels of the CCD array and the address space of the semiconductor memory card, and FIG. 15 is the configuration of an electronic album that plays back still images recorded on the semiconductor memory card. FIG. 16 is a diagram showing the configuration of the signal processing circuit in FIG. 15, FIG. 17 is a diagram specifically showing the configuration of the drive circuit, and FIG. 18 explains the operation of an example of the electronic camera of the present invention. 19 is a diagram showing the configuration of the shutter control circuit, FIG. 20 is a diagram showing a timing chart for explaining the operation of the shutter control circuit shown in FIG. 19, and FIG. 21 is a diagram showing a timing chart for explaining the operation of the shutter control circuit shown in FIG. 22 is a diagram showing a timing chart explaining another example of the operation of the electronic camera of the present invention, and FIG. 22 is a CCD solid-state imaging device applied to take a one-frame still image consisting of images of an odd field and an even field. FIG. 23 is a diagram showing a timing chart for explaining the operation of the electronic camera of the present invention when the solid-state imaging device of FIG. 22 is used, and FIGS.
This figure shows an example of a modification of the reproducing device, and FIG. 26 is a diagram showing another example of the method of recording image information signals on a memory card. Agent Patent Attorney Noriyuki Ken Yudo Mitsuyuki Matsuyama Figure 1 Figure 2 Figure 4 Tip Figure 5 Figure 6
17 de・ノ [SF) / 5D2Si) 3 Fig. 9 Fig. l πB Fig. 20-N Sariri l 1 Takujoki Tomo I] 4 Fig. 25 Fig. 26

Claims (3)

[Claims] (1) A memory card with a built-in back battery for storing image information is used as a storage medium, and a solid-state image sensor photoelectrically converts the captured image, and the analog signal output from this solid-state image sensor is digitized. an analog-to-digital conversion element, power supply means for driving the analog-to-digital conversion element and the solid-state image sensor, and means for detecting attachment/detachment of the memory card, and supplying the power when the memory card is attached. An electronic camera, characterized in that means are used to store image information on the memory card. (2) The electronic camera according to claim 1, wherein the power supply means is a battery. (3) Claim 1 or 2, characterized in that a power supply means is independently provided to hold image information of the memory card when the memory card is installed.
Electronic camera as described in section.