JP3193558B2 - Video signal recording and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for recording a video signal of a still image in a high-definition mode output from a high-resolution imaging apparatus on a recording medium in a standard mode and reproducing the same.

[0002]

2. Description of the Related Art Conventionally, as an electronic still video apparatus, an apparatus for recording a video signal in a high-definition mode such as Hi-Vision on a recording medium as a video signal in a standard mode such as the NTCS system has been known (Japanese Patent Laid-Open No. 5-30461). Gazette). This recording apparatus is configured to temporarily store a high-definition mode video signal in a frame memory, divide one screen into a plurality of portions, and record the divided portions on a plurality of tracks of a recording medium. Is performed at a high drive frequency corresponding to the high definition mode, and the recording operation on the recording medium is
It is performed at a low drive frequency corresponding to the standard mode.

[0003]

As described above, when data is stored in the memory, the memory and its peripheral circuits must be driven at a high speed. Therefore, it is necessary to use an expensive circuit corresponding to the high-speed drive as the memory. In addition, there is a problem that power consumption is increased.

An object of the present invention is to provide a video signal recording apparatus which does not require a frame memory to record a video signal in a high definition mode on a recording medium in a standard mode. It is an object.

[0005]

According to the present invention, there is provided a video signal recording apparatus comprising: an image pickup means for generating, transferring, and outputting a pixel signal in a high definition mode to the outside; and a transfer operation of the pixel signal in the image pickup means. Generating means capable of outputting a transfer clock at a low frequency corresponding to the standard mode, a memory for temporarily storing pixel signals output from the imaging means, and an operation for writing and reading pixel signals to and from the memory And a means for writing a pixel signal read from the memory to a recording medium, wherein the memory is configured to output an odd-numbered horizontal scanning line among the respective horizontal scanning lines forming an image captured by the imaging device. A first memory unit for storing the first half, a second memory unit for storing the second half of the odd-numbered horizontal scanning lines, and a second memory unit for storing the first half of the even-numbered horizontal scanning lines. Consists of a fourth memory unit for storing a memory unit, the second half of this even-numbered horizontal scanning lines,
The pixel signal at the center of each horizontal scanning line is stored redundantly in the first to fourth memory units.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIGS. 1 and 2 show a video signal recording apparatus according to an embodiment of the present invention. This apparatus converts a high-quality still image obtained in a high-definition mode such as a high-definition mode into an NTS image.
It is recorded on a magnetic disk according to a standard mode such as the C system.

Referring to FIG. 1, an image pickup unit 10 of an image pickup apparatus
Are provided with, for example, about 2 million photodiodes 11 arranged regularly in the vertical and horizontal directions. Each photodiode 11 corresponds to each pixel, and the optical information detected by each photodiode 11 is converted into an electric signal, which is output from an imaging device via a vertical transfer CCD 12 and a horizontal transfer CCD 13 as described later. You. In the figure, the lower side of the imaging unit 10 corresponds to the upper side of the screen of the display device (not shown), and the upper side of the imaging unit 10 corresponds to the lower side of the screen.

In FIG. 1, a vertical transfer CCD 12 is formed beside each column of photodiodes 11 extending vertically. That is, a plurality of vertical transfer CCDs 12 are provided in parallel with each other.
The output signal (pixel signal) is transferred to the vertical transfer CCD 12 adjacent thereto and transferred to the horizontal transfer CCD 13 via the vertical transfer CCD 12. The transfer operation in the vertical transfer CCD 12 is performed by vertical transfer clock signals φV1 to φV4 applied to the imaging unit 10.

The horizontal transfer CCD 13 is connected to the vertical transfer CCD 12 via the transfer gate 15, and the opening / closing operation of the transfer gate 15, that is, the transfer operation of the pixel signal from each vertical transfer CCD 12 to the horizontal transfer CCD 13 is performed by the transfer gate signal. Controlled by φT.

The transfer operation in the horizontal transfer CCD 13 is as follows.
It is controlled by horizontal transfer clock signals φH1 and φH2. The pixel signal output from the horizontal transfer CCD 13 is amplified by the output amplifier 31 and supplied to the signal processing circuit shown in FIG.

Vertical transfer clock signals φV1 to φV4, transfer gate signal φT, horizontal transfer clock signals φH1, φH
The drive frequency of No. 2 is switched to a high frequency (74.25 MHz) when a moving image is monitored on the display device (during a monitor operation), when a video signal is recorded on a magnetic disk (during a recording operation), and when a low frequency (18.614 Hz) is used. ). As the value of the low frequency, for example, a value of (4fsc × (Nh / 2) / Nn) or more is selected where fsc is the frequency of the subcarrier of the NTSC system (standard mode) which is a standard television system. Here, Nh is the number of horizontal effective pixels of the image sensor, and Nn is the number of horizontal effective pixels of the image in the standard mode. (Nh / 2) / Nn in consideration of simplification of the circuit configuration.
, And the low frequency value is obtained from a simple integer ratio relatively close to it. In this example, it is obtained from a ratio of 13/10. The high-frequency signal is output from the high-definition synchronization signal generator 21.
The low frequency signal is generated by the oscillator of the standard synchronization signal generator 22 and the switch 23
The high-frequency or low-frequency signal is output from the CCD clock generator 24 in accordance with the switching state.

The output end of the horizontal transfer CCD 13 is connected to a reset drain 17 for sweeping out signal charges that have already been read. The signal charge sweeping operation of the reset drain 17 is performed by the drive signal φRG after the output of the signal charge from the horizontal transfer CCD 13 is completed.

Note that a smear drain 19 is provided to sweep out unnecessary charges accumulated in the horizontal transfer CCD 13 at once. The operation of sweeping out the smear drain 19 is controlled by the drive signal φSMG, and the vertical transfer CCD 12
This is performed before the pixel signal of the next horizontal scanning line is transferred to the horizontal transfer CCD 13 from.

Referring to FIG. 2, a description will be given of a configuration for performing predetermined processing on a pixel signal output from an imaging device, monitoring the moving image with a display device (not shown), or recording the still image on a magnetic disk D. I do.

The pixel signal output from the output amplifier 31 is subjected to noise removal in a correlated double sampling circuit (CDS) 33 and input to a low-pass filter 35 and a camera process circuit 37. In the camera process circuit 37, color separation processing, gamma correction, white balance adjustment, and the like are performed in accordance with the high-speed clock signal output from the clock generator 24, whereby the luminance signal (Y) and the color difference The signal (Pr, Pb) is obtained. These signals (Y, Pr, Pb) are output during the monitor operation.
The signal is directly output to the display device through the mute circuit 38. On the other hand, during the recording operation, the mute circuit 3
At 8, a signal (Y, Pr, Pb) is output to the display device, for example, so that the entire screen becomes blue.

The color temperature detector 41 detects the color temperature of the subject, and the color temperature information is converted into data used for white balance adjustment (color temperature correction processing) in the system control circuit 42. . The color temperature data is directly input from the system control circuit 42 to the camera process circuit 37 during the monitor operation. The color temperature data is output from the system control circuit 42 as ID data together with various information such as a track number during the recording operation, and is input to the DPSK modulation circuit 51. This ID data is DPSK-modulated by the DPSK modulation circuit 51 and input to the addition circuit 53. The color temperature data included in the ID data will be described later in detail.

At the time of the recording operation, the pixel signal output from the CDS 33 is subjected to A / D conversion in the A / D converter 64 after high-frequency components are removed by the low-pass filter 35, and is temporarily stored in the memory 65. You. This memory 65
Is composed of first to fourth memory units 65a to 65d, and each of the memory units 65a to 65d has a storage capacity enough to store half a pixel signal of one horizontal scanning line and, for example, two pixel signals. ing. Each of the memory units 65a to 65d includes
The signal is input to the D / A converter 87 via the third switches 84 to 86. The write and read operations to the first to fourth memory units 65a to 65d are controlled by a memory control circuit 66 that operates based on a command from the system control circuit 42,
The switching operation of the first to third switches 84 to 86 is controlled by the system control circuit 42.

The pixel signal converted into an analog signal by the D / A converter 87 is input to a blanking circuit 43, and a blanking period is provided between each horizontal scanning period including a large number of pixel signals. In the synchronization signal adding circuit 45, a vertical synchronization signal is added during a vertical blanking period,
Also, a horizontal synchronization signal is added during the horizontal blanking period. The signal subjected to such processing is subjected to processing such as FM modulation in the SV recording processing circuit 55 and is input to the addition circuit 53.

In the addition circuit 53, an SV recording processing circuit 55
And the output signal from the DPSK modulation circuit 51 are superimposed on each other, and the resulting video signal and I
The D code follows the still video recording method, and is recorded on the magnetic disk D via the magnetic head 57.

The magnetic disk D is rotated at a speed of, for example, 3600 rpm by a spindle motor 62 driven and controlled by a motor control circuit 61. Magnetic heads 57, 5
8 is driven by the tracking control circuit 63 and is set at a predetermined track position. The motor control circuit 61 and the tracking control circuit 63 are controlled by the system control circuit 42.

Each circuit shown in a portion surrounded by a broken line B in FIG. 2 operates according to a low-speed clock signal output from the clock generator 24.

The color temperature data included in the ID data will be described with reference to FIG. The color temperature detector 41 has three light receiving elements for detecting an R (red) component, a G (green) component, and a B (blue) component included in the light beam, and the R and G detected by each light receiving element. And outputs a R / G signal and a B / G signal as voltage signals based on the signals of the B component and the B component. The R / G signal and the B / G signal are converted into digital signals in the system control circuit 42,
It is recorded in the ID data as white balance information.
Each of the R / G signal and the B / G signal is 8-bit data, and therefore, the amount of white balance information in the ID data is 16 bits.

Next, with reference to FIG. 1 and FIGS. 4 to 8, the operation of recording pixel signals obtained by the image pickup device on the magnetic disk D will be described. FIG. 4 shows an arrangement of each pixel signal in one screen. 5 and 6 show control by a computer provided in the system control circuit 42.
8 and FIG. 8 show the storing and reading operations in the memory 65, respectively.

The pixel signals shown in FIG. 4 constitute a screen of one field, and this screen is divided at the center by a chain line C extending vertically. Pixel signals of the left half screen are represented by white circles and white triangles, and pixel signals of the right half screen are represented by black circles and black triangles. In this figure, each row extending in the left-right direction and formed by white circles and black circles, or white triangles and black triangles, respectively, corresponds to one horizontal scanning line.
Each pixel signal is obtained by two photodiodes 11 vertically adjacent to each other as shown in FIG.

One screen is divided into four parts by alternate long and short dash lines S1, S2 and S3 extending in parallel with the horizontal scanning lines, and the image of each divided part is composed of, for example, about 130 horizontal scanning lines. As described later, the pixel signal of the top divided screen is the first track, the pixel signal of the second divided screen from the top is the second track, and the pixel signal of the third divided screen is the third track, the bottom. Are recorded on the fourth track.

Referring to FIG. 5, in step 101,
The operation mode of the video signal recording apparatus is set to the recording mode, and the switch 23 of the clock generator 24 is switched to the standard mode side (the state shown by the broken line in FIG. 1). Step 10
In 2, the shutter is opened and closed in response to a release button (not shown), and an image of one screen is captured. Step 103
Then, the pixel signal is transferred from the photodiode 11 to the vertical transfer C
Transferred to CD12. In step 104, the counter N
Is set to “1”.

In step 105, the magnetic head 57
It is transferred to the truck, ie first to the first truck.

In step 106, transfer gate signal φT
Is output and the transfer gate 15 is opened.
A pixel signal for one horizontal scanning line held at a portion of each vertical transfer CCD 12 closest to the transfer gate 15 is transferred to the horizontal transfer CCD 13. After this transfer operation, the transfer gate 15 is closed. When this step 106 is executed for the first time, a pixel signal of one horizontal scanning line (a row composed of white circle pixel signals and black circle pixel signals) located in the uppermost row in FIG. 4 is transferred to the horizontal transfer CCD 13. You. The transfer operation in the vertical transfer CCD 12 is performed according to a low-speed clock signal.

In step 107, the horizontal transfer CCD 13
Are driven by a low-speed clock signal, and pixel signals of odd-numbered horizontal scanning lines are output. This pixel signal is temporarily stored in the memory 65 in step 108,
The data is read from the memory 65 and recorded on the magnetic disk D. The operation in step 108 will be described with reference to FIGS.

At the start of execution of step 108, FIG.
The first switch 84 is connected to the first memory unit 65a as shown in FIG.
The second switch 85 is switched to the third memory section 65c, and the third switch 86 is switched to the second switch side (that is, the third memory section 65c).

In this state, the first memory section 65a stores the pixel signals of the first half of the odd-numbered horizontal scanning lines and the first partial pixel signals (Q1) of the second half of the horizontal scanning lines. At the same time (W1), the pixel signal stored in the third memory unit 65c is read (R1). The read pixel signal is subjected to predetermined processing and recorded on the first track. Note that the pixel signal of the third memory unit 65c is
Although the signal is one horizontal scanning line before the pixel signal stored in the first memory unit 65a, if step 108 is executed immediately after the magnetic head 57 is moved to the first track, each memory unit still has The pixel signal is not stored, and the reading of the third memory unit 65c is not performed.

Immediately before the end of the storage operation in the first memory section 65a, the storage of the pixel signals of the second half of the odd-numbered horizontal scanning lines in the second memory 65b is started (L1). First
When the storing operation to the memory section 65a is completed, FIG.
The second switch 85 is switched to the fourth memory section 65d as shown in FIG. The second memory unit 65b stores the pixel signal of the second half of the odd-numbered horizontal scanning line and the last partial pixel signal (P1) of the first half of this horizontal scanning line (W2), and The pixel signals stored in the four memory unit 65d are read (R2), subjected to predetermined processing, and recorded on the first track. Second memory unit 65
The operation of storing data in b ends before the operation of reading data from the fourth memory unit 65d. Similar to the read operation of the third memory unit 65c, immediately after the magnetic head 57 is moved to the first track, the read of the fourth memory unit 65d is not performed.

As described above, in the operation of storing the pixel signal in the memory in step 108, the first memory unit 65a
And the second memory unit 65b stores pixel signals P1 and Q1 corresponding to the same pixel redundantly. This is the same in the storage operation of the third memory unit 65c and the fourth memory unit 65d described below.

In step 109, as in step 106, transfer gate signal φT is output and transfer gate 15
Are released, and the pixel signal of the next horizontal scanning line, that is, the even-numbered horizontal scanning line is transferred to the horizontal transfer CCD 13.
This pixel signal is supplied to the horizontal transfer CC in step 110.
It is read from D13.

In step 111, as shown in FIG. 7A, the second switch 85 switches to the third memory section 65c, and the third switch 86 switches to the first switch side (that is, the first memory section 65a). Can be In this state, the pixel signals of the first half of the even-numbered horizontal scanning lines are stored in the third memory unit 65c (W3), and the first memory unit 6
The pixel signal stored in 5a is read (R3),
A predetermined process is performed and recorded on the first track. The pixel signal of the first memory unit 65a is transmitted to the third memory unit 65c.
Is a signal one horizontal scanning line before the pixel signal stored in.

Immediately before the end of the storage operation of the third memory section 651c, the storage of the pixel signals of the latter half of the even-numbered horizontal scanning lines in the fourth memory 65d is started (L2). Third
When the storing operation to the memory unit 65c is completed, FIG.
The first switch 84 is switched to the second memory section 65b as shown in FIG. Then, the pixel signals of the latter half of the even-numbered horizontal scanning lines are stored in the fourth memory unit 65d (W4), and the pixel signals stored in the second memory unit 65b are read out (R4), and the predetermined number is read out. Is recorded on the first track of the magnetic disk D. The operation of storing data in the fourth memory unit 65d ends before the operation of reading data in the second memory unit 65b. The second memory unit 65b
Is a signal one horizontal scanning line before the pixel signal stored in the fourth memory unit 65d.

In step 112, it is determined whether or not recording of one track has been completed. In this embodiment, one screen is divided into four parts. Therefore, in this step, it is determined whether or not recording of a signal of １ ／ of one screen is completed. This determination is made by counting the horizontal synchronization signal.

If the recording of 1/4 of one screen is not completed, steps 106 to 111 are executed again, and the signal of the next horizontal scanning line is read from the image pickup device and recorded on the magnetic disk D. By repeating such an operation, the first
When 1/4 pixel signal of one screen is recorded on the track,
Moving from step 112 to step 113, the counter N
Is increased by one.

At step 114, the counter N is set to "5".
It is determined whether or not the above has been achieved. For the first time this step 1
When 14 is executed, the counter N is "2".
In step 105, the magnetic head 57 is moved to the second track. Then, steps 106 to 111 are repeatedly executed, and the pixel signal of the second divided screen from the top is
It is recorded on the second track.

When it is determined in step 114 that the counter N is equal to or more than "5", that is, when the recording of the pixel signals of one screen on the first to fourth tracks is completed, in step 115, the main video signal recording is performed. The operation mode of the device is switched to the monitor mode, and the program ends.

FIG. 9 shows pixel signals recorded on the magnetic disk D. This pixel signal follows a format such as the NTSC system, and between the two horizontal synchronizing signals H, pixel signals P and Q of about half of one horizontal scanning line are recorded. The pixel signal P of the white circle is a signal of the first half of the odd-numbered one horizontal scanning line, and after the last signal (symbol P1) of this first half, a part of the pixel signal of the second half of the horizontal scanning line (P1) The code Q1) is recorded. The pixel signal Q of the black circle is a signal in the second half of the odd-numbered horizontal scanning line, and before the first signal (code Q1) in this second half,
Part of the pixel signal in the first half of the horizontal scanning line (reference P
1) is recorded. The pixel signals P1 and Q1 are signals at the center of one screen as shown in FIG. 4, and are recorded in two recording portions on the magnetic disk D in an overlapping manner.

The reason why the pixel signals at the center of one horizontal scanning line are recorded in an overlapping manner is that, when a magnetic disk is reproduced and one screen is displayed, a divided portion (dotted line C in FIG. 4) is displayed.
(In the vicinity of) is to prevent a seam from appearing. That is, the rise of the pixel signal is slow in the vicinity of the horizontal synchronization signal when the pixel signal is recorded on the magnetic disk D, and the pixel signal becomes dull. Therefore, such a pixel signal is discarded during reproduction.

FIG. 10 shows an apparatus for reproducing a video signal recorded on the magnetic disk D by the video signal recording apparatus shown in FIGS.

The magnetic disk D is rotated at a speed of, for example, 3600 rpm by a spindle motor 72 driven and controlled by a motor control circuit 71, similarly to the video signal recording apparatus. The magnetic head 73 includes the tracking control circuit 7
4 to set a predetermined track position.
The motor control circuit 71 and the tracking control circuit 74 are controlled by a system control circuit 75.

The video signal and the ID code recorded on the magnetic disk D according to the still video recording method are read by the magnetic head 73. The video signal is subjected to processing such as FM demodulation in an SV reproduction processing circuit 76, A / D converted in an A / D converter 78, and stored in a reproduction memory 79. On the other hand, the ID code is subjected to DPSK demodulation in the DPSK demodulation circuit 77 and is input to the system control circuit 75. The ID code includes various information such as a track number and data necessary for white balance adjustment. This data is input to the digital signal processing circuit 81. The data of the white balance adjustment is ID
Recorded in the user's area of the code.

In this video signal reading operation, the SV reproduction processing circuit 76, DPSK demodulation circuit 77, A / D converter 78, reproduction memory 79, and motor control circuit 71 have a clock generator having the same configuration as that of FIG. Is driven in accordance with the low-speed clock signal output from.

The pixel signal stored in the reproduction memory 79 is
The data is read out by the digital signal processing circuit 81, subjected to processes such as color separation and white balance adjustment, and stored in the reproduction memory 79 again. Thereby, the reproduction memory 7
9 stores a luminance signal (Y) and a color difference signal (Pr, Pb) according to the high-definition mode as digital signals. These signals (Y, Pr, Pb) are stored in the D / A converter 82. The D / A conversion is performed, and the data is directly output to the display device through the mute circuit 83. During the operation of storing the video signal in the reproduction memory 79, the mute circuit 83 outputs a signal (Y, Pr, Pb) such that the entire screen becomes blue, for example, to the display device.

In the monitor operation for reading out the pixel signals stored in the reproduction memory 79 in this manner, the reproduction memory 79 and the D / A converter 82 are driven according to the high-speed clock signal output from the clock generator.

Next, with reference to FIG. 11, the operation of reading out the pixel signals recorded on the magnetic disk D and displaying them on the display device will be described. The control shown in the flowchart of FIG. 11 is executed by a computer provided in the system control circuit 75.

In step 201, the counter N is set to "1", and in step 202, the magnetic head 74 is moved to the first track of the magnetic disk D. As described above, in the first track, the pixel signal of the uppermost divided screen among the divided screens obtained by dividing the screen in the high definition mode into four is recorded. In step 203, the pixel signals of the first track are read out, subjected to a predetermined process, and sequentially written one horizontal scanning line at a time in the memory area of the reproduction memory 79 corresponding to the divided screen.

The writing of the pixel signal into the reproduction memory 79 will be described with reference to FIG. As described above, one horizontal scanning line is divided into halves and recorded on the magnetic disk D. After the last signal P1 of the first half P of one horizontal scanning line, the first signal Q1 of the second half is recorded. Immediately before the first signal Q1 of the second half Q, the last signal P1 of the first half is recorded. That is, the signals P1 and Q1 are recorded in an overlapping manner, but these signals are distorted during recording and reproduction on the magnetic disk D, and have low accuracy as pixel signals. Therefore, in step 203, these signals P1 and Q1 are removed. That is, only the first half P is written in the predetermined area of the reproduction memory 79 except for the signal Q1 of the second half, and only the second half Q is written in the next area of this area except for the signal P1 of the first half.

After such a write operation to the reproduction memory 79, in step 204, it is determined whether or not the counter N is equal to "4". When the counter N is not "4", the reproduction of the pixel signals for the four tracks has not been completed yet. Therefore, after the counter N is incremented by 1 in step 206, steps 202 and 203 are executed again, and the next track is executed. Are reproduced and written into the memory area corresponding to the next divided screen.

When the reproduction of the pixel signals of four tracks is completed in this way, the counter N has reached "4" in step 204, so that step 205 is executed next. That is, the pixel signals stored in the reproduction memory 79 are read out to the digital signal processing circuit 81, subjected to processing such as white balance adjustment, and stored again in the reproduction memory 79, and then stored in the reproduction memory 79 in accordance with the high-speed clock signal. 79 and output to the display device.

Note that the signals P1 and Q1 recorded on the magnetic disk D redundantly do not always correspond to one pixel, and the number of pixels may be increased as necessary.

As described above, in this embodiment, the memory 65 corresponding to the capacity of about two horizontal scanning lines is used in place of the frame memory corresponding to the high definition television system, so that the image pickup apparatus can obtain the same. The memory 65 and the peripheral circuits are not driven according to the high-speed clock signal. Therefore, the configuration of this recording apparatus is inexpensive and requires less power consumption than a circuit configuration driven at high speed. Further, in the video signal recording apparatus according to the present embodiment, a raw pixel signal which is not subjected to processing such as white balance adjustment is recorded on the magnetic disk D, so that the circuit configuration for recording is simplified.

Further, in the video signal reproducing apparatus of the present embodiment, processing such as white balance adjustment is performed on the raw pixel signal recorded on the magnetic disk D. The reproduction faithful to the color temperature becomes possible.

In the above embodiment, the present invention is applied to field readout in an interline type image pickup apparatus. However, the present invention can be used for frame readout and has a frame transfer type image pickup apparatus. It can also be applied to video signal recording devices.

[0058]

As described above, according to the video signal recording apparatus of the present invention, a frame memory is not required for recording a video signal in a high-definition mode on a recording medium in a standard mode. In addition, it is possible to record a video signal with low power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an imaging device provided in a video signal recording device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a video signal recording device according to one embodiment of the present invention.

FIG. 3 is a diagram showing an array of pixel signals on one screen.

FIG. 4 is a diagram showing a relationship between a color temperature and an output signal in a color temperature detector.

FIG. 5 is a flowchart illustrating an operation of recording a pixel signal obtained by an imaging device on a magnetic disk.

FIG. 6 is a flowchart illustrating an operation of recording a pixel signal obtained by an imaging device on a magnetic disk.

FIG. 7 is a diagram showing storage and read operations in a memory.

FIG. 8 is a timing chart showing storage and read operations in the memory.

FIG. 9 is a diagram showing pixel signals recorded on a magnetic disk.

FIG. 10 is a block diagram showing a video signal reproducing apparatus according to one embodiment of the present invention.

FIG. 11 is a flowchart showing an operation of reproducing a pixel signal recorded on a magnetic disk.

FIG. 12 is a diagram illustrating an operation when writing a pixel signal recorded on a magnetic disk to a memory.

[Explanation of symbols]

 Reference Signs List 10 imaging unit 11 photodiode 65 memory 65a first memory unit 65b second memory unit 65c third memory unit 65d fourth memory unit

Claims (8)

(57) [Claims] An imaging unit that generates, transfers, and outputs a pixel signal in a high definition mode to the outside, and a transfer clock for a pixel signal transfer operation in the imaging unit,
A clock generating unit capable of outputting at a low frequency corresponding to a standard mode, a memory for temporarily storing a pixel signal output from the imaging unit, and a unit for controlling writing and reading operations of the pixel signal to and from the memory Means for writing a pixel signal read from the memory to a recording medium, wherein the memory comprises a first half of an odd-numbered horizontal scanning line among horizontal scanning lines forming an image captured by the imaging device. A first memory unit for storing the second half of the odd-numbered horizontal scanning lines, a third memory unit for storing the first half of the even-numbered horizontal scanning lines,
And a fourth memory unit for storing the latter half of the even-numbered horizontal scanning lines. Pixel signals at the center of each horizontal scanning line are redundantly stored in the first to fourth memory units. Characteristic video signal recording device. 2. The video signal recording apparatus according to claim 1, wherein the control unit has a switch for selectively connecting the first to fourth memory units to the writing unit. 3. The storage device according to claim 2, wherein the control unit stores and reads the first memory unit and the third memory unit, and stores and reads the second memory unit and the fourth memory unit.
2. The video signal recording device according to claim 1, wherein the reading and storing operations of the memory unit are performed simultaneously. 4. The standard mode is a video signal generation mode conforming to a standard television system, wherein the frequency of a subcarrier of the standard television system is fsc, Nh is the number of horizontal effective pixels, and Nn is the horizontal level of an image in the standard mode. When the number of effective pixels is set, the value of the low frequency is (4fsc × (Nh / 2) / N
2. The video signal recording apparatus according to claim 1, wherein n) or more. 5. The first memory section stores a signal of a first half of an odd-numbered horizontal scanning line and a first signal of a second half of the horizontal scanning line, and the second memory section stores a first signal of a second half of the horizontal scanning line. 1
The last signal of the first half and the signal of the second half stored in the memory unit are stored, and the third memory unit stores the signal of the first half of the even-numbered horizontal scanning line and the second half of the horizontal scanning line. The first signal is stored, and the fourth memory unit stores the last signal of the first half and the second half of the signal stored in the third memory unit. These first, second, and third signals are stored in the fourth memory unit.
2. The video signal recording apparatus according to claim 1, wherein all the pixel signals stored in the fourth memory unit are recorded on the recording medium. 6. A reproduction device comprising: means for reproducing a pixel signal recorded on a recording medium by the video signal recording apparatus according to claim 1; and a reproduction memory for storing the pixel signal reproduced by the reproduction means. A video signal reproducing apparatus, wherein a part of an overlapping part of a pixel signal redundantly stored in the first to fourth memory units is removed and stored in a memory. 7. The video signal according to claim 1, further comprising color temperature data recording means for DPSK-modulating and recording color temperature data in a predetermined area of an ID code of a recording medium during a recording operation. Recording device. 8. In a predetermined area of an ID code of a recording medium,
7. The color temperature data at the time of recording operation is recorded by DPSK modulation, and said reproducing means performs a color temperature correction process on a video signal based on the color temperature data.
3. The video signal reproducing device according to claim 1.