JP3193557B2 - Video signal recording and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention records a video signal of a still image in a high-definition mode output from a high-resolution imaging device on a recording medium in a standard mode. The present invention relates to an apparatus for reproducing in a high definition mode.

[0002]

2. Description of the Related Art Conventionally, as an electronic still video apparatus, an apparatus for recording a video signal in a high-definition mode such as Hi-Vision on a recording medium as a video signal in a standard mode such as the NTCS system has been known (Japanese Patent Laid-Open No. 5-30461). Gazette). This recording apparatus is configured to temporarily store a high-definition mode video signal in a frame memory, divide one screen into a plurality of portions, and record the divided portions on a plurality of tracks of a recording medium. Is performed at a high drive frequency corresponding to the high definition mode, and the recording operation on the recording medium is
It is performed at a low drive frequency corresponding to the standard mode.

[0003]

As described above, when data is stored in the memory, the memory and its peripheral circuits must be driven at a high speed. Therefore, it is necessary to use an expensive circuit corresponding to the high-speed drive as the memory. In addition, there is a problem that power consumption is increased.

The present invention has been made to solve the above problems, and a video signal recording apparatus which does not require a frame memory to record a video signal in a high definition mode on a recording medium in a standard mode. It is an object of the present invention to provide a device for reproducing a video signal recorded by a signal recording device.

[0005]

A video signal recording apparatus according to the present invention transfers a pixel signal to a first and a second horizontal transfer section through a plurality of vertical transfer sections provided in parallel with each other. The pixel signals transferred by the odd-numbered column vertical transfer units are output to the outside via the first horizontal transfer unit, and the pixel signals transferred by the even-numbered column vertical transfer units are output to the outside via the second horizontal transfer unit. And clock generating means capable of outputting a transfer clock for driving the vertical transfer unit and the first and second horizontal transfer units at a high frequency corresponding to the monitor operation and at a low frequency corresponding to the recording operation. And first and second output signals from the first and second horizontal transfer units, respectively.
Means for outputting a pixel signal to the monitor device as a moving image, recording signal processing means for performing processing for recording the first and second pixel signals on a recording medium, and output from the recording signal processing means. Means for recording the first and second pixel signals as still images in the first and second recording areas of the recording medium via a plurality of heads, respectively.

A video signal reproducing apparatus according to the present invention includes a means for reading a video signal recorded on a recording medium in a standard mode, and a reproducing means for performing a predetermined reproduction process on the video signal read by the reading means. And a clock generating means capable of switching and outputting a clock for driving the reading means and the reproducing means between a low frequency corresponding to the standard mode and a high frequency corresponding to the monitor operation. And

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIGS. 1 and 2 show a video signal recording apparatus according to an embodiment of the present invention. This apparatus converts a high-quality still image obtained in a high-definition mode such as a high-definition mode into an NTS image.
It is recorded on a magnetic disk according to a standard mode such as the C system.

Referring to FIG. 1, an imaging unit 10 of an imaging apparatus
Are provided with, for example, about 2 million photodiodes 11 arranged regularly in the vertical and horizontal directions. Each photodiode 11 corresponds to each pixel, and optical information detected by each photodiode 11 is converted into an electric signal, and a vertical transfer CCD (vertical transfer unit) as described later.
12. First and second horizontal transfer CCD (horizontal transfer unit) 1
The image is output from the image pickup device via 3 and 14. In the figure, the lower side of the imaging unit 10 corresponds to the upper side of the screen of the display device (not shown), and the upper side of the imaging unit 10 corresponds to the lower side of the screen.

In FIG. 1, a vertical transfer CCD 12 is formed beside each column of photodiodes 11 extending vertically. That is, a plurality of vertical transfer CCDs 12 are provided in parallel with each other.
The output signal (pixel signal) is transferred to the vertical transfer CCD 12 adjacent thereto, and transferred to the first and second horizontal transfer CCDs 13 and 14 via the vertical transfer CCD 12. Note that the transfer operation in the vertical transfer CCD 12 is based on the vertical transfer clock signal φV applied to the imaging unit 10.
1 to φV4.

The first horizontal transfer CCD 13 is connected to the vertical transfer CCD 12 via a first transfer gate 15, and the second horizontal transfer CCD 14 is connected to the first horizontal transfer CCD 13 via a second transfer gate 16. Accordingly, pixel signals output from each vertical transfer CCD 12 are transferred to the first horizontal transfer CCD 13 through the first transfer gate 15, and output from the even-numbered vertical transfer CCD 12 counted from the left end in FIG. The pixel signal is transferred to the second horizontal transfer CCD 14 through the second transfer gate 16. Opening and closing operations of the first and second transfer gates 15 and 16 are controlled by transfer gate signals φT1 and φT2.

That is, the pixel signals output from the odd-numbered vertical transfer CCDs 12 counted from the left end in FIG. 1 are transferred in the horizontal direction by the first horizontal transfer CCDs 13 and output from the even-numbered column vertical transfer CCDs 12. The pixel signals are transferred by the second horizontal transfer CCD 14 in the horizontal direction. The transfer operation in the first and second horizontal transfer CCDs 13 and 14 is controlled by horizontal transfer clock signals φH1 and φH2. Pixel signals output from the horizontal transfer CCDs 13 and 14 are amplified by output amplifiers 31 and 32 and supplied to a signal processing circuit shown in FIG.

Vertical transfer clock signals φV1 to φV4, transfer gate signals φT1, φT2, horizontal transfer clock signal φ
The driving frequencies of H1 and φH2 are set at high frequencies (3
7.125 MHz), and can be switched to a low frequency (18.614 Hz) when recording video signals on a magnetic disk (during recording operation). The value of this low frequency is (4fsc × (Nh / 2)) where fsc is the frequency of the subcarrier of the NTSC system (standard mode) which is a standard television system, for example.
/ Nn) or more. Here, Nh is the number of horizontal effective pixels of the image sensor, and Nn is the number of horizontal effective pixels of the image in the standard mode, and (Nh /
2) The low frequency value can be obtained from a simple integer ratio exceeding and relatively close to / Nn. In this example, it is obtained from a ratio of 13/10. The high-frequency signal is generated by the oscillator of the high-definition synchronizing signal generator 21, and the low-frequency signal is generated by the oscillator of the standard synchronizing signal generator 22. Depending on the switching state of the switch 23, the high-frequency signal or the low-frequency signal is generated. A signal is output from the CCD clock generator 24.

Output ends of the horizontal transfer CCDs 13 and 14 are connected to reset drains 17 and 18, respectively. The operation of sweeping out the charges in the drains 17 and 18 is performed after the reading of the signal charges from the horizontal transfer CCDs 13 and 14 is completed, and is controlled by the drive signal φRG.

In order to sweep out the unnecessary charges accumulated in the horizontal transfer CCDs 13 and 14 at a stretch, the smear drain 1
9 are provided. The sweeping operation of the smear drain 19 is controlled by the drive signal φSMG, and the vertical transfer C
This is performed before the pixel signal of the next horizontal scanning line is transferred from the CD 12 to each of the horizontal transfer CCDs 13 and 14.

Referring to FIG. 2, a description will be given of a configuration for performing predetermined processing on a pixel signal output from an imaging device, monitoring the moving image by a display device (not shown), or recording the moving image on a magnetic disk D as a still image. I do.

The pixel signals output from the output amplifiers 31 and 32 are respectively correlated double sampling circuits (CDS).
The noise is removed at 33 and 34 and input to the low-pass filters 35 and 36 and the camera process circuit 37.
The camera process circuit 37 performs color separation processing according to a high-speed clock signal output from the clock generator 24.
Gamma correction, white balance adjustment, and the like are performed, whereby a luminance signal (Y) and color difference signals (Pr, Pb) according to the high definition mode are obtained. These signals (Y, P
(r, Pb) is directly output to the display device through the mute circuit 38 during the monitor operation. On the other hand, during the recording operation, the mute circuit 38 outputs signals (Y, Pr, Pb) such that the entire screen becomes blue, for example, to the display device.

The color temperature detector 41 detects the color temperature of the subject, and the information on the color temperature is converted by the system control circuit 42 into data used for white balance adjustment (color temperature correction processing). . The color temperature data is directly input from the system control circuit 42 to the camera process circuit 37 during the monitor operation. The color temperature data is output from the system control circuit 42 as ID data together with various information such as a track number during the recording operation, and is input to the DPSK modulation circuits 51 and 52. This I
The D data is supplied to the DPSK modulation circuits 51 and 52 at the DPS
The signal is K-modulated and input to addition circuits 53 and 54. In addition,
Regarding the color temperature data included in the ID data,
Details will be described later.

At the time of recording operation, the pixel signals output from the CDSs 33 and 34 are subjected to high-frequency components removed by low-pass filters 35 and 36, and then are subjected to blanking circuits 43 and 4.
4, a blanking period is provided between each horizontal scanning period including a large number of pixel signals. In the synchronization signal adding circuits 45 and 46, a vertical synchronization signal is added during a vertical blanking period, and a horizontal synchronization signal is added during a horizontal blanking period. The signal subjected to such processing is
In the SV recording processing circuits 55 and 56, processing such as FM modulation is performed, and input to the addition circuits 53 and 54.

In addition circuits 53 and 54, output signals from SV recording processing circuits 55 and 56 and DPSK modulation circuit 51,
The output signal from 52 is superimposed on each other, and the obtained video signal and ID code are recorded on the magnetic disk D via the two magnetic heads 57 and 58 according to the still video recording method. That is, of the pixel signals output from the image pickup device, the pixel signals of the odd columns are recorded on the first track (recording area) of the magnetic disk D via the magnetic head 57, and the pixel signals of the even columns are magnetic. The data is recorded on the second track adjacent to the inside of the first track via the head 58.

The magnetic disk D is rotated at a speed of, for example, 3600 rpm by a spindle motor 62 driven and controlled by a motor control circuit 61. Magnetic heads 57, 5
8 is driven by the tracking control circuit 63 and is set at a predetermined track position. The motor control circuit 61 and the tracking control circuit 63 are controlled by the system control circuit 42.

Each circuit shown in a portion surrounded by a broken line B in FIG. 2 operates according to a low-speed clock signal output from the clock generator 24.

The color temperature data included in the ID data will be described with reference to FIG. The color temperature detector 41 has three light receiving elements for detecting an R (red) component, a G (green) component, and a B (blue) component included in the light beam, and the R and G detected by each light receiving element. And outputs a R / G signal and a B / G signal as voltage signals based on the signals of the B component and the B component. The R / G signal and the B / G signal are converted into digital signals in the system control circuit 42,
It is recorded in the ID data as white balance information.
Each of the R / G signal and the B / G signal is 8-bit data, and therefore, the amount of white balance information in the ID data is 16 bits.

Next, with reference to FIG. 1 and FIGS. 4 to 6, the operation of recording pixel signals obtained by the image pickup device on the magnetic disk D will be described. FIG. 4 shows an arrangement of each pixel signal in one screen, and FIGS. 5 and 6 show control by a computer provided in the system control circuit 42.

In FIG. 4, pixel signals indicated by white circles and black circles are obtained by the odd-numbered photodiodes 11 counted from the left end in FIG. 1, and pixel signals indicated by white triangles and black triangles are even-numbered columns. Obtained by the photodiode 11 of the eye. The white circle and white triangle pixel signals belong to the first field, and the black circle and black triangle pixel signals belong to the second field. Each row extending in the left-right direction of FIG. 4 and formed by alternately arranging pixel signals indicated by circles and pixel signals indicated by triangles corresponds to one horizontal scanning line.

In this embodiment, one screen is divided into two parts by a dashed line S extending in parallel with the horizontal scanning line.
It is composed of 00 horizontal scanning lines.

Referring to FIG. 5, in step 101,
The operation mode of the video signal recording apparatus is set to the recording mode, and the switch 23 of the clock generator 24 is switched to the standard mode side (the state shown by the broken line in FIG. 1). Step 10
In 2, the shutter is opened and closed in response to a release button (not shown), and an image of one screen is captured. Step 103
In, the parameter F indicating the field is set to “1”, and in step 104, the counter N is set to “1”.

In step 105, the pixel signal of the F-th field is transferred to the vertical transfer CCD 12. When step 105 is executed for the first time, since the parameter F is “1”, the pixel signal of the first field, that is, the white circle and white triangle pixel signals of FIG. In step 106, the magnetic heads 57 and 58 are respectively transferred to the Nth and (N + 1) th tracks, that is, first to the first and second tracks.

In step 107, transfer gate signal φT
1 is output and the first transfer gate 15 is opened, whereby the pixel signal for one horizontal scanning line held at the portion of each vertical transfer CCD 12 closest to the transfer gate 15 is output.
The data is transferred to the first horizontal transfer CCD 13. After this transfer operation, the first transfer gate 15 is closed. When this step 107 is performed for the first time, the pixel signal of one horizontal scanning line (row in which pixel signals of white circles and pixel signals of white triangles are alternately formed) located in the uppermost row in FIG. First
The data is transferred to the horizontal transfer CCD 13. Note that the vertical transfer CC
The transfer operation in D12 is performed according to a low-speed clock signal.

In step 108, the transfer gate signal φT
2 is output and the second transfer gate 16 is opened, whereby the even-numbered pixel signal of the first horizontal transfer CCD 13 is transferred to the second horizontal transfer CCD 14. After this transfer operation, the second transfer gate 16 is closed. In this manner, for one horizontal scanning line, the odd-numbered pixel signals (white circles) are transferred to the first horizontal transfer CCD 13, and the even-numbered pixel signals (white triangles) are transferred to the second horizontal transfer CCD 14. .

In step 109, the first and second horizontal transfer CCDs 13 and 14 are driven by a low-speed clock signal, the first horizontal transfer CCD 13 outputs odd-numbered pixel signals, and the second horizontal transfer CCD 14 outputs even-numbered pixel signals. A pixel signal is output.

In step 110, each horizontal transfer CCD 1
The pixel signals output from 3 and 14 are subjected to still video recording signal processing in the signal processing circuit of FIG. 2 and are simultaneously recorded on the first and second tracks of the magnetic disk D via the magnetic heads 57 and 58, respectively. Is done. Step 1
At 11, it is determined whether or not recording of these two tracks has been completed. In this embodiment, the upper half of one screen (FIG. 4)
, The pixel signal of the odd-numbered column is the first
The pixel signal of the even-numbered column is recorded in one round of the track, and the pixel signal of the even-numbered column is recorded in one round of the second track. , By counting the horizontal synchronization signal.

If the recording of one half of one screen has not been completed, steps 107 to 110 are executed again, and the signal of the next horizontal scanning line is read from the image pickup device and recorded on the magnetic disk D. By repeating such an operation, the first
When the upper half pixel signals of the first field are recorded on the second track and the second track, respectively, the process proceeds from step 111 to step 112, and the counter N is incremented by two.

At step 113, the counter N is set to "5".
It is determined whether or not the above has been achieved. For the first time this step 1
13 is executed, the counter N is "3".
Step 106 is executed, and the magnetic heads 57 and 58 are transferred to the third and fourth tracks, respectively. Then, steps 107 to 110 are repeatedly executed, and the pixel signal of the first field of the lower half of one screen (reference Q in FIG. 4) is recorded on the third and fourth tracks.

When it is determined in step 113 that the counter N is equal to or more than "5", that is, when the recording of the pixel signal of the first field on the first to fourth tracks is completed, the pixel of the second field is Signal to magnetic disk D
In step 114, the parameter F is set to “2”. Next, at step 115, it is determined whether or not the counter N is "5". When this step 115 is executed for the first time, the counter N is "5". The pixel signal is transferred to the vertical transfer CCD 12. That is,
The pixel signals of black circles and black triangles in FIG.
2 Then, in step 106, the magnetic heads 57 and 58 are moved to the fifth and sixth tracks, respectively, and steps 107 to 111 are repeatedly executed, and the pixel signals of the upper half of the second field are recorded on the fifth and sixth tracks. You.

When the recording of the pixel signal of the upper half of the second field is completed, the counter N is set to "7" in step 112, and steps 113, 114, 115 and
The operations are performed in the order of 116. Since it is determined in step 116 that the counter N is not "9", step 106
Then, the magnetic heads 57 and 58 are transferred to the seventh and eighth tracks, respectively. And steps 107 to 11
1 is repeatedly executed, and pixel signals of the lower half of the second field are recorded on the seventh and eighth tracks.

When the recording of the pixel signal of the lower half of the second field is completed, the counter N is set to "9" in step 112, so that the process proceeds from step 116 to step 117, and the operation mode of the present video signal recording apparatus is monitored. Mode and the program ends.

FIG. 7 shows an apparatus for reproducing a video signal recorded on the magnetic disk D by the video signal recording apparatus shown in FIGS.

The magnetic disk D is rotated at a speed of, for example, 3600 rpm by a spindle motor 72 driven and controlled by a motor control circuit 71, similarly to the video signal recording apparatus. Only one magnetic head 73 is provided,
Driven by the tracking control circuit 74, the track position is determined. The motor control circuit 71 and the tracking control circuit 74 are controlled by a system control circuit 75.

The video signal and the ID code recorded on the magnetic disk D according to the still video recording method are read by the magnetic head 73. The video signal is subjected to processing such as FM demodulation in an SV reproduction processing circuit 76, A / D converted in an A / D converter 78, and then stored in a memory 79. On the other hand, the ID code is subjected to DPSK demodulation in the DPSK demodulation circuit 77 and is input to the system control circuit 75. The ID code includes various information such as a track number and data necessary for white balance adjustment. This data is input to the digital signal processing circuit 81. The white balance adjustment data is recorded in the user area of the ID code.

In this video signal read operation, the SV reproduction processing circuit 76, DPSK demodulation circuit 77, A / D converter 78, memory 79 and motor control circuit 71 are provided by a clock generator having the same configuration as that of FIG. It is driven according to the output low-speed clock signal.

The pixel signals stored in the memory 79 are read out by the digital signal processing circuit 81, subjected to processes such as color separation and white balance adjustment, and stored in the memory 79 again. As a result, the luminance signal (Y) and the color difference signals (Pr, P) according to the high-definition mode are stored in the memory 79.
b) is stored as a digital signal, and these signals (Y, Pr, Pb) are D / A-converted by the D / A converter 82 and output directly to the display device through the mute circuit 83. . During the operation of storing the video signal in the memory 79, the mute circuit 83 outputs a signal (Y, P
r, Pb) is output to the display device.

In the monitor operation for reading out the pixel signals stored in the memory 79 in this manner, the memory 79 and the D / A converter 82 are driven according to the high-speed clock signal output from the clock generator.

Next, referring to FIGS. 8 and 9, the operation of reading out pixel signals recorded on the magnetic disk D and displaying the read out signals on the display device will be described. The control shown in the flowcharts of FIGS. 8 and 9 is executed by a computer provided in the system control circuit 75.

In step 201, the magnetic head 74 is moved to the first track of the magnetic disk D. As described above, the pixel signals corresponding to the odd columns in the upper half of the first field of the screen in the high definition mode are recorded on the first track. In step 202, the pixel signals of the first track are read out, subjected to a predetermined process, and sequentially written into a predetermined area of the memory 79 one by one horizontal scanning line. Next, at step 203, the magnetic head 74 is moved to the second track. Then, in step 204, the pixel signal of the second track, that is, the pixel signal corresponding to the even-numbered column in the upper half of the first field, is read out and sequentially written in a predetermined area of the memory 79 one by one horizontal scanning line. Hereinafter, the same operation is performed.

That is, in steps 205 and 206, the pixel signals corresponding to the odd columns in the lower half of the first field are written in the memory 79. In steps 207 and 208,
Pixel signals corresponding to even columns are written to the memory 79. In steps 209 and 210, pixel signals corresponding to the odd columns in the upper half of the second field are written to the memory 79. In steps 211 and 212, pixel signals corresponding to the even columns are written to the memory 79. Step 21
In steps 3 and 214, the pixel signals corresponding to the odd columns in the lower half of the second field are written in a predetermined area of the memory 79. In steps 215 and 216, the pixel signals corresponding to the even columns are written in the memory 79.

After all the pixel signals of one screen are stored in the memory 79 in this way, in step 217,
The pixel signals stored in the memory 79 are read out by the digital signal processing circuit 81, subjected to processing such as white balance adjustment, and stored in the memory 79 again. Then, the signal stored in the memory 79 is read out from the memory 79 in accordance with the high-speed clock signal and output to the display device.

As described above, according to the present embodiment, the memory and the peripheral circuits are not driven according to the high-speed clock signal in the operation of recording the pixel signals in the high-definition mode obtained by the imaging device on the magnetic disk D. Therefore,
The configuration of this recording apparatus is inexpensive and requires less power consumption than a circuit configuration driven at high speed. Further, in the video signal recording apparatus according to the present embodiment, a raw pixel signal which is not subjected to processing such as white balance adjustment is recorded on the magnetic disk D, so that the circuit configuration for recording is simplified.

In the video signal reproducing apparatus according to the present embodiment, the raw pixel signal recorded on the magnetic disk D is subjected to processing such as white balance adjustment. The reproduction faithful to the color temperature becomes possible.

In the above embodiment, the present invention is applied to frame reading in an interline type image pickup apparatus. However, the present invention can be used for field readout and has a frame transfer type image pickup apparatus. It can also be applied to video signal recording devices.

[0050]

As described above, according to the video signal recording apparatus of the present invention, a frame memory is not required for recording a video signal in a high-definition mode on a recording medium in a standard mode. In addition, it is possible to record a video signal with low power consumption. According to the video signal reproducing device of the present invention, the video signal recorded by the video signal recording device of the present invention can be reproduced and displayed on a display device or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an imaging device provided in a video signal recording device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a video signal recording device according to one embodiment of the present invention.

FIG. 3 is a diagram illustrating a relationship between a color temperature and an output signal in a color temperature detector.

FIG. 4 is a diagram showing an array of pixel signals on one screen.

FIG. 5 is a flowchart illustrating an operation of recording a pixel signal obtained by an imaging device on a magnetic disk.

FIG. 6 is a flowchart illustrating an operation of recording a pixel signal obtained by an imaging device on a magnetic disk.

FIG. 7 is a block diagram showing a video signal reproducing apparatus according to an embodiment of the present invention.

FIG. 8 is a flowchart showing an operation of reproducing a pixel signal recorded on a magnetic disk.

FIG. 9 is a flowchart showing an operation of reproducing a pixel signal recorded on a magnetic disk.

[Explanation of symbols]

 11 Photodiode 12 Vertical transfer CCD 13 First horizontal transfer CCD 14 Second horizontal transfer CCD

Claims (7)

(57) [Claims] 1. A pixel signal is transferred to first and second horizontal transfer units via a plurality of vertical transfer units provided in parallel with each other, and the pixel signal transferred by the odd-numbered column vertical transfer unit is Imaging means for outputting to the outside via the first horizontal transfer unit and for outputting the pixel signal transferred by the vertical transfer unit for the even-numbered column to the outside via the second horizontal transfer unit;
Monitor output means for outputting the first and second pixel signals respectively output from the horizontal transfer unit to a monitor device as a moving image in accordance with a high-frequency transfer clock; and outputting the first and second pixel signals to a recording medium. A recording signal processing means for performing processing for recording, and a first and a second pixel signals output from the recording signal processing means are transmitted to a first recording medium of a recording medium via a plurality of heads in accordance with a low-frequency transfer clock. Means for recording a still image in each of the first and second recording areas, switching means for selecting and operating one of the monitor output means and the recording means, and the transfer clock,
A video signal recording apparatus, comprising: clock generation means capable of outputting at a high frequency corresponding to the monitor operation of the monitor output means and at a low frequency corresponding to the recording operation of the recording means. 2. The video signal recording apparatus according to claim 1, wherein the monitor operation is performed in a high definition mode, and the recording operation is performed in a standard mode. 3. The standard mode is a video signal generation mode conforming to a standard television system, wherein the frequency of a subcarrier of the standard television system is fsc, Nh is the number of horizontal effective pixels of the imaging means, and Nn is a standard mode. When the number of horizontal effective pixels of the image is set to the value of the low frequency, (4fsc × (N
h / 2) / Nn) or more.
2. The video signal recording device according to claim 1. 4. The image forming apparatus according to claim 1, wherein the color temperature information at the time of image pickup is stored in an ID of a recording medium.
2. The video signal recording apparatus according to claim 1, further comprising a color temperature information recording unit that records the code in a predetermined area of the code by DPSK modulation. 5. The video signal recording apparatus according to claim 1, wherein said switching means operates during a shutter release operation for recording a video signal on a recording medium. 6. An apparatus for reproducing a video signal recorded on a recording medium by the video signal recording apparatus according to claim 1, comprising: means for reading a video signal recorded on a recording medium in a standard mode; A reproducing unit for performing a predetermined reproducing process on the read video signal; and a clock for driving the reading unit and the reproducing unit, a low frequency corresponding to the standard mode and a high frequency corresponding to the monitor operation. And a clock generating means capable of switching and outputting the video signal. 7. A color temperature information at the time of imaging is recorded in a predetermined area of an ID code of the recording medium by DPSK modulation, and the reproducing means corrects a color signal to a video signal based on the color temperature information. The video signal reproducing device according to claim 5, wherein the video signal reproducing device performs a process.