JPS63145564A - Interface for controlling peripheral equipment - Google Patents

Abstract

PURPOSE:To control different kinds of peripheral equipments by means of a common interface without giving a specific circuit to a control signal of the peripheral equipment side by using an arithmetic control section so as to control an enable clock generating circuit, a polarity inversion circuit and a tri-state buffer. CONSTITUTION:The enable clock generating circuit 1 generates an enable clock controlling the peripheral equipments 4, 5 and the said enable clock is fed to the polarity inversion circuit 2. The polarity inversion circuit 2 inverts the enable clock selectively according to the control signal fed from the arithmetic control section 6. That is, the arithmetic control section 6 identifies at which polarity of the enable clock the connected peripheral equipment is in operation and control the polarity inversion of the polarity inversion circuit 2. Thus, different kinds of peripheral equipments are controlled by the common interface.

Description

[Detailed Description of the Invention] [Summary 1 Polarity! Two types of cycles that operate with the enable clock A)! This is an interface that controls 8 ifs, and allows two types of peripheral devices to be controlled by one interface without adding any circuits to the peripheral device side.

[Industrial Application Field 1] The present invention relates to a peripheral Q position control interface, and more specifically, to a peripheral Q position control interface, and more particularly, to
II+- to one interface to control different types of peripheral devices.
! It's Surano.

[Prior Art] For example, it is possible to selectively connect a liquid crystal display device that displays high brightness and a liquid crystal display device that displays low density display to a type of word processor that uses a 5A liquid crystal display, depending on the purpose. There is something configured.

In this case, if the control signals for the liquid crystal display devices including the enable clock are shared, it is possible to connect the high-density liquid crystal display device and the low-density liquid crystal display device to the main body without being aware of it. The liquid crystal display device is configured such that a high-density display liquid crystal display device operates with a positive polarity enable clock, and a low-density display liquid crystal display device operates with a negative polarity enable clock.

By the way, when using a conventional liquid crystal display device configured to operate according to the polarity of the enable clock as described above, it is necessary to provide a circuit corresponding to the polarity of the enable clock assigned to each liquid crystal display device. things were being done.

[Problems to be Solved by the Invention] However, with such a conventional configuration, although the interface on the main device side can be shared, a circuit specific to control signals must be added to each peripheral device side. First, there was a problem that the circuit configuration on the peripheral device side became complicated and the cost became high.

The present invention has been made in view of these points, and provides a peripheral device control system that allows different types of peripheral devices to be controlled using a common ink face without adding any circuit specific to the peripheral device side control signals. The purpose is to provide an interface.

[Means for Solving the Problems] Fig. 1 is a physical block diagram of the y1s!i position control ink face of the present invention. In the figure, 1 indicates the enable clock generation circuit, and 2 indicates the polarity of the enable clock. 3 is a tri-state buffer, and these enable clock generation circuits 1 and 3 are tri-state buffers.
, the polarity inverting circuit 2 and the tricycle buffer 3 are l
It operates according to the control signal applied from the i-port control IW6. Reference numerals 4 and 5 indicate peripheral devices, and the control signal line of the peripheral device 4 is pulled up, and the control signal line of the peripheral device 5 is pulled down.

[Operation Coin enable clock generation circuit 1 generates one enable clock for controlling peripheral devices 4.5, and this enable clock is applied to polarity inversion circuit 2. The polarity inversion circuit 2 selectively inverts the enable [ ] in accordance with a control signal applied from the σ operation control section 6 . That is, the arithmetic control unit 6 identifies which polarity of the enable clock the connected peripheral device operates with by executing a pre-stored program. Then, in accordance with the identification result, the polarity inversion operation of the potential inversion circuit 2 is controlled. Note that during the initial operation until the arithmetic control unit 6 identifies the type of peripheral device and starts controlling the polarity inversion operation of the polarity inversion circuit 2,
Trice date buffer 773 is set to high impedance.

This prevents peripheral devices from malfunctioning due to unstable enable clocks caused by initial operation, and allows different types of peripheral devices to be controlled using a common interface.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, and the same parts as in FIG. 1 are denoted by the same reference numerals. In FIG. ing. That is, Exclusive A Agate 2
The output signal of the enable clock generation circuit 1 is applied to one input terminal of the , and the output signal of the enable clock generation circuit 1 is applied to the other input terminal of the arithmetic control section 6.
An inverted control signal is applied from

The operation of the device configured as described above will be explained as follows.

For example, if the peripheral device 4 operates with a 0-polarity enable clock, its control signal line is pulled up in advance and set to a high level. -14 does not work. Further, tryst days 1 to 3 are set to high impedance. The execution unit 90G identifies that the clock i22'A iα4 is set to operate with the enable clock of negative polarity by executing the program. And Exclusive or Good 2
After fixing the inverted tII signal applied to the signal to a high level, the trice art gate 3 is heard. Also, an enable clock is generated at the corner where the peripheral device 4 is operated.

As a result, the peripheral device 4 operates according to the negative enable clock applied via the tristate gate 3. On the other hand, if the peripheral device is set to operate with a positive enable clock, its control signal line may be pulled down and the inverted control signal may be fixed at a low level.

In the above embodiment, the peripheral device is a liquid crystal display device, but other devices may be used.

[Effects of the Invention] As explained in detail above, according to the present invention, the type of E
A peripheral device control interface that can control the peripheral device A using a common interface can be provided, and the circuit on the peripheral device side can be simplified and costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a peripheral device control ink face according to the present invention, and FIG. 2 is a structural block diagram showing an embodiment of the present invention. In Figures 1 and 2, 1 is an enable clock generation circuit, 2 is a polarity inversion circuit (exclusive OR gate), 3 is a tri-state buffer, 4.5 is a peripheral device, and 6 is a pruning control section. .

Claims (1)

[Claims] In an interface that controls two types of peripheral devices (4) and (5) that operate with enable clocks of different polarities, the enable clock generating circuit (1) a polarity inversion circuit (2) that inverts the polarity of the enable clock, a tri-state buffer (3) that controls the transmission of the enable clock whose polarity has been inverted, and an arithmetic control section (6) that outputs control signals to each section. A peripheral device control interface, characterized in that the tri-state buffer (3) is set to high impedance during initial operation so that the enable clock is not output from the polarity inversion circuit (2).