JPS63145546A - モジュロw回路 - Google Patents

モジュロw回路

Info

Publication number
JPS63145546A
JPS63145546A JP62158807A JP15880787A JPS63145546A JP S63145546 A JPS63145546 A JP S63145546A JP 62158807 A JP62158807 A JP 62158807A JP 15880787 A JP15880787 A JP 15880787A JP S63145546 A JPS63145546 A JP S63145546A
Authority
JP
Japan
Prior art keywords
modulo
value
circuit
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62158807A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0542017B2 (enrdf_load_stackoverflow
Inventor
Teru Ishizuka
輝 石塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of JPS63145546A publication Critical patent/JPS63145546A/ja
Publication of JPH0542017B2 publication Critical patent/JPH0542017B2/ja
Granted legal-status Critical Current

Links

JP62158807A 1986-07-03 1987-06-27 モジュロw回路 Granted JPS63145546A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP15500886 1986-07-03
JP61-155008 1986-07-03

Publications (2)

Publication Number Publication Date
JPS63145546A true JPS63145546A (ja) 1988-06-17
JPH0542017B2 JPH0542017B2 (enrdf_load_stackoverflow) 1993-06-25

Family

ID=15596672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62158807A Granted JPS63145546A (ja) 1986-07-03 1987-06-27 モジュロw回路

Country Status (1)

Country Link
JP (1) JPS63145546A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0542017B2 (enrdf_load_stackoverflow) 1993-06-25

Similar Documents

Publication Publication Date Title
Efanov et al. Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger’s code
US10992314B2 (en) Residue number systems and methods for arithmetic error detection and correction
Romanov et al. A method of synthesis of irredundant circuits admitting single fault detection tests of constant length
JPS63145546A (ja) モジュロw回路
Vasudevan et al. A technique for modular design of self-checking carry-select adder
Roy Diagnosis and fault equivalence in combinational circuits
JPS6088370A (ja) 論理回路
US3459927A (en) Apparatus for checking logical connective circuits
US6027243A (en) Parity check circuit
JPH0542015B2 (enrdf_load_stackoverflow)
JPS63145539A (ja) モジュロw回路
JPH0542016B2 (enrdf_load_stackoverflow)
JPS63145547A (ja) モジュロw回路
JPH01169544A (ja) モジュロn回路
Vedeshenkov On the BGM model-based diagnosis of failed modules and communication lines in digital systems
JPS63145542A (ja) モジュロw回路
JP3123962B2 (ja) Fifoメモリのエラー検出方式
Friedman et al. Restricted checking sequences for sequential machines
Narayanan et al. Carry Select Adder Based on Dual Rail Error Detection and Easy Testability
Chakravarty Synthesis of delay fault testability circuits
JPH0713653B2 (ja) 故障検出回路
JP3052900B2 (ja) テスト回路
JPH01227973A (ja) 試験容易化回路
Dorr Self-checking combinational logic binary counters
JP2008134067A (ja) 半導体集積回路