JPS63144603A - Transmission line - Google Patents
Transmission lineInfo
- Publication number
- JPS63144603A JPS63144603A JP61292719A JP29271986A JPS63144603A JP S63144603 A JPS63144603 A JP S63144603A JP 61292719 A JP61292719 A JP 61292719A JP 29271986 A JP29271986 A JP 29271986A JP S63144603 A JPS63144603 A JP S63144603A
- Authority
- JP
- Japan
- Prior art keywords
- line
- center conductor
- impedance
- conductor
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000012212 insulator Substances 0.000 claims abstract description 13
- 150000001875 compounds Chemical class 0.000 claims description 13
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
Landscapes
- Waveguides (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半絶縁性化合物半導体基板上に形成される
低インピーダンスの伝送線路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a low impedance transmission line formed on a semi-insulating compound semiconductor substrate.
第３図、第４図は従来の伝送線路を示す上面図およびＢ
−Ｂ断面図である。この伝送ｉ路は、半絶縁性化合物半
導体基板１上へ形成した、それぞれ特性インピーダンス
に対応する幅を持つマイクロストリップ線路２，３，４
を示している。なお、５は前記半絶縁性化合物半導体基
板１の裏面接地導体である。Figures 3 and 4 are top views showing conventional transmission lines and B
-B sectional view. This transmission i-path consists of microstrip lines 2, 3, and 4 formed on a semi-insulating compound semiconductor substrate 1, each having a width corresponding to a characteristic impedance.
It shows. Note that 5 is a ground conductor on the back surface of the semi-insulating compound semiconductor substrate 1.
次に動作について説明する。Next, the operation will be explained.
半絶縁性化合物半導体基板１上に形成されたマイクロス
トリップｉ路２，３，１１の特性インピーダンスは、そ
の線路幅と半絶縁性化合物半導体基板１の比誘電率と基
板厚によって決まる。The characteristic impedance of the microstrip i-paths 2, 3, and 11 formed on the semi-insulating compound semiconductor substrate 1 is determined by the line width, the dielectric constant of the semi-insulating compound semiconductor substrate 1, and the substrate thickness.
半絶縁性化合物半導体基板１の比誘電率を一定とした場
合、マイクロストリップ線路２，３．４の特性インピー
ダンスはその線路幅と半絶縁性化合物半導体基板１の厚
みの比が大きいほど低い特性インピーダンスを持ち、小
さいほど高い特性インピーダンスをもつ伝送線路となる
。When the dielectric constant of the semi-insulating compound semiconductor substrate 1 is constant, the characteristic impedance of the microstrip lines 2, 3.4 becomes lower as the ratio between the line width and the thickness of the semi-insulating compound semiconductor substrate 1 increases. The smaller the impedance, the higher the characteristic impedance of the transmission line.
このような理由から、第３図において、マイクロストリ
ップ線絡３が他のマイクロストリップ線路２，４より非
常に低い特性インピーダンスの場合、線路幅が拡がり、
集積化するうえで面積をとることがわかる。For this reason, in FIG. 3, when the microstrip line 3 has a much lower characteristic impedance than the other microstrip lines 2 and 4, the line width increases,
It can be seen that the area is required for integration.
従来の伝送線路は以上のような特徴をもち、低い特性イ
ンピーダンス１７％路３を形成する場合、線路幅が半絶
縁性化合物半導体基板１で大きな面積をとり、集積回路
の面積を縮小することができないなどの問題点があった
。Conventional transmission lines have the above characteristics, and when forming a low characteristic impedance 17% line 3, the line width takes up a large area on the semi-insulating compound semiconductor substrate 1, making it possible to reduce the area of the integrated circuit. There were problems such as not being able to do so.
この発明は、上記のような問題点を解消するためになさ
れたもので、線路幅をあまり拡げずに、特定の低いイン
ピーダンス線路を得ることができ、かつ集積回路の縮小
化を図った伝送線路を得ることを目的とする。This invention was made to solve the above-mentioned problems, and it is a transmission line that can obtain a specific low impedance line without significantly increasing the line width, and that also reduces the size of the integrated circuit. The purpose is to obtain.
この発明に係る伝送線路は、半絶縁性化合物半導体基板
上に下側接地導体を設け、この上に中心導体線路を、下
側絶縁体を介して形成し、中心導体線路に接触しないよ
うに上側接地導体を、上側絶縁体を介して中心導体線路
を取り囲むように形成したものである。In the transmission line according to the present invention, a lower ground conductor is provided on a semi-insulating compound semiconductor substrate, a center conductor line is formed on the lower ground conductor via a lower insulator, and an upper ground conductor line is formed so as not to contact the center conductor line. A ground conductor is formed to surround the center conductor line via an upper insulator.
この発明における伝送線路は、中心導体線路と接地導体
が非常に近接することにより、線路幅を拡げずに低い特
性インピーダンスの伝送線路が実現される。In the transmission line according to the present invention, the center conductor line and the ground conductor are very close to each other, so that a transmission line with low characteristic impedance can be realized without increasing the line width.
以下、乙の発明の一実施例を図面について説明する。 An embodiment of the invention of B will be described below with reference to the drawings.
第１図はこの発明の一実施例を示す伝送線路の上面図で
、あり、第２図は、第１図のＡ−Ａ断面図を示す。FIG. 1 is a top view of a transmission line showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA in FIG.
第１図、第２図において、１，２，４．５は第３図、第
４図と同じものであり、６は前記半絶縁性化合物半導体
基板１上に形成された下側接地導体、７はこの下側接地
導体６上に下側絶縁体９を介して形成された中心導体線
路、８は上側接地導体で、中心導体線路７に接触しない
ように上側絶縁体１ｏを介して形成される。1 and 2, 1, 2, and 4.5 are the same as in FIGS. 3 and 4, and 6 is a lower ground conductor formed on the semi-insulating compound semiconductor substrate 1; 7 is a center conductor line formed on this lower ground conductor 6 via a lower insulator 9, and 8 is an upper ground conductor, which is formed via an upper insulator 1o so as not to contact the center conductor line 7. Ru.
第１図は特定インピーダンスをもつマイクロストリップ
線路２から低インピーダンス線路である中心導体線′Ｉ
ＦＩ７へ接続し、高インピーダンス線路であるマイクロ
ストリップ線路４へ接続した状態である。上、下側接地
導体６，８と中心導体線路７の間隔が狭いために、低イ
ンピーダンスでも線路幅はあまり拡げる必要はなくなる
。Figure 1 shows a central conductor line 'I' which is a low impedance line from a microstrip line 2 with a specific impedance.
It is connected to FI 7 and connected to microstrip line 4 which is a high impedance line. Since the distance between the upper and lower ground conductors 6, 8 and the center conductor line 7 is narrow, there is no need to widen the line width much even if the impedance is low.
第２図に示したように、中心導体線ｌｌｌ１７は上。As shown in FIG. 2, the center conductor wire llll17 is on the top.
下側接地導体６，８に非常に近接し、また、その上、下
側絶縁体１０，９の比誘電率を変化させることで伝送線
路の特性インピーダンスを変化させることが可能となる
。By being very close to the lower ground conductors 6, 8, and in addition changing the dielectric constant of the lower insulators 10, 9, it is possible to change the characteristic impedance of the transmission line.
以上説明したように、この発明は、半絶縁性化合物半導
体基板上に下側接地導体を設け、この上に中心導体線路
を、下側絶縁体を介して形成し、中心導体線路に接触し
ないように上側接地導体を、上側絶縁体を介して中心導
体線路を取り囲むように形成したので、中心導体線路の
線路幅を拡げずに低い特性インピーダンス線路が実現で
き、集積回路の高４Ａ積化が図れる効果がある。As explained above, the present invention provides a lower ground conductor on a semi-insulating compound semiconductor substrate, forms a center conductor line thereon through a lower insulator, and prevents contact with the center conductor line. Since the upper ground conductor is formed to surround the center conductor line via the upper insulator, a low characteristic impedance line can be realized without increasing the line width of the center conductor line, and a high 4A integration of the integrated circuit can be achieved. effective.
第１図はこの発明の一実施例を示す伝送線路の上面図、
第２図は、第１図のＡ−Ａ断面図、第３図は従来の伝送
線路の上面図、第４図は、第３図の１３−Ｂ断面図であ
る。
図において、１は半絶縁性化合物半導体基板、６は下側
接地等体、７は中心導体線路、８は上側接地導体、９は
下側絶縁体、１０は上側絶縁体である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
第２図
］０：よｇｊ潤種怪
第３図FIG. 1 is a top view of a transmission line showing an embodiment of the present invention;
2 is a sectional view taken along line AA in FIG. 1, FIG. 3 is a top view of a conventional transmission line, and FIG. 4 is a sectional view taken along line 13-B in FIG. In the figure, 1 is a semi-insulating compound semiconductor substrate, 6 is a lower ground conductor, 7 is a center conductor line, 8 is an upper ground conductor, 9 is a lower insulator, and 10 is an upper insulator. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2] 0: Yogj Junshukai Figure 3
Claims (1)
この上に中心導体線路を、下側絶縁体を介して形成し、
前記中心導体線路に接触しないように上側接地導体を、
上側絶縁体を介して前記中心導体線路を取り囲むように
形成したことを特徴とする伝送線路。A lower ground conductor is provided on the semi-insulating compound semiconductor substrate,
A center conductor line is formed on this via the lower insulator,
Connect the upper ground conductor so that it does not touch the center conductor line,
A transmission line, characterized in that the transmission line is formed so as to surround the center conductor line via an upper insulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61292719A JPS63144603A (en) | 1986-12-09 | 1986-12-09 | Transmission line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61292719A JPS63144603A (en) | 1986-12-09 | 1986-12-09 | Transmission line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63144603A true JPS63144603A (en) | 1988-06-16 |
Family
ID=17785427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61292719A Pending JPS63144603A (en) | 1986-12-09 | 1986-12-09 | Transmission line |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63144603A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0393606A (en) * | 1989-09-04 | 1991-04-18 | Shinku Yakin Kk | Method and device for forming thick film of high temperature superconductor |
| US6075423A (en) * | 1997-11-26 | 2000-06-13 | Intel Corporation | Controlling signal trace characteristic impedance via a conductive epoxy layer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5873138A (en) * | 1981-10-27 | 1983-05-02 | Toshiba Corp | Microwave amplifier |
| JPS6177402A (en) * | 1984-09-21 | 1986-04-21 | Toyo Commun Equip Co Ltd | Matching network device |
-
1986
- 1986-12-09 JP JP61292719A patent/JPS63144603A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5873138A (en) * | 1981-10-27 | 1983-05-02 | Toshiba Corp | Microwave amplifier |
| JPS6177402A (en) * | 1984-09-21 | 1986-04-21 | Toyo Commun Equip Co Ltd | Matching network device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0393606A (en) * | 1989-09-04 | 1991-04-18 | Shinku Yakin Kk | Method and device for forming thick film of high temperature superconductor |
| US6075423A (en) * | 1997-11-26 | 2000-06-13 | Intel Corporation | Controlling signal trace characteristic impedance via a conductive epoxy layer |
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