JPS60124851A - Microwave integrated circuit device - Google Patents

Microwave integrated circuit device

Info

Publication number
JPS60124851A
JPS60124851A JP58232366A JP23236683A JPS60124851A JP S60124851 A JPS60124851 A JP S60124851A JP 58232366 A JP58232366 A JP 58232366A JP 23236683 A JP23236683 A JP 23236683A JP S60124851 A JPS60124851 A JP S60124851A
Authority
JP
Japan
Prior art keywords
circuit
conductor
transmission line
semiconductor substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58232366A
Other languages
Japanese (ja)
Other versions
JPH0624223B2 (en
Inventor
Susumu Uehashi
上橋 進
Katsuhiko Mishima
三島 克彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58232366A priority Critical patent/JPH0624223B2/en
Publication of JPS60124851A publication Critical patent/JPS60124851A/en
Publication of JPH0624223B2 publication Critical patent/JPH0624223B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6627Waveguides, e.g. microstrip line, strip line, coplanar line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1903Structure including wave guides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Waveguides (AREA)

Abstract

PURPOSE:To form a passive circuit element having a circuit parameter within a wide range by forming a transmission line section in a strip conductor constituting a circuit element and the transmission line to the upper section of a section where there is no conductor film. CONSTITUTION:With a monolithic microwave integrated circuit 15, metallic films (conductor films) 17a, 17b as grounding conductors are shaped on a semi-insulating semiconductor substrate 16 at a regular interval, an insulating film (a dielectric film) 19 is formed, and a strip conductor 20 constituting a circuit element and a transmission line is shaped so that the transmission line section is positioned at the upper section of a slot 18. The variance range of characteristics impedance by the adjustment of the width of the slot 18 is very large, and inductance and capacitance having a circuit parameter within a wide range can be formed even when each circuit element is shaped by the strip conductor 20 by a distributed parameter circuit.

Description

【発明の詳細な説明】 〔発明の技術分野〕 マイクロ波帯において使用され、絶縁性または半絶縁性
半導体基板上に集積回路を形成し九マイクロ波集積回路
装置に関する。
TECHNICAL FIELD OF THE INVENTION The present invention relates to a microwave integrated circuit device for use in the microwave band, forming an integrated circuit on an insulating or semi-insulating semiconductor substrate.

〔発明の技術的背景〕[Technical background of the invention]

周知のように、マイクロ波集積回路にあっては、特性の
均−化及び小型化を目的として、ハイブリット型マイク
ロ波集積回路から絶縁性または半絶縁性半導体基板上に
能動索子及び受動素子を形成して電子回路を構成したモ
ノリシックマイクロ波集積回路(以下MMICと略す)
へ移行されつつある。
As is well known, in microwave integrated circuits, active elements and passive elements are fabricated on insulating or semi-insulating semiconductor substrates from hybrid microwave integrated circuits for the purpose of equalizing characteristics and downsizing. Monolithic microwave integrated circuit (hereinafter abbreviated as MMIC) formed to form an electronic circuit
is being transitioned to.

第1図は従来のMMICの基本構造を示すものである。FIG. 1 shows the basic structure of a conventional MMIC.

すなわち、図中符号11はQaAs (、fリウム・ヒ
素)半絶縁性半導体基板で、この半導体基板11の上面
部には動作層でなるFET12等の回路素子や伝送線路
を構成するストリップ導体13が形成され、下面部には
接地導体となるストリッグ線路14が形成されている。
That is, the reference numeral 11 in the figure is a QaAs (f lium arsenide) semi-insulating semiconductor substrate, and on the upper surface of this semiconductor substrate 11 are circuit elements such as an FET 12 which is an active layer, and strip conductors 13 which constitute a transmission line. A string line 14, which serves as a ground conductor, is formed on the lower surface.

ここで、上記のような構造を有するMMICにおいて、
マイクロ波回路を構成する方法には、集中定数回路を用
いる方法と分布定数回路を用いる方法とがある。
Here, in the MMIC having the above structure,
There are two methods for constructing a microwave circuit: a method using a lumped constant circuit and a method using a distributed constant circuit.

まず、上記集中定数回路は、上記半導体装置ノ1上に導
体膜及び絶縁膜を所望の特性を有する回路ノ母ターンに
して形成するようにしたものである。この集中定数回路
の回路素子には、例えば第2図(a)に示すように導体
膜A、を螺旋状の回路/?ターンにしたスフ2イラル形
インダクタ、第2図(blに示すように導体膜A i 
、 A sをそれぞれ所定の間隙を設けてくし形の回路
・母メーンにしたくし形キャパシタ及び第2図(c)に
示すように導体膜A4 、A、間に絶縁性薄膜Bを形成
したオーバレイキャノやシタ等がある。このような集中
定数回路素子は、波長に比べて十分小さく形成できると
いう利点を有している。
First, the lumped constant circuit is formed on the semiconductor device No. 1 by using a conductor film and an insulating film as a circuit mother circuit having desired characteristics. For example, as shown in FIG. 2(a), the circuit elements of this lumped constant circuit include a conductor film A and a spiral circuit/? A conductive film A i as shown in Fig. 2 (bl)
, A s as a comb-shaped circuit/mother main with predetermined gaps, and an overlay capacitor with an insulating thin film B formed between conductor films A4 and A as shown in FIG. 2(c). and shita, etc. Such a lumped constant circuit element has the advantage that it can be formed sufficiently small compared to the wavelength.

一方、上記分布定数回路は、前記ストリップ導体13で
なる伝送線路の特性インピーダンスや電気長を変えるこ
とによって、インダクタンスやキヤt+シクンスを形成
するようにしたものである。つまり、第3図にその一例
を示して説明すると、第3図(a)に示すようなLC回
路は、第3図(b)に示すよりに構成することができる
。すなわち、ストリップ導体130幅を一部狭めること
によって高“・ν特性インピーダンスとなる線路13a
〜13cでインダクタンスL a = L cを形成し
、ストリップ導体13の幅を拡げることによって低い特
性インピーダンスとなる線路13d、13e”t’キヤ
i4シタンスcd、Ceを形成することができる。この
場合、上記インダクタンスL a ” Lcでなる直列
インダクタンスをL1上記キャノやシタンスcd、Ce
でなる並列キャパシタンスをCとし、特性インピーダン
スzO及び伝送線路長!で構成したときの直列リアクタ
ンスX及び並列サセプタンスBは次式で近似されること
が知られている。
On the other hand, the distributed constant circuit is configured to form an inductance or a capacitance t+sequence by changing the characteristic impedance and electrical length of the transmission line made of the strip conductor 13. That is, to explain an example with reference to FIG. 3, the LC circuit as shown in FIG. 3(a) can be constructed as shown in FIG. 3(b). That is, by partially narrowing the width of the strip conductor 130, the line 13a has a high "·ν characteristic impedance.
By forming an inductance L a = L c with ~13c and widening the width of the strip conductor 13, it is possible to form lines 13d, 13e"t' capacitance cd, Ce having a low characteristic impedance. In this case, The series inductance consisting of the above inductance L a " Lc
Let C be the parallel capacitance, and the characteristic impedance zO and the transmission line length! It is known that the series reactance X and parallel susceptance B when configured as follows are approximated by the following equations.

(但しλは線路波長)・・・・・・・・・・・・・・・
・・・(1)〔背景技術の問題点〕 しかしながら、上記のように構成される従来のMMIC
では、以下のような欠点を有している。
(However, λ is the line wavelength) ・・・・・・・・・・・・・・・
...(1) [Problems with the background art] However, the conventional MMIC configured as described above
However, it has the following drawbacks.

まず、上記集中定数回路素子を形成する場合、大きな回
路ノ4ラメータを有する回路素子を作ることが困難であ
り、例えば18 COH2)においてスパイラル形イン
ダクタは10〔nH〕、くし形キャパシタはo、5(p
p)程度が限界である。
First of all, when forming the lumped constant circuit element mentioned above, it is difficult to make a circuit element having a large circuit and 4 parameters. (p
p) Degree is the limit.

また、オーバレイキャノfシタは大きな容量値を有する
ことができるものであるが、導体膜間に絶縁性薄膜を形
成するために萬度なノロセス技術が必要である。
Further, although the overlay capacitor can have a large capacitance value, a reliable process technique is required to form an insulating thin film between the conductor films.

次に、上記分布定数回路素子を形成する場合、(1)式
から明らかなように、広範囲のインダクタンスやキャノ
4シタンスを得るためには、伝送線路の特性インピーダ
ンスを広範囲で変えなければならない。例えば、GaA
s半絶縁性半導体基板に形成したマイクロストリップ線
路において、ストリップ導体の幅Wと基板厚Hとの比に
対する特性インピーダンスZoは第4図に示すような特
性となる。つまり、ストリップ導体の幅Wが1〔13以
上と極めて大きい領域では、回路の小屋化というMMI
C本来の目的に反するほど回路が大きくなってしまう。
Next, when forming the above-mentioned distributed constant circuit element, as is clear from equation (1), in order to obtain a wide range of inductance and capacitance, the characteristic impedance of the transmission line must be varied over a wide range. For example, GaA
In a microstrip line formed on a semi-insulating semiconductor substrate, the characteristic impedance Zo with respect to the ratio of the width W of the strip conductor to the substrate thickness H has a characteristic as shown in FIG. In other words, in areas where the width W of the strip conductor is extremely large, such as 1 [13 or more], MMI, which is called a circuit hut,
C The circuit becomes so large that it goes against the original purpose.

また、導体幅Wが10〔μ扉〕以下と極めて小さい領域
では導体損が増大し、伝搬損が大きくなって使用できな
い。
Further, in a region where the conductor width W is extremely small, such as 10 [μ doors] or less, conductor loss increases and propagation loss increases, making it unusable.

したがって、使用するのに適当な基板厚H(例えば10
0〜400〔μm〕)に対して実現可能なW/Hは、0
,1〜2.0程度に定まり、線路の特性インピーダンス
zOは約20〜120〔Ω〕に限定されてしまう。
Therefore, the appropriate substrate thickness H (for example, 10
0 to 400 [μm]), the achievable W/H is 0
, 1 to 2.0, and the characteristic impedance zO of the line is limited to about 20 to 120 [Ω].

ここで、上記基板厚Hに対する波長当りの伝搬損失につ
いて、上記GaA@牛絶縁性半導体基板について想定し
た計算値を第5図に示して説明する(但し、基板比抵抗
ρ=IX10[:Ω・為〕。
Here, the propagation loss per wavelength with respect to the substrate thickness H will be explained by showing the calculated values assumed for the GaA insulating semiconductor substrate in FIG. 5 (substrate specific resistance ρ=IX10[:Ω・[For].

基板比誘電率gr=12.5の場合)。すなわち、%i
インピーダンス50〔Ω〕の伝搬損失は、厚さ0.21
1:fl)以下の薄い基板で急激に増大してしまうばか
りでなく、GaA−基板の薄い基板は壊れやすく取り扱
いが難しい。一方、厚い基板を用いた場合には、所望の
特性インピーダンスのマイクロストリップ線路の線路幅
が広くなり、微細な回路を形成するのに不適当である。
When the substrate relative dielectric constant gr=12.5). That is, %i
The propagation loss for an impedance of 50 [Ω] is 0.21 for a thickness of
Not only does it increase rapidly when the substrate is thinner than 1:fl), but the thin GaA-substrate is easily broken and difficult to handle. On the other hand, if a thick substrate is used, the line width of the microstrip line with the desired characteristic impedance becomes wide, making it unsuitable for forming fine circuits.

したがって、分布定数回路素子を形成する基板の厚さH
及び基板上に形成されるマイクロストリップ線路の特性
インピーダンスZoの許容範囲はかなり狭い範囲となっ
ている。
Therefore, the thickness H of the substrate forming the distributed constant circuit element
The allowable range of the characteristic impedance Zo of the microstrip line formed on the substrate is quite narrow.

以上述べたように、従来のMMICでは、集中定数回路
を使用した場合においても分布定数回路を使用した場合
においても、広範囲の回路ノfラメータを有する受動回
路妻子を形成することが困難であった。
As mentioned above, with conventional MMICs, it is difficult to form passive circuits with a wide range of circuit f parameters, whether using lumped constant circuits or distributed constant circuits. .

〔発明の目的〕[Purpose of the invention]

この発明は上記のような問題を改善するためになされた
もので、広範囲な回路/?ラメータの有する受動回路素
子を形成することのできる、極めて良好なマイクロ波集
積回路装置を提供することを目的とする。
This invention was made to improve the above-mentioned problems, and it can be applied to a wide range of circuits/? It is an object of the present invention to provide an extremely good microwave integrated circuit device that can form a passive circuit element included in a ramometer.

〔発明の概要〕[Summary of the invention]

すなわち、この発明によるマイクロ波集積回路装置は、
絶縁性または半絶縁性半導体基板と、この半導体基板上
の一部に形成され接地導体となる導体膜と、この導体膜
及び前記半導体基板上に形成される誘電体膜と、この誘
電体膜上に形成され回路素子及び伝送線路を構成するス
トリップ導体とを具備し、前記ストリップ導体の伝送線
路部分が前記半導体基板−ヒに直接誘電体膜を形成した
前記導体膜の不在部分上方に位置するようにしたことを
特徴とするものである。
That is, the microwave integrated circuit device according to the present invention has the following features:
An insulating or semi-insulating semiconductor substrate, a conductor film formed on a part of this semiconductor substrate and serving as a ground conductor, a dielectric film formed on this conductor film and the semiconductor substrate, and a dielectric film formed on this dielectric film. a strip conductor that is formed on the semiconductor substrate and constitutes a circuit element and a transmission line, and a transmission line portion of the strip conductor is located above a portion where the conductor film is not formed, where a dielectric film is directly formed on the semiconductor substrate. It is characterized by the following.

〔発明の実施例〕[Embodiments of the invention]

以下、第6図乃至第9図を参照してこの発明の一実施例
を詳細に説明する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 6 to 9.

第6図はこの発明に係るモノリシックマイクロ波集積回
路(MMIC) J sの基本構造を示すものである。
FIG. 6 shows the basic structure of a monolithic microwave integrated circuit (MMIC) Js according to the present invention.

丁なわち、このMMIC7sでは、半絶縁性半導体基板
16上に接地導体となる複数枚(図では2枚)の金属膜
(導体膜)1ya。
That is, in this MMIC 7s, a plurality of (two in the figure) metal films (conductor films) 1ya are provided on the semi-insulating semiconductor substrate 16 to serve as ground conductors.

17bが、それぞれ所定の間隔を設けて形成されている
。そして、この金属膜17a、Ilb及び上記半導体基
板16上の金属膜不在部分(スロット)18の上には、
絶縁膜(誘電体膜)19が形成され、さらにこの絶縁膜
19上にはストリップ導体20が形成されている。この
ス) IJツブ導体20は、回路素子及び電送線路を構
成するもので、特にこのストリップ導体20の電送線路
部分は上記スロット18の上方に形成されるようになさ
れている。
17b are formed at predetermined intervals. Then, on the metal films 17a, Ilb and the metal film absent portion (slot) 18 on the semiconductor substrate 16,
An insulating film (dielectric film) 19 is formed, and a strip conductor 20 is further formed on this insulating film 19. The IJ tube conductor 20 constitutes a circuit element and a power transmission line, and in particular, the power transmission line portion of this strip conductor 20 is formed above the slot 18.

このようなMMICJ sは、一般に第7図に示すよう
に、接地導体でなる容器21に配設して使用されるが、
この場合上記MMICJ sの金属膜17&、l’lb
は、それぞれ容器21の接地導体と導線22& 、22
bで接続される。
Such MMICJs are generally used by being placed in a container 21 made of a grounded conductor, as shown in FIG.
In this case, the metal film 17&, l'lb of the above MMICJ s
are the grounding conductor of the container 21 and the conducting wires 22&, 22, respectively.
Connected at b.

つまり、上記のように構成したMMIo 15は、半絶
縁性半導体基板16の厚さに拘らず、ストリップ導体2
0及びスロット18のそれぞれの幅を調整することによ
り、数オームから数百オームまでの特性インピーダンス
を有する伝送線路を形成し得るものである。すなわち、
スロット18を形成しないとき伝送線路の特性インピー
ダンスは最低となり、スロット18の幅を十分大きくす
ると容器21の接地導体とMMIC15のストリップ導
体20とで伝送線路が構成され、これによって特性イン
ピーダンスが高くなるからである。
In other words, the MMIo 15 configured as described above is capable of connecting the strip conductor 2 regardless of the thickness of the semi-insulating semiconductor substrate 16.
By adjusting the respective widths of the slot 0 and the slot 18, a transmission line having a characteristic impedance ranging from several ohms to several hundred ohms can be formed. That is,
When the slot 18 is not formed, the characteristic impedance of the transmission line is the lowest, and if the width of the slot 18 is made sufficiently large, the transmission line is constituted by the ground conductor of the container 21 and the strip conductor 20 of the MMIC 15, thereby increasing the characteristic impedance. It is.

このように、スロット18の幅の調整による特性インピ
ーダンスの可変範囲は、従来のマイクロストリップ線路
やコゾレーナ線路における特性インピーダンスの可変範
囲に比べて極めて太きいもので、このため前述した分布
定数回路により上記ストリップ導体20で各回路素子を
形成した場合にも、広範囲な回路ノ4ラメーメを有する
インダクタンスやキャパシタンスを形成し得るようにな
る。
In this way, the range in which the characteristic impedance can be varied by adjusting the width of the slot 18 is extremely wide compared to the range in which the characteristic impedance can be varied in conventional microstrip lines or cosolena lines. Even when each circuit element is formed using the strip conductor 20, inductance and capacitance having a wide range of circuit characteristics can be formed.

また、第8図に示すように、上記MMICJ sは金属
膜17&の上方の絶縁膜19上に、ストリップ導体20
を延長して金属膜によりキャパシタ電極22を形成する
と、絶縁膜19を介して上記キャパシタ電極22と金属
膜17aとの間に容易に太きl容量値を有するキャパシ
タンスを作ることが可能となる。さらに、上記金属膜1
7&の上方の絶縁膜19上に形成したストリップ導体2
0でオープンスタブ23を構成すると、線路の特性イン
ピーダンスを極めて低くでき、大きな容量値を有する分
布定数形並列キャΔシタンスを作ることが可能となる。
Further, as shown in FIG. 8, the MMICJ s has a strip conductor 20 on the insulation film 19 above the metal film 17&
If the capacitor electrode 22 is formed by extending the metal film, it becomes possible to easily create a capacitance having a large capacitance value between the capacitor electrode 22 and the metal film 17a via the insulating film 19. Furthermore, the metal film 1
Strip conductor 2 formed on the insulating film 19 above 7&
When the open stub 23 is configured with 0, the characteristic impedance of the line can be made extremely low, and a distributed constant type parallel capacitance having a large capacitance value can be created.

ところで、マイクロ波集積回路では、マイクロ波回路を
構成する所望の回路パターンと接地導体とを接続する必
要がある。この場合、従来のマイクロ波集積回路では、
半絶縁性半導体基板を貫通するピアホールを形成して、
その基板上に形成した回路ノやターンと基板の裏面に形
成した接地導体とを接続するようにしていたため、接続
部分に寄生インダクタンスが生じたり、特に厚い基板の
場合にはエツチングにより穴を形成するのでピアホール
の径が大きくなる等の問題があった。ところが、上記の
ように構成したMMIC7sでは、第9図に示すように
、エツチングにより絶縁膜19に小径の穴をあけて内側
面に金属膜を形成したスルーホール(又はピアホール)
24を設けることにより、容易に所望の回路ノ臂ターン
を形成したストリップ導体20と接地導体となる金属膜
171Lとの接続が可能となる。そして、半絶縁性半導
体基板16に比1 べて絶縁膜19が十分に薄いので、従来のような問題を
ほとんど生じ得ないものとなる。
By the way, in a microwave integrated circuit, it is necessary to connect a desired circuit pattern constituting the microwave circuit to a ground conductor. In this case, in a conventional microwave integrated circuit,
By forming a peer hole that penetrates a semi-insulating semiconductor substrate,
Since the circuits and turns formed on the board were connected to the ground conductor formed on the back of the board, parasitic inductance occurred at the connection part, and holes were formed by etching, especially in the case of thick boards. Therefore, there were problems such as the diameter of the pier hole becoming large. However, in the MMIC 7s configured as described above, as shown in FIG. 9, a through hole (or pier hole) is formed by etching a small diameter hole in the insulating film 19 and forming a metal film on the inner surface.
By providing the strip conductor 24, it becomes possible to easily connect the strip conductor 20 formed with the desired circuit arm turn to the metal film 171L which becomes the ground conductor. Furthermore, since the insulating film 19 is sufficiently thinner than the semi-insulating semiconductor substrate 16, problems like those of the prior art are unlikely to occur.

したがって、上記のように構成したMMIC15は、半
導体基板16の厚さによらず、広範囲な特性インピーダ
ンスを有する伝送線路を形成することができるばかりで
なく、集中定数回路及び分布定数回路でそれぞれ回路素
子を形成したとき大きな回路パラメータを持たせること
が可能であり、さらに回路)4?ター/と接地導体とを
容易にかつ精度良く接続できるものである。
Therefore, the MMIC 15 configured as described above not only can form a transmission line having a wide range of characteristic impedances regardless of the thickness of the semiconductor substrate 16, but also can form circuit elements in lumped constant circuits and distributed constant circuits. It is possible to have large circuit parameters when forming a circuit) 4? The ground conductor can be easily and precisely connected to the ground conductor.

尚、上記実施例では半絶縁性半導体基板を用いて説明し
たが、絶縁性半導体基板を用いた場合でも同様に実施可
能である。
Although the above embodiments have been described using a semi-insulating semiconductor substrate, the same implementation is possible even when an insulating semiconductor substrate is used.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、広範囲な回路ノ9ラメ
ータを有する受動回路素子な容易に形成することができ
、さらに回路パターンと接地導体とを簡単に接続できる
、極めて良好なマイクロ波集積回路装置を提供すること
ができる。
As described above, according to the present invention, an extremely good microwave integrated circuit can be provided, in which passive circuit elements having a wide range of circuit parameters can be easily formed, and furthermore, the circuit pattern and the ground conductor can be easily connected. equipment can be provided.

2

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のマイクロ波集積回路装置の基本構造を示
す斜視図、第2図(al〜(e)はそれぞれ集中定数回
路の回路素子のノ等ターンを示す平面図、第3図(!L
) 、 (b)はそれぞれ分布定数回路の各回路素子の
ノ千ターンを説明するための回路図及び平面図、第4図
はマイクロストリップ線路の線路幅と基本厚に対する特
性インピーダンスの特性を示す特性図、第5図はマイク
ロストリップ線路の基板厚に対する伝搬損失を説明する
ための特性図、第6図はこの発明に係るマイクロ波集積
回路装置の一実施例を示す基本構成図、第7図乃至第9
図はそれぞれ上記実施例の使用例を示す構成図である。 11.16・・・半絶縁性半導体基板、12・・・FE
T、IJ・・・ストリップ導体、14・・・ストリッグ
線路、15・・・モノリシックマイクロ波集積回路(M
MIC)、zy・・・金属膜、18・・・スロット、1
9・・・絶縁膜、2o・・・ストリップ導体、21・・
・容器、22・・・キャノ4シタ電極、23・・・オー
プンスタブ、24・・・スルーホール。 出願人代理人 弁理士 鈴 江 武 彦第1図 第2図 (a) (b) (C) 第3図 第6図 第4閏 0.04 0.+ 0.2 0.40.6to 2.0
 4.OW/H 第5図 第8閉
FIG. 1 is a perspective view showing the basic structure of a conventional microwave integrated circuit device, FIG. L
) and (b) are a circuit diagram and a plan view to explain the number of turns of each circuit element of a distributed constant circuit, respectively, and Figure 4 is a characteristic showing the characteristic impedance characteristics with respect to the line width and basic thickness of a microstrip line. 5 is a characteristic diagram for explaining propagation loss with respect to substrate thickness of a microstrip line, FIG. 6 is a basic configuration diagram showing an embodiment of a microwave integrated circuit device according to the present invention, and FIGS. 9th
Each figure is a configuration diagram showing an example of use of the above embodiment. 11.16... Semi-insulating semiconductor substrate, 12... FE
T, IJ... Strip conductor, 14... String line, 15... Monolithic microwave integrated circuit (M
MIC), zy...Metal film, 18...Slot, 1
9... Insulating film, 2o... Strip conductor, 21...
- Container, 22... Cano 4-side electrode, 23... Open stub, 24... Through hole. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 (a) (b) (C) Figure 3 Figure 6 Leap 0.04 0. + 0.2 0.40.6to 2.0
4. OW/H Fig. 5 8 Closed

Claims (1)

【特許請求の範囲】[Claims] 絶縁性または半絶縁性半導体基板と、この半導体基板上
の一部に形成され接地導体となる導体膜と、この導体膜
及び前記半導体基板上に形成される誘電体膜と、この誘
電体膜上に形成され回路素子及び伝送線路を構成するス
トリップ導体とを具備し、前記ストリップ導体の伝送線
路部分が前記半導体基板上に直接誘電体膜を形成した前
記導体膜の不在部分上方に位置するようにしたことを特
徴とするマイクロ波集積回路装置。
An insulating or semi-insulating semiconductor substrate, a conductor film formed on a part of this semiconductor substrate and serving as a ground conductor, a dielectric film formed on this conductor film and the semiconductor substrate, and a dielectric film formed on this dielectric film. a strip conductor that is formed to constitute a circuit element and a transmission line, such that a transmission line portion of the strip conductor is located above a portion where the conductor film is absent where a dielectric film is directly formed on the semiconductor substrate. A microwave integrated circuit device characterized by:
JP58232366A 1983-12-09 1983-12-09 Microwave integrated circuit device Expired - Lifetime JPH0624223B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58232366A JPH0624223B2 (en) 1983-12-09 1983-12-09 Microwave integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58232366A JPH0624223B2 (en) 1983-12-09 1983-12-09 Microwave integrated circuit device

Publications (2)

Publication Number Publication Date
JPS60124851A true JPS60124851A (en) 1985-07-03
JPH0624223B2 JPH0624223B2 (en) 1994-03-30

Family

ID=16938086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58232366A Expired - Lifetime JPH0624223B2 (en) 1983-12-09 1983-12-09 Microwave integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0624223B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63108756A (en) * 1986-10-25 1988-05-13 Shinko Electric Ind Co Ltd Package for ultrahigh frequency element
US5986331A (en) * 1996-05-30 1999-11-16 Philips Electronics North America Corp. Microwave monolithic integrated circuit with coplaner waveguide having silicon-on-insulator composite substrate
EP0973199A2 (en) * 1998-07-14 2000-01-19 Matsushita Electric Industrial Co., Ltd. Semiconductor device comprising a composite layer structure
CN108550969A (en) * 2018-05-25 2018-09-18 深圳市深大唯同科技有限公司 A kind of tunable dielectric integrated RF transmission line, coupler and feeding network
JP2022542833A (en) * 2019-08-02 2022-10-07 レイセオン カンパニー Vertical Serpentine Frequency Selective Limiter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123753A (en) * 1982-01-20 1983-07-23 Hitachi Ltd Semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123753A (en) * 1982-01-20 1983-07-23 Hitachi Ltd Semiconductor integrated circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63108756A (en) * 1986-10-25 1988-05-13 Shinko Electric Ind Co Ltd Package for ultrahigh frequency element
US5986331A (en) * 1996-05-30 1999-11-16 Philips Electronics North America Corp. Microwave monolithic integrated circuit with coplaner waveguide having silicon-on-insulator composite substrate
EP0973199A2 (en) * 1998-07-14 2000-01-19 Matsushita Electric Industrial Co., Ltd. Semiconductor device comprising a composite layer structure
EP0973199A3 (en) * 1998-07-14 2006-10-18 Matsushita Electric Industrial Co., Ltd. Semiconductor device comprising a composite layer structure
CN108550969A (en) * 2018-05-25 2018-09-18 深圳市深大唯同科技有限公司 A kind of tunable dielectric integrated RF transmission line, coupler and feeding network
JP2022542833A (en) * 2019-08-02 2022-10-07 レイセオン カンパニー Vertical Serpentine Frequency Selective Limiter

Also Published As

Publication number Publication date
JPH0624223B2 (en) 1994-03-30

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