JPS63144555A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS63144555A
JPS63144555A JP61291455A JP29145586A JPS63144555A JP S63144555 A JPS63144555 A JP S63144555A JP 61291455 A JP61291455 A JP 61291455A JP 29145586 A JP29145586 A JP 29145586A JP S63144555 A JPS63144555 A JP S63144555A
Authority
JP
Japan
Prior art keywords
layer
layers
conductivity type
regions
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61291455A
Other languages
Japanese (ja)
Other versions
JP2659941B2 (en
Inventor
Masaki Momotomi
正樹 百冨
Masashi Wada
和田　正志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61291455A priority Critical patent/JP2659941B2/en
Publication of JPS63144555A publication Critical patent/JPS63144555A/en
Application granted granted Critical
Publication of JP2659941B2 publication Critical patent/JP2659941B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To supply stable step-up voltage having a margin in a process manner by using two second conductivity type layers as an input terminal at high voltage and a first conductivity type layer as an output terminal and connecting the output terminal to the input terminal as the second conductivity type layers by employing the structure as a unit. CONSTITUTION:Phosphorus ions are implanted into N-well regions 62 on a P-type substrate 61, and N-well layers are formed through annealing. Field oxidation is conducted in order to isolate elements. Boron ions are implanted into P<+> regions, arsenic ions are implanted into N<+> regions, and both regions are annealed. Consequently, P<+> layers 63 and N<+> layers 64 are shaped. Inter- layer insulating films are each deposited, and contact holes are bored and an Al layer 65 is formed. N-wells are brought to 623X10<16>cm<-3>, P<+> layers to 632X10<17>cm<-3> and N<+> layers to 642X10<20>cm<-3> as final respective concentration. The junction breakdown strength of the P<+> layers 63 and the N<+> layers 64 at that time is brought to 7V. An output from a step-up circuit and an input Al layer 66 are connected, and final P<+> potential is brought to ground potential by an Al layer 67.

Description

【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） この発明は、半導体集積回路に関し、特に電気的書き込
み消去可能な不揮発生メモＩＪ　（ＢＢＦＲＯＭ）の高
電圧リミッタ回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit, and particularly to a high voltage limiter circuit for an electrically programmable and erasable non-volatile memory IJ (BBFROM).

（従来の技術） 従来より、ＥＥＦＲＯＭにおいては、メモリセルのフロ
ーティングゲートと、ドレイン間の薄い酸化膜に高電界
を与え、電子をトンネルさせて、フローティングゲート
の電荷量を変え、その“しきい値“を変えて、不揮発な
記憶を実現させている。(Prior art) Conventionally, in EEFROM, a high electric field is applied to a thin oxide film between the floating gate and drain of a memory cell, causing electrons to tunnel, changing the amount of charge on the floating gate, and increasing its "threshold value". “We are making non-volatile memory possible by changing the

そのために高電圧（通常２０Ｖ）が必要となる。This requires a high voltage (usually 20V).

最近では、外部より５ｖの電源電圧を与え、チップ内部
の昇圧回路により、高電圧を発生しているため、メモリ
セルの”しきい値”を一定にし、かつ、接合破壊や酸化
膜破壊を起こさないために昇圧電位を一定にするリミッ
タ回路が必要となってくる。内部昇圧回路とリミッタ回
路接続の従来例を第２図に示す。Recently, a power supply voltage of 5V is applied externally, and a booster circuit inside the chip generates a high voltage, which allows the "threshold value" of the memory cell to be constant and prevents junction breakdown and oxide film breakdown. Therefore, a limiter circuit is required to keep the boosted potential constant. A conventional example of the connection between the internal booster circuit and the limiter circuit is shown in FIG.

ＩＪ　ミッタ回路には第３図に示す様にトランジスタの
５ｕｒｆａｃｅ　Ｂｒｅａｋｄｏｗｎ電圧を利用してい
るものがある。これはＰ型基板（３１）上に、ｎ領域（
３２）に昇圧電位を入力とし、　Ｐｏ１ｙｓｉゲート（
３３）を接地電位にすることにより、５ｕｒｆａｃｅ　
ｂｒｅａｋｄｏｗｎ電圧で昇圧電位をリミットしようと
するものである。しかし、この構造ではブレイクダウン
後にゲート酸化膜（３４）に正孔がトラップされＷａｌ
ｋｏｕｔ　　するためにリミッタ電位が変化するという
欠点があった。さらにゲート酸化膜厚がばらつくとリミ
ッタ電位も変化するため安定な昇圧電位を供給できない
という欠点があった。他の方法として、リミッタ回路に
第４図に示されるＪｕｎｃｔｉｏｎ　Ｂｒｅａｋｄｏｗ
ｎ　　電圧を利用しているものがある。Some IJ emitter circuits utilize the 5 surface breakdown voltage of a transistor as shown in FIG. This is an n-region (
32), the boosted potential is input to the Polysi gate (
By setting 33) to ground potential, 5urface
This attempts to limit the boosted potential using the breakdown voltage. However, in this structure, holes are trapped in the gate oxide film (34) after breakdown and Wal
There is a drawback that the limiter potential changes due to kout. Furthermore, if the thickness of the gate oxide film varies, the limiter potential also changes, so a stable boosted potential cannot be supplied. Another method is to use a limiter circuit with a junction breakdown as shown in FIG.
There are some that use n voltage.

これはＰ型基板（４１）Ｊ：に、ｎ層（４２）とｐ一層
（８）を形成することにより１層の濃度を最適化し、ｎ
層とｐ一層のＪｕｎｃｔｉｏｎ　Ｂｒｅａｋｄｏｗ１電
圧を２０Ｖ程度にし。This is achieved by optimizing the concentration of the first layer by forming an n layer (42) and a p layer (8) on a p-type substrate (41) J:.
The junction breakdown voltage of the layer and the p-layer is set to about 20V.

リミッタ電位を一定にしようとするものである。This is intended to keep the limiter potential constant.

しかし、これだと、第５図に示す様に接合耐圧を２０Ｖ
に設定しようとすると、熱工程の変化、ｐ濃度の変化に
対して、接合耐圧の変化量が大きいため、最適化するの
が困難であるという欠点があった。これによるとｐ−濃
度がＺ５Ｘ１０　ｃｍ　　から１．５Ｘ１０ｃｒｎ　に
変化するだけで耐圧が３０Ｖから４０ＶとＩＯＶも変化
する。第５図は８．Ｍ、ＳＺＢらの文献（Ａｐｐｌ、Ｐ
ｈｙＳ、Ｌｅｔｔ、、８．１１１（１９６６）　）から
引用している。However, with this, the junction breakdown voltage is 20V as shown in Figure 5.
However, there is a drawback that it is difficult to optimize the junction breakdown voltage due to changes in the thermal process and p concentration because the amount of change in the junction breakdown voltage is large. According to this, just by changing the p- concentration from Z5×10 cm to 1.5×10 crn, the IOV also changes from 30 V to 40 V. Figure 5 shows 8. M, SZB et al. (Appl, P
hyS, Lett, 8.111 (1966)).

（発明が解決しようとする問題点） 本発明は上記欠点を鑑み、安定でプロセスマージンの太
きいリミッタ回路を提供し、安定な昇圧電位を供給・し
ようとするものである。(Problems to be Solved by the Invention) In view of the above drawbacks, the present invention provides a limiter circuit that is stable and has a large process margin, and supplies a stable boosted potential.

〔発明の構・成〕[Structure/formation of the invention]

Ｃ問題を解決するための手段） 本発明のリミッタ回路を第１図（ａ）に示す。Ｐ型半導
体基板（１１）上に第１．第２．第３のＮ−ｗｅｌｌ層
（１２゜１３．１４）を形成し、それぞれにｐ層（１５
，１６，１７）を形成し、それぞれのｐ層の中にｎ層（
１８，１９，２０）とＮ−ｗｅｌｌ層に電位を与えるた
めのｎ層（２１，２２，２３）を形成し、第１のＮ−ｗ
ｅｌｌ（１２）中のｎ層（２１，１８）を高電圧の入力
端（２４）とし、第１のｐ　Ｍ（Ｔｏ）と第２のＮ−ｗ
ｅ　１１　（１３）中のｎ層（１９，２２）を接続（２
５）Ｌ、１２＋ のｐ層（１６）と第３のＮ−ｗｅ　ｌ　ｌ　（１４）中
のｎ層（２０，２３）を接続（２６）ｌ、、第３のｐ層
（１７）を痩地電位（２７）にすることにより、リミッ
タ回路を形成する。Means for Solving Problem C) A limiter circuit of the present invention is shown in FIG. 1(a). A first layer is formed on the P-type semiconductor substrate (11). Second. A third N-well layer (12° 13.14°) is formed, and a p layer (15°
, 16, 17), and an n-layer (
18, 19, 20) and an n layer (21, 22, 23) for applying a potential to the N-well layer.
The n-layer (21, 18) in the ell (12) is used as a high voltage input terminal (24), and the first pM(To) and the second N-w
e 11 Connect the n layer (19, 22) in (13) (2
5) Connect the p-layer (16) of L, 12+ and the n-layer (20, 23) in the third N-well (14) (26), thin the third p-layer (17). By setting it to earth potential (27), a limiter circuit is formed.

（°作用） 第１図（ａ）を用いて作用を説明する。Ｎ−ＷＣｌ２層
（１２，１３，１４）、１）層（１５，１６，１７）ｎ
＋＊（１ｓ、ｘ　　９　、ｚｏ、ｚｔ、２２　、ｉ３）
はそれぞれ同一工程で形成されるために濃度はすべて同
一となっている。接合耐圧はｐ層とｐ層中の＋ ｎ層によって決まっており、それぞれ接合耐圧が７Ｖ程
度になる様に設定されている。第５図に示す様に接合耐
圧が７Ｖの場合には、熱工程の変化。(° Effect) The effect will be explained using FIG. 1(a). N-WCl2 layer (12, 13, 14), 1) layer (15, 16, 17) n
+*(1s, x 9 , zo, zt, 22 , i3)
Since they are formed in the same process, they all have the same concentration. The junction breakdown voltage is determined by the p layer and the +n layer in the p layer, and each is set so that the junction breakdown voltage is about 7V. As shown in Figure 5, when the junction breakdown voltage is 7V, the thermal process changes.

イオン注入のドーズ量による変化に対して、接合耐圧の
バラツキが、第４図で２０Ｖの接合耐圧によるバラツキ
よりも、はるかに小さく安定であることがわかる。It can be seen from FIG. 4 that the variation in the junction breakdown voltage is much smaller and more stable than the variation due to the junction breakdown voltage of 20 V with respect to changes due to the dose of ion implantation.

またＮ−ｗｅｌｌの電位とｎ層の電位が同一であるため
に、ｐ層中のｎとＮ−ｗｅｌｌがパンチスルーを行なっ
ても問題にならない。また同電位であるためにバイポー
ラトランジスタを形成しても問題にならない。Further, since the potential of the N-well and the potential of the n-layer are the same, there is no problem even if the n-well in the p-layer and the n-well punch through. Furthermore, since the potentials are the same, there is no problem even if a bipolar transistor is formed.

１つあたりの接合耐圧が７ｖであるため、これを３段直
列に接続しているために、リミッタ電圧は７ＶＸ３＝２
１Ｖとなる。したがって昇圧電位が２１Ｖを越えると直
流パスが入力端子（２４）から接地電位（２７）に流れ
るため、昇圧電位は２１Ｖにｌ１ｗ１ｔされる。Since the junction breakdown voltage per unit is 7V, since these are connected in series in three stages, the limiter voltage is 7VX3=2
It becomes 1V. Therefore, when the boosted potential exceeds 21V, the DC path flows from the input terminal (24) to the ground potential (27), so that the boosted potential is reduced to 21V.

第１図（ｂ）は同図（ａ）のリミッタ回路と昇圧回路の
接続を示す回路図である。FIG. 1(b) is a circuit diagram showing the connection between the limiter circuit and the booster circuit shown in FIG. 1(a).

（実施例） 本発明の実施例を第２図を参照して詳細に説明する。(Example) An embodiment of the present invention will be described in detail with reference to FIG.

２０ΩのＰ型基板（６１）上にＮ−ｗｅ　ｌ　１領域（
６２）ニリン１５０ＫｅＶ７．９　Ｘ　１０　ｃｍ　　
でイオン注入し、１１９０℃２００分のアニールを行な
いＮ−ｗｅｌｌ層を形成する。N-wel 1 area (
62) Nilin 150KeV7.9 X 10 cm
Ion implantation is performed at 1190° C. for 200 minutes to form an N-well layer.

次に素子分離を行なうための、フィールド酸化を行なう
（第２図ａ） 次にｒ領域ｌこ４０　ＫｅＶ　２　Ｘ　１０”ｃａｒ　
ｒボロンイオン注入し、さらにｎ領域に４０　ＫｅＶ５
Ｘ１０　ｃｍでヒ素をイオン注入し％　９００℃、３７
分のアニールを行なう。これによりｐ層（６３）、ｎ層
（６４）を形成する（第２図ｂ） さらに、それぞれ層間絶縁膜を堆積し、コンタクトホー
ルを開けＡｔ層（６５）を形成する（第２図Ｃ）最終的
なそれぞれの濃度はＮ−ｗｅｌｌ層（６２）３　Ｘ　１
０　ｃｍ一層（６３）　２Ｘ　１０　ａｎ　　、　ｎ層
（６４）２Ｘ１０ｍ　　　である。Next, field oxidation is performed to perform element isolation (Figure 2a). Next, the r region is 40 KeV 2
r boron ion implantation and further 40 KeV5 into the n region.
Arsenic was ion-implanted at 10cm x 900℃, 37%
Perform annealing for 1 minute. As a result, a p-layer (63) and an n-layer (64) are formed (Fig. 2b). Furthermore, an interlayer insulating film is deposited on each layer, and a contact hole is opened to form an At layer (65) (Fig. 2c). The final concentration of each is N-well layer (62) 3 x 1
0 cm single layer (63) 2X 10 an, n layer (64) 2X 10 m.

このときのｐ層（６３）とｎ層（６４）の接合耐圧は７
■である。昇圧回路の出力と、入力Ａｔ層（６６）を接
続し、最終のｐの電位はＡｔ層（６７）により接地電位
にする。At this time, the junction breakdown voltage between the p layer (63) and the n layer (64) is 7
■It is. The output of the booster circuit and the input At layer (66) are connected, and the final potential of p is set to the ground potential by the At layer (67).

基板としてはＳｔを用いたが、その他Ｇ　ｅ　、　Ｇａ
Ａｓ　。Although St was used as the substrate, other materials such as Ge, Ga
As.

ＧａＰ等でも同様である・ 〔発明の効果〕 本発明のリミッタ回路により、プロセス的にマージンの
ある、かつ安定な昇圧電位を供給することができた。The same applies to GaP, etc. [Effects of the Invention] The limiter circuit of the present invention was able to supply a stable boosted potential with a process margin.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ｆａ）は本発明のリミッタ回路の断面図、第１図
（ｂ）は昇圧回路とリミッタ回路の接続図、第２図は本
発明の実施例の工程断面図、第３図、第４図は夫々従来
のリミッタ回路の断面図、第５図はＪｕｎｃｔｉｏｎ　
Ｂｒｅａｋｄｏｗｎ電圧と濃度の関係を示す図である。 図において、 １−１・・・Ｐ型基板、　　１−２　、１−３　、１−
４・・・Ｎ−ｗｅｌｌ、　　ｌ−５、１−６、１−７＋
＋ｐ層、１−８゜１−９　、１−１０・９層中のｎＪｉ
ｉ、　１−１１．１−１２　、１−１３”・Ｎ−ｗｅｌ
ｌ電位を与えるｎ層、１−１４゜１−１５　、１−１６
・・・紅配線％３−１・・・Ｐ型基板、３−２　・ｎ層
、ａ　−３−・Ｐｏ１ｙｓｉ　Ｇａｔｅ　、　３−４　
”・Ｇａｔｅ　Ｓｉｎ、　、　４−１−　Ｐ型基板、４
−２−ｎ層。 ４−３・・・ｐ一層、６−１・・・Ｐ型基板、６−２・
・・Ｎ−ｗｅｌｌ層、６−３　・ｐ層、６−４−ｎｌ、
６−５・・・ＡＬ配線、６−６・・・昇圧電位入力部、
６−７・・・接地電位。 代理人　弁理士　則　近　憲　佑 同　　　　竹　花　喜久男 都″′″絡　（ｂ） 第１図 ｐ−５ｕｂ　　　　−一一一３１ 第３図 第４図 ρ−５Ｕｂ （ｂ） −５ｕｂ （ｃ） 第２図 第５図Fig. 1 (fa) is a sectional view of the limiter circuit of the present invention, Fig. 1 (b) is a connection diagram of the booster circuit and the limiter circuit, Fig. 2 is a process sectional view of the embodiment of the present invention, Figs. Figure 4 is a cross-sectional view of a conventional limiter circuit, and Figure 5 is a junction.
FIG. 3 is a diagram showing the relationship between Breakdown voltage and concentration. In the figure, 1-1...P-type substrate, 1-2, 1-3, 1-
4...N-well, l-5, 1-6, 1-7+
+p layer, 1-8゜1-9, nJi in 1-10・9 layer
i, 1-11.1-12, 1-13"・N-well
n layer giving l potential, 1-14°1-15, 1-16
...Red wiring%3-1...P type substrate, 3-2 ・n layer, a-3-・Polysi Gate, 3-4
”・Gate Sin, , 4-1- P type substrate, 4
-2-n layer. 4-3...P single layer, 6-1...P type substrate, 6-2...
・・N-well layer, 6-3 ・p layer, 6-4-nl,
6-5... AL wiring, 6-6... Boosted potential input section,
6-7...Ground potential. Agent Patent attorney Nori Ken Yudo Takehana Kikuoto ``'''' (b) Figure 1 p-5ub -11131 Figure 3 Figure 4 ρ-5Ub (b) -5ub (c) 2nd Figure 5

Claims (1)

【特許請求の範囲】[Claims] 第１導電型の半導体基板に第２導電型のウェルが形成さ
れ、このウェルの中に第１導電型層が形成され、この第
１導電型層の中に第１の第２導電型層が形成され前記ウ
ェルの中で前記第１導電型層の外に第２の第２導電型層
が形成され、前記第１、第２の第２導電型層を高電圧の
入力端子とし、前記第１導電型層を出力端子とし、この
構造を単位として、前記出力端子を前記第１、第２の第
２導電型層の入力端子と接続することにより前記構造が
直列に多段接続されていることを特徴とする半導体集積
回路A well of a second conductivity type is formed in a semiconductor substrate of a first conductivity type, a first conductivity type layer is formed in the well, and a first second conductivity type layer is formed in the first conductivity type layer. a second conductivity type layer is formed outside the first conductivity type layer in the well, the first and second second conductivity type layers are used as high voltage input terminals; One conductivity type layer is used as an output terminal, and the structures are connected in series in multiple stages by connecting the output terminal to the input terminals of the first and second second conductivity type layers, using this structure as a unit. A semiconductor integrated circuit characterized by
JP61291455A 1986-12-09 1986-12-09 Semiconductor integrated circuit Expired - Fee Related JP2659941B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61291455A JP2659941B2 (en) 1986-12-09 1986-12-09 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61291455A JP2659941B2 (en) 1986-12-09 1986-12-09 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS63144555A true JPS63144555A (en) 1988-06-16
JP2659941B2 JP2659941B2 (en) 1997-09-30

Family

ID=17769088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61291455A Expired - Fee Related JP2659941B2 (en) 1986-12-09 1986-12-09 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2659941B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0323898U (en) * 1989-07-17 1991-03-12
JPH0323897U (en) * 1989-07-17 1991-03-12

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5050559A (en) * 1973-08-24 1975-05-07
JPS546480A (en) * 1977-06-16 1979-01-18 Nippon Denso Co Ltd Semiconductor device
JPS58217023A (en) * 1982-06-10 1983-12-16 Sony Corp Power source circuit for ic

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5050559A (en) * 1973-08-24 1975-05-07
JPS546480A (en) * 1977-06-16 1979-01-18 Nippon Denso Co Ltd Semiconductor device
JPS58217023A (en) * 1982-06-10 1983-12-16 Sony Corp Power source circuit for ic

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0323898U (en) * 1989-07-17 1991-03-12
JPH0323897U (en) * 1989-07-17 1991-03-12

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