JPS63144494A - Refresh system for main memory - Google Patents

Abstract

PURPOSE:To prevent delay in access by using a cache comparator so as to compare the content of a tag memory with a high-order address when a low- order address is inputted and giving a refresh signal by a timer clock when the coincidence period continues for a prescribed period or over. CONSTITUTION:A cache memory 13 uses a cache comparator 15 to compare the contents of a tag memory 14 receiving a low-order address at a part of an address from a CPU 10 with the high-order address and a coincidence signal is outputted for high speed operation. A refresh signal is raised a the leading of the cache access signal and when the cache access signal has a prescribed time or over of interval, a refresh signal is caused by the refresh request signal by a timer clock. In this case, since no access is given to a DRAM 11 being the main memory, the refresh signal and the signal accessing the main memory 11 from the CPU 10 do not collide with each other. Thus, the retarded access is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a method for refreshing a main memory, particularly a circuit incorporating a cache memory for high-speed access to a dynamic RAM provided at low cost.

[Conventional technology]

Generally, an access method using a cache memory is executed by hardware as shown in the block diagram shown in FIG. That is, in Figure 3, 1 in the figure is C.
When an address is generated from CPU1, the lower address that is part of that address is input as the address of tag memory 2, and the contents of the tag memory and the upper address from CPU1 are compared by comparator 3. When compared, if they match, it means that the data exists in the high-speed cache memory 4, so the data is read at high-speed access. Furthermore, if they do not match, data is taken into the CPUI from the main memory 5 using the dynamic RAM by normal access, and the contents of the data are written into the cache memory 4 at that time. In addition, this access method using the cache memory 4 does not allow particularly high-speed access because normal access is used when writing.

In addition, in the method using this cache memory 4, the main memory 5 is usually a dynamic RA as described above.
Since M is used, it is necessary to perform refresh, but conventionally, this refresh method has been performed by using a timer and applying a refresh signal at regular intervals.

[Problem that the invention seeks to solve]

However, according to the refresh method in the access method that incorporates the cache memory as described above, there is a problem that the refresh signal may collide when accessing the main memory 5 from the CPU 1, resulting in slow access. there were.

Therefore, the present invention has been made by focusing on the problems of the related art, and it is an object of the present invention to solve these problems, avoid the refresh signal from colliding with the access from the CPU, and delay the access. The purpose is to provide a main memory refresh method that eliminates the

[Means for Solving the Problems] To achieve this objective, the main memory refresh method according to the present invention is based on the contents of the tag memory into which the lower address of the address from the CPU is input, and l; This comparator for cache compares addresses, and is characterized in that it provides a refresh signal every time there is a match, and provides a refresh signal by a timer clock when the match period is longer than a certain value.

[Effect]

By making the main memory refresh method fair as described above, if the cache comparator matches and the cache memory is operating at high speed, it will not be possible to access the dynamic RAM, which is the main memory. Therefore, if a refresh signal is applied at that time, the refresh signal and the signal for accessing the main memory from the CPU will not conflict with each other, thereby preventing slow access.

〔Example〕

Next, an example of the implementation of the present invention will be described in detail with reference to FIGS. 1 and 2.

Figure 1 is a block diagram of hardware for implementing an access method that takes advantage of only the advantages of the static column method in order to correct the problems of access methods using general cache memory. is CPU, 1
1 is a low-speed main memory using dynamic RAM. This main memory 11 is controlled by a memory control 12. Also, 1 in the figure
3 is a high-speed cache memory, and this cache memory 13 compares the contents of the tag memory 14, into which the lower addresses of some of the addresses from CPU10 are entered manually, with the upper addresses by a cache comparator 15, and a match signal is output. It is designed to operate at high speed. or,
Reference numeral 16 in the figure is an address Philip crop, and the address of the above-mentioned cache memory 13 at high speed operation is set in this address Philip crop 16, and the high speed operation is performed on the poem matched by the static column comparator 17 at the next access. be prepared to do so. Further, when a match signal is output from the static column comparator 17, high-speed operation is performed using the static column, but the data is also set in the cache memory 13 and prepared for the next access. In addition, 1 in the figure
8 is a selection circuit for selecting whether to use the cache memory 13 or a static column, and this selection circuit 18 sends a signal to the memory control 12 via a cache control 19 and a static column control 20. Moreover, FIG. 2 is a conceptual diagram showing the refresh operation signals necessary for the main memory 11 using dynamic RAM in such a circuit configuration, and A is a refresh request by the usual evening/r macro lock. In the present invention, the refresh signal is issued at the same time as the rise of the cache access signal, and the cache access signal is issued for a certain period of time or more. If it is left unused, a refresh signal is generated by a refresh request signal generated by a normal timer clock.

Note that the main memory refresh method according to the present invention is not limited to a circuit incorporating a static RAM method as shown in FIG. It goes without saying that the cache method shown in the figure also requires implementation.

〔Effect of the invention〕

As described above, according to the main memory refresh method according to the present invention, the CPU is not accessing the main memory when the cache is accessed, that is, when a match signal is output from the cache comparator. If seven refresh operations are performed, the refresh signal and the access signal from the CPU will not collide, and there will be no access delay.

[Brief explanation of the drawing]

Figure 1 is a circuit block diagram of the hardware on which the main memory refresh method according to the present invention is executed;
The figure is a conceptual diagram of signals representing the refresh timing, and FIG. 3 is a block diagram of a circuit incorporating a general cache memory. 10...CPU II...Main memory 13...Cache memory 14...Tag memory 15...Cache comparator

Claims (1)

[Claims] A cache comparator that compares the content of the tag memory into which the lower address from the CPU is input and the upper address. It gives a refresh signal each time they match, and when the matching period is longer than a certain value, a timer is activated. A main memory refresh method characterized by providing a clock-based refresh signal.