JPS6314397A - Storage circuit - Google Patents

Abstract

PURPOSE:To attain read/write by dividing row selection lines into two, and adding a rotary shift circuit, and a function detecting a maximum address, inhibiting the succeeding operation and starting an adjacent circuit to a row driving circuit driving the divided line so as to apply time division read/write to/from a memory element having plural consecutive addresses from a designated address. CONSTITUTION:Address information 65, '06' is stored from a host device to an address register 60 and a row address '0' is inputted to a row driving circuit 20 and a row driving circuit 30. The row driving control section 24 of the row driving circuit 20 receives a column address '6', it is decoded to be a low-order column selection address and in turning on a rotary shift circuit 23, the row driving selection circuit 22 selects/drives a row selection line 130 corresponding to next row address '1'. The row driving circuit 30 uses a row driving selection circuit 32 to select and drive a row selection line 130. In receiving an operating clock as one of control information 75 to a storage control section 70, the storage control section 70 starts the read corresponding to the operation clock in the write/read control section 80.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit, and more particularly to a memory circuit that can time-divisionally read or write memory elements at a plurality of consecutive addresses from a designated address.

[Conventional technology]

In recent years, as integrated circuits have progressed, random access memory circuits using semiconductors have been proposed that have increased storage capacity and a variety of functions. Among them, for a memory circuit that can read or write only 1 bit of information at a specified address, by simply applying multiple operating clocks in succession, it is possible to read or write only 1 bit of information at a specified address. A memory circuit has been proposed that can read or write information at an address in a time-division manner, and some are designed to operate the memory circuit efficiently.

As shown in Figure 5, this type of conventional memory circuit has 8 rows x 8 columns (8 rows x 8 columns in the case of IJ socks).
IJ Nox-like arrangement, each 0.1. ..., a memory matrix 310 consisting of 64 memory elements numbered 63, and 8 row selection lines 420 to 427 and 5 arranged in the row direction of the matrix are selectively selected and driven. 8 column information lines 440 to 447 arranged in the IJ sock column direction;
A column write circuit 340 and a column read circuit 350 selectively select these and perform write and read operations on these, respectively, and address information 365 from the host device is stored, and these are stored as row addresses. The address register 360 outputs to the line 361 and the column AT/L/S line 362, and receives control information 375 from the host device, and the write/read controller 3
A storage control unit 370 sends out an operation pulse 371 to an address register 360, and a storage control unit 370 receives a column address from an address register 360 via a column address line 362 and stores it.
Each time an operation reference 371 is received from 70, this column address is incremented by one, and the result is sent to column address line 38.
2a and 382b, the write/read control section 380 supplies data to the column write circuit 340 and the column read circuit 350, respectively.

In the conventional memory circuit I described above, a read operation for memory elements at four consecutive addresses starting from address 066 and including this address 066 will be described as shown in the time chart shown in FIG. Note that the operation is exactly the same in the case of writing, and can be easily inferred from the case of reading.

First, the row address stored in the address register 360
0# and column address "'6" are applied to row drive circuit 320 and write/read control section 380 via row address line 361 and column address line 362, respectively. The row drive circuit 320 decodes the row address “0#” and selects the row selection line 420.
Drive. The write/read controller 380 stores column address "6".

The storage control unit 370 also receives the operating clock 371 and sets the column address 6” to the column address line 382b.
is applied to column readout circuit 350 via.

Thereafter, each time the operation clock 371 is received at a fixed time interval t, the memory contents are increased by one, and the memory contents "
7# “O” “1” is applied to the column readout circuit 350 via the column address line 382b.The column readout circuit 350 sequentially decodes this column address and outputs the first column information lines 446, 447,
440.44'l are selected in sequence.

Address 6.7, which is the intersection with the already selected row selection line
, 0.1 are read out sequentially to obtain read information 3.
55 and sends it to the higher-level device.

[Problem that the invention seeks to solve]

The conventional memory circuit described above is limited to reading and writing memory element information from the same row selection line when reading and writing data of a specific length from an arbitrary address.
It was not possible to read or write across the memory element information K of the next row selection line.

This has resulted in a major drawback in practical terms.

[Means for solving problems]

The memory circuit of the present invention has M pieces (0, 1) arranged in two rows.
...M-1) row selection line, N (0, 1...N-1) column information lines arranged in the direction of one column, and an M line at the intersection of the row selection line and the column information line. Memory elements arranged in a matrix of rows and N columns (both even numbers) and individually addressed;
an address register that stores a register consisting of a row address and a column address specifying one address of the memory element; an address decoder that decodes the row address and column address, respectively; and the row selection line is selected based on the output of the address decoder. a row drive circuit having a row drive selection circuit that selectively selects write information; a column write circuit having a write selection circuit that selectively provides write information to the column information line; In a storage circuit having a column readout circuit having a readout selection circuit for reading out readout information, the N column information lines are connected to upper column information lines (0 to N/2-1) and lower column information lines (N/2). ~N-1), and divides the row selection line into a first row selection line that intersects the upper column information line and a second row selection line that intersects the lower column information line, and A drive circuit selects and drives the first row selection line, and in the case of a column address that is located between the address decoder and the row drive selection circuit and selects an upper column, the output of the address decoder is directly used to select the row drive selection line. a first row drive circuit having a rotation shift circuit that shifts the output of the address decoder in the case of a column address for selecting a lower column, and supplies the next row address to the row drive selection circuit; It is divided into a second row drive circuit that selects and drives the 2-0 row selection line, and further includes a means for prohibiting further reading or writing when the largest address is selected, and a means for inhibiting other memory circuits. A circuit that includes a signal that enables reading or writing, and a means that can activate the reading or writing operation by a signal from another storage circuit, thereby allowing data to be read or written across rows or stored from the address specified by the address. It is possible to time-divisionally read or write memory elements at a plurality of consecutive addresses across circuits.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In this embodiment, for the sake of simplicity, a case of a matrix of 8 rows by 8 columns will be described.

The memory circuit shown in FIG. 1 is arranged in a matrix of 8 rows and 8 columns in the form of an IJ sock, each with 0. ．． It has a memory matrix 10 consisting of 64 memory elements numbered 1..., 63, and this memory matrix 10 is
Eight column information lines 140 to 1 arranged in the socks column direction
It is connected to 47. Column information lines 140 to 147 selectively select one of the column information lines and write information 4 thereto.
5, and a column read circuit 50 that selectively selects one of the column information lines and reads read information 55 from it. Column write circuit 40 and column read circuit 50 are connected to write/read controller 80 via column address lines 82a and 82b, respectively.

To explain in more detail the eight column information lines 140 to 147, these column information lines consist of four upper column information lines (140 to 143) and four lower column information lines (144 to 147).
) and are selected by the upper column selection address and the lower column selection address, respectively. The first row selection lines 120 to 127 and the lower column selection line 14
Eight second row selection lines 130 to 1 intersecting lines 4 to 147
37. First row selection lines 120-12
7 and the second row selection lines 130 to 137 are one of each.
A first row drive circuit 2 that selectively selects and drives one of the
0 and the second row drive circuit 30. The first row drive circuit 20 and the second row drive circuit 30 are connected to an address register 60 via a row address line 61. This address register is configured to receive and store address information 65 consisting of a row address and a column address from a host device (not shown), and output these to a row address line 61 and a column address line 62, respectively.

The storage control unit 70 receives control information 75 including a write/read control signal and an operation clock from the host device, and controls the one-row drive control unit 24 . Write/read control unit 80. - and row drive circuit 24
It is configured to be able to send control signals, operating clocks, etc. The write/read control section 80 is configured to input an operating clock via a column address line 62 from the address register 60 and a control signal 71 from the storage control section 70, and output it to the first column address lines 82a and 82b. . The row drive control unit 24 has a column address line 62 from the address register 60 and a control signal line 72 from the storage control unit 70.
Input the control signal through.

The first row drive circuit 20 is configured to control the first row drive circuit 20 .

The row drive circuit 20 has an address decoder 21.

It has a row drive selection circuit 22 and a rotation shift circuit 23 located therebetween, which decodes the row address received from the address register 60 via the row address line 61 and selects one of the nine row selection lines 120 to 127. It has a function of selectively selecting and driving.

In this selection, the column address line 6 of the address register 60
Column address on 2 and control signal 72 from storage control unit 70
The rotation shift circuit 23 is turned on and off by the output of the row drive control unit 24, which operates independently.If the 9th column address is an upper column selection address, the rotation shift circuit 23 is turned off and the decoded row is If the row selection line corresponding to the address is selected and the second column address is a lower column selection address, the rotate shift circuit 23 is turned on and selects the row selection line corresponding to the next row address of the decoded row address ( Note that the row following row address 7 returns to row address 0.).

The row drive circuit 30 has an address decoder 31 and a row drive selection circuit 32, and decodes the row address received from the address register 60 via the row address line 61 and selects one of the two row selection lines 130-137. It has a function of selectively selecting and driving.

The column write circuit 40 includes an address decoder 41 and a write selection circuit 42, and decodes the column address received from the write/read control unit 80 via the column address line 82a, and writes the column address to the nine column information lines 140 to 147. one of the selected column information lines and one or more of the row selection lines 120 to 127 selected by the row drive circuit 20 or 30, respectively.
It has a function of writing the write information 45 received from the host device into the memory element at the intersection with one of 30 to 137.

The column read circuit 50 has an address decoder 51 and a read selection circuit 52, and has a column address line 8 from the write/read control section 80.
2, and selectively selects one of the column information lines 140 to 147, and selects the selected column information line and the row drive circuit 20 or 30, respectively. It has a function of reading information from the memory element at the intersection with one of the row selection lines 120 to 127 or one of the row selection lines 130 to 137, and transmitting this read information 55 to the host device.

The write/read control section 80 receives a column address from the address register 60 via the column address line 61 and stores it, and writes the column address every time an operation clock is applied from the storage control section 70 via the control signal line 71. The address is incremented by one (note that after column address 7, it returns to column address O.

) has a function.

The results are supplied to the column write circuit 40 and the column read circuit 50 via the column address lines 82a and 82b, respectively, and the memory elements at consecutive addresses starting from the address specified by the column address of the address information 65 are read. It is configured so that it can be written or read in parts.

Every time 70 executes a write or read operation for a plurality of consecutive addresses, it compares whether the address being executed is the largest address using the adjacent circuit control signal 94, and if it is the largest address, the subsequent The operation control signal 92 prohibiting the operation causes the storage control unit 70 to prohibit subsequent write or read operations, and the adjacent circuit activation output signal 91 is turned on for the maximum address and thereafter. Adjacent circuit activation input signal 9
5 is connected to the adjacent circuit activation output signal of the adjacent storage circuit, and when turned on, the storage control unit 70 is activated by the operation control signal 92.
It has the function of controlling the CPU to execute write or read operations.

FIG. 2 is a time chart showing the operation of one embodiment of the present invention. For one embodiment of the invention in FIG.
A read operation for memory elements at four consecutive addresses including addresses 66 to 066 will be described. Note that the operation for writing is exactly the same, and can be easily inferred from the case for reading.

First, "06" is given to the address register 60 as address information 65 from the host device and is stored.

Row address “0” is the row drive circuit 20 and row drive circuit 30
are input respectively. In the row drive circuit 20, the row drive control section 2
4 inputs the column address "6", decodes that this is the lower column selection address, and turns on the rotate shift circuit 23. As a result, the row drive selection circuit 22 selects the next row address "1". Selects and drives the corresponding row selection line 121.The row drive selection circuit 30 selects and drives the row selection line 121.
selectively drives the row selection line 130.

As one of the control information 75 for the storage control unit 70, the second
When the illustrated operating clock CO is given.

The storage control section 70 causes the write/read control section 80 to start a read operation in response to an operation clock via a control signal 71. The write/read controller 80 sends the column address "6n" given in advance to the column read circuit 50 via the column address line 82b.
and according to the decoding result of the address decoder 51,
The column information line 146 is selected by the read selection circuit 52 and the contents of the memory element "6" are read out as the read information 55.

When the next operation clock CI is applied, the write/read controller 8
For 0, add 1 to the stored column address, ``7'', as the new column address, and repeat the above operation.

The contents of memory element "7" are read. Furthermore, when clock C2 is applied, the above operation is repeated with the first column address "'0", and the contents of address 8, which is the intersection of the second column information line 140 and the row selection line 121 that has already been selected and driven by the row drive circuit 20. is read out. When clock C3 is further applied, the contents of address 9 are read out in the same manner as above.

FIG. 3 is a diagram showing an example of the configuration of a circuit that uses a plurality of memory circuits according to the present invention to read or write information from arbitrary addresses to consecutive addresses across the memory circuits. The first to fourth memory circuits 200 to 203 in FIG. 3 are all the same as the memory circuit explained in FIG. 1. The signals A and D in these memory circuits 200 to 203
J.Do.

AI and AO are address information 65. in FIG. Write information 45. Read information 55. Adjacent circuit activation input signal 95. Each corresponds to the adjacent circuit activation output signal 91. Note that E and C are the control information 75 in FIG. 1, and represent an enable signal and a clock signal, respectively.

In the embodiment shown in FIG. 3, four memory circuits 200 to 203 are combined to form a memory device with addresses O to 255, and the input and output signals of each memory circuit 200 to 203 are interconnected. There is. The address is determined by decoding the address 265 of each memory circuit 200 to 203 and the address of the upper two pits to form the first enable signal 270 of the first memory circuit 200 to the fourth enable signal 273 of the fourth memory circuit 203. By adding the first to fourth memory circuits 200
~203 sequentially O~63.64~127°128~19
1. It is configured to be divided into addresses 192 to 255.

FIG. 4 is an explanatory diagram for reading out address information continuously across circuits in the embodiment of FIG. 3. In the operation clock CO of FIG. 4, the address of address "62" is given, and address ``62'' of the first memory circuit 200 of FIG. 3 is read out. Similarly, in the operation clock CI, the first memory circuit 200
The address "63" is read out. Since the operating clock C2 exceeds the maximum address of the first memory circuit 200, the adjacent circuit activation output signal 91 in FIG. 1 is turned on.

This turns on the adjacent circuit activation input signal (AI) of the second storage circuit 201 in FIG. 3, thereby starting the read operation of the second storage circuit 201. In the storage circuit 200 of temperature removal 1, the read operation is prohibited, and in the second storage circuit 201, the address "64#" is selected and the information at the address "64" is read. Similarly, at the operation clock C3, address "65" of the second memory circuit 201 is selected, and information at address "65" is read out.

In the above embodiment, the case where both the number of rows and the number of columns are 8 has been explained, but the invention is not limited to this, and it is sufficient if both numbers are even numbers, and if the total number of 2 column information lines is N, then ,
Connect the first column information line to 0, 1 . ....

(N-1)/2, a total of N/2, and the second column information line is N
/2, (N+1)/2, ..., N-1 total N
/2 pieces.

〔Effect of the invention〕

As explained above, the present invention divides two row selection lines into two, includes a rotation shift circuit in the row drive circuit that drives one of them, detects the maximum address, prohibits subsequent operations, and activates the adjacent circuit. By adding this function, the memory elements at consecutive addresses can be read and written from a specified address to the next row, even between multiple memory circuits. This has the advantage of being able to provide a memory circuit that makes it possible to continuously obtain length data with one command.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. Fig. 2 is a diagram showing a time chart in an embodiment of the present invention, Fig. 3 is a block diagram showing an embodiment of the invention using a plurality of memory circuits, and Fig. 4 is a diagram showing an embodiment of the invention using a plurality of memory circuits. FIG. 5 is a block diagram showing a conventional memory circuit, and FIG. 6 is a diagram showing a time chart in the conventional memory circuit. Explanation of symbols: 10...Memory matrix, 20°3
0... Row drive circuit, 21.31... Address decoder, 22.32... Row drive selection circuit, 23... Rotate shift circuit, 24... Row drive control unit, 40...
・Column write circuit, 50... Column read circuit, 41.51...
・Address decoder, 42...Write selection circuit, 45.
. . . Write information, 52 . . . Read selection circuit, 55 . . . Read information. 60... Address register, 61... Row address line. 62... Column address line, 70... Storage control unit, 71
゜72... Control signal line, 75... Control information, 80...
. . . Write/read control unit, 82a, 82b . . . Column address lines. 120-127.130-137... Row selection line. 140-147...Column information lines. Figure 2 Row Address 261 =Kari] Mutual '==2nd Column Address 6
2 KoC=[=====Figure 6

Claims (1)

[Claims] 1, M pieces arranged in the row direction (0, 1, ..., M-1
) row selection lines and N selection lines (0, 1, . . . ) arranged in the column direction.
. . , N-1) column information lines, memory elements arranged in a matrix of M rows and N columns (all even numbers) at the intersections of the row selection line and the column information line, respectively addressed. an address register that stores an address consisting of a row address and a column address specifying one address of a memory element, an address decoder that decodes the row address and column address, respectively, and the row selection line is selected based on the output of the address decoder. a row drive circuit having a row drive selection circuit that selectively selects write information; a column write circuit having a write selection circuit that selectively supplies write information to the column information line; In a memory circuit having a column readout circuit having a readout selection circuit for reading readout information, the N column information lines are connected to an upper column information line (0-N/2-1) and a lower column information line (N/2-1).
2 to N-1), and divides the row selection line into a first row selection line that intersects with the upper column information line and a second row selection line that intersects with the lower column information line; The row drive circuit selects and drives the first row selection line, and in the case of a column address that is located between the address decoder and the row drive selection circuit and selects an upper column, the output of the address decoder is directly used to drive the row. a first row drive circuit having a rotation shift circuit which is applied to a selection circuit and, in the case of a column address for selecting a lower column, shifts the output of the address decoder and provides the next row address to the row drive selection circuit; Said second
and a second row drive circuit that selects and drives the row selection line, and further includes a means for prohibiting further reading or writing when the largest address is selected, and a second row driving circuit that selects and drives the row selection line of the memory circuit. A signal that enables writing and a means that can start a read or write operation by a signal from another memory circuit, and a plurality of consecutive memory cells extending across rows or across memory circuits from the address specified by the address. 1. A memory circuit characterized in that memory elements at different addresses can be read or written in a time-division manner.