JPS63142787U - - Google Patents

Info

Publication number
JPS63142787U
JPS63142787U JP3538587U JP3538587U JPS63142787U JP S63142787 U JPS63142787 U JP S63142787U JP 3538587 U JP3538587 U JP 3538587U JP 3538587 U JP3538587 U JP 3538587U JP S63142787 U JPS63142787 U JP S63142787U
Authority
JP
Japan
Prior art keywords
circuit
signal
pulse train
outputs
switching gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3538587U
Other languages
Japanese (ja)
Other versions
JPH0441349Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3538587U priority Critical patent/JPH0441349Y2/ja
Publication of JPS63142787U publication Critical patent/JPS63142787U/ja
Application granted granted Critical
Publication of JPH0441349Y2 publication Critical patent/JPH0441349Y2/ja
Expired legal-status Critical Current

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  • Electric Clocks (AREA)
  • Electromechanical Clocks (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の実施例に係る時計の回路図
。第2図は、第1図のタイムチヤート。 2……発振器、4……分周回路、6……初期リ
セツト回路、12……初期早送り回路、14……
修正スイツチ、22……第2の切り換えゲート回
路、30……第1の切り換えゲート回路、40…
…駆動回路、42……モータ、44……輪列、4
6……指針、48……カウンタ回路。
FIG. 1 is a circuit diagram of a timepiece according to an embodiment of the present invention. Figure 2 is the time chart of Figure 1. 2... Oscillator, 4... Frequency dividing circuit, 6... Initial reset circuit, 12... Initial fast forward circuit, 14...
Correction switch, 22... Second switching gate circuit, 30... First switching gate circuit, 40...
... Drive circuit, 42 ... Motor, 44 ... Wheel train, 4
6...Pointer, 48...Counter circuit.

Claims (1)

【実用新案登録請求の範囲】 発振器と、この発振器からの信号を分周して周
期の異なる複数種のパルス列信号を出力する分周
回路と、修正スイツチと、この修正スイツチの非
操作時には前記分周回路から出力されるパルス列
信号のうち1分周期の第1のパルス列信号を出力
するとともに操作時は前記第1のパルス列より短
い周期の第2のパルス列信号を出力する第1の切
換ゲート回路と、この第1の切換ゲート回路から
出力される第2のパルス列信号をカウントすると
ともにそのカウント値が「60」になつた時から
検出信号を出力するカウンタ回路と、このカウン
タ回路からの検出信号発生時には前記第1の切換
ゲート回路から前記第2のパルス列信号に代えて
より周期の短い第3のパルス列信号を出力させる
切換信号を出力する第2の切換ゲート回路と、モ
ータと、前記第1の切換ゲート回路から出力され
るパルス列信号を前記モータを駆動させる信号に
変換する駆動回路と、前記モータによつて回転駆
動される輪列と、輪列によつて駆動される時刻の
時分を表示する指針と、電源投入を検出して前記
分周回路を一時リセツトするパルスを出力する初
期リセツト回路と、を有する時計において、 前記初期リセツト回路からパルスが発生した後
の前記修正スイツチの最初の操作時には前記第1
の切換ゲート回路に切換信号を強制的に供給する
ように前記第2の切換ゲート回路を制御する制御
信号を出力する初期早送り回路を設けたことを特
徴とする時計の修正装置。
[Claims for Utility Model Registration] An oscillator, a frequency dividing circuit that divides the signal from the oscillator and outputs a plurality of types of pulse train signals with different periods, a correction switch, and when the correction switch is not operated, a first switching gate circuit that outputs a first pulse train signal with a period of one minute among the pulse train signals output from the circuit, and outputs a second pulse train signal with a shorter period than the first pulse train during operation; , a counter circuit that counts the second pulse train signal output from the first switching gate circuit and outputs a detection signal from when the count value reaches "60", and a detection signal generation from this counter circuit. a second switching gate circuit that outputs a switching signal that sometimes causes the first switching gate circuit to output a third pulse train signal having a shorter period instead of the second pulse train signal; a motor; A drive circuit that converts a pulse train signal output from a switching gate circuit into a signal for driving the motor, a wheel train that is rotationally driven by the motor, and displays the hours and minutes of the time when the wheel train is driven. and an initial reset circuit that detects power-on and outputs a pulse that temporarily resets the frequency dividing circuit, the first operation of the correction switch after the pulse is generated from the initial reset circuit. Sometimes the first
A timepiece correcting device comprising: an initial fast-forwarding circuit that outputs a control signal for controlling the second switching gate circuit so as to forcibly supply the switching signal to the second switching gate circuit.
JP3538587U 1987-03-11 1987-03-11 Expired JPH0441349Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3538587U JPH0441349Y2 (en) 1987-03-11 1987-03-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3538587U JPH0441349Y2 (en) 1987-03-11 1987-03-11

Publications (2)

Publication Number Publication Date
JPS63142787U true JPS63142787U (en) 1988-09-20
JPH0441349Y2 JPH0441349Y2 (en) 1992-09-29

Family

ID=30844826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3538587U Expired JPH0441349Y2 (en) 1987-03-11 1987-03-11

Country Status (1)

Country Link
JP (1) JPH0441349Y2 (en)

Also Published As

Publication number Publication date
JPH0441349Y2 (en) 1992-09-29

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