JPH0441349Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a correction device for a watch that displays hours and minutes using hands.

(Prior art) Conventionally, as shown in Utility Model Application Publication No. 55-106890, for example, when a correction switch is pressed, a rather slow fast-forward correction of the time is made, and if the press lasts for a certain period of time or more, a faster correction is made. It is done. This was very convenient for hand-type analog display watches, especially watches that could only adjust the time quickly in a certain direction, as it allowed for long-term time adjustments to be made in a short amount of time.

(Problem to be solved by the invention) However, as clocks have become more accurate since the adoption of the crystal oscillation method, long-term corrections are most often made when replacing the power supply battery. In this case, a high-speed correction is usually required, so the conventional method in which a high-speed correction cannot be made unless the switch is pressed for a certain period of time has many inconveniences.

(Means for solving the problem) The present invention forcibly performs high-speed correction when operating the correction switch for the first time after turning on the power, and for subsequent operations of the correction switch, is a slow correction, and when the operation continues for a certain period of time, a high speed correction is made.

(Example) FIG. 1 is a circuit diagram according to an embodiment of the present invention.

The reference signal from the oscillator 2 is frequency-divided by the frequency dividing circuit 4, and outputs a first pulse train signal φ ₁ , a second pulse train signal φ ₂ and a third pulse train signal φ ₃ .
Here, the period has a relationship of φ ₁ > φ ₂ > φ ₃ ,
The period of the first pulse train signal φ ₁ is 1 minute.

Reference numeral 6 denotes an initial reset circuit consisting of a capacitor 8 and a resistor 10, which supplies a pulse signal R to the frequency dividing circuit 4 and a counter circuit to be described later at the same time as the power is turned on.

12 is an initial fast-forwarding circuit according to the present invention;
A flip-flop (hereinafter referred to as FF) 18 to which the operation signal A from the correction switch 14 is inputted to the clock input φ via the inverter 16;
and an ANDQUETE 20 into which the operation signal A from the correction switch 14 is input. The output signal of this AND gate 20 is output as a control signal B.

22 is a second switching gate circuit, which is an OR gate 2 into which a detection signal from a counter circuit (to be described later) and a control signal B from the initial fast-forwarding circuit 12 are input.
4, an AND gate 26 to which the output signal from the OR gate 24 and the third pulse train signal φ ₃ from the frequency dividing circuit 4 are input, an inverted signal from the OR gate 24, and an operation signal A from the correction switch 14. and the input AND gate 28.

30 is a first switching gate circuit, which includes an AND gate 32 to which the inverted output signals of the OR gate 24 and AND gate 28 are input, and an AND gate 34 to which the signal from this AND gate 32 and the first pulse train signal φ ₁ are input. , an AND gate 36 into which the output signal from the AND gate 28 and the second pulse train signal φ ₂ are input, and AND gates 26, 3
and an OR gate 38 into which numbers 4 and 36 are input.

Pulse train signal C output from OR gate 38
is amplified via the drive circuit 40 and supplied to the motor 42. This motor 42 is rotated in response to a pulse train signal and drives a wheel train 44. By driving this wheel train 44, the hands 46 display hours and minutes.

48 is a counter circuit, the output signal of the AND gate 36 via the AND gate 50 is input to the clock input φ, and the pulse signal R from the initial reset circuit 6 and the operation signal A via the inverter 52 are input to the reset input R. An input OR gate 54 has an input sexagesimal counter 56. sexagesimal counter 5
The Q output of 6 is input to the OR gate 24 as a detection signal D, and is also inverted and input to the AND gate 50.

This will be explained below using the time chart shown in FIG.

First, when the power is turned on, a pulse signal R is output from the initial reset circuit 6, and the frequency dividing circuit 4 is temporarily reset. At the same time, it is also input to the reset input R of the FF 18, and its output is set to H level. In this state, operation signal A, control signal B
The detection signal D is at the L level, and the output signal of the OR gate 24 is at the L level. Therefore, the output signals of AND gates 26 and 28 become L level, and the output signal of AND gate 32 becomes H level. As a result, the AND gate 34 opens, and the first pulse train signal φ ₁ with a period of 1 minute is transmitted to the OR gate 38.
The signal is supplied to the drive circuit 40 via. Along with this, the motor 42 is driven at a one-minute cycle.

When the correction switch 14 is turned on and the operation signal A becomes H level, the output signal of the inverter 52 becomes L level, thereby canceling the reset of the sexagesimal counter 56. Also, operation signal A
becomes H level, AND gate 20
The control signal B from becomes H level. Therefore, the output signal of the OR gate 24 becomes H level, and as a result, the output signal of the AND gate 32 becomes L level, the AND gate 34 is closed, and the AND gate 2
6 is open, and the third pulse train signal φ ₃ having the shortest period is supplied to the drive circuit 40 via the AND gate 34 and the OR gate 38 . As a result, motor 4
2 rotates at high speed and fast forward correction is performed. When the operation signal A of the correction switch 14 is stopped and the operation signal A falls to the L level, the output signal of the inverter 16 reversely rises, and as a result, the output signal of the FF 18 becomes the L level and the control signal B returns to the L level. . Therefore, the AND gate 26 is closed, the AND gate 34 is opened, and the drive circuit 40 is again supplied with the first signal.
A pulse train signal φ ₁ is supplied.

After that, when the correction switch 14 is turned on and the operation signal is set to the H level, the control signal B is set to the L level.
level, the output signal of the AND gate 28 is H.
level. As a result, the output signal of the AND gate 32 becomes L level, the AND gate 36 is opened, and the AND gate 34 is closed. As a result, the second pulse train signal φ ₂ is supplied to the drive circuit 40 via the OR gate 38 . As a result, the motor 42 rotates at a faster cycle than usual, and the pointer 46 is adjusted to a low speed. At the same time, the second pulse train signal φ ₂ is input to the sexagesimal counter 56 via the AND gate 50 which is open at this time.

If you stop operating the correction switch 14 in this state, the AND gate 36 will close, the AND gate 34 will open, and the motor 42 will drive at a one-minute cycle. When the low speed correction is performed, that is, when the count value of the sexagesimal counter 56 reaches "60", the detection signal D becomes H level, and thereby the output signal of the OR gate 24 becomes H level. As a result, as before, the AND gate 28 is closed, the AND gate 26 is opened, and the third pulse train signal φ ₃ is supplied to the drive circuit 40 via the OR gate 38.
For this reason, the motor 42 rotates at a higher speed, and the indicated time is rapidly forwarded and corrected.

After this, if you stop operating the correction switch 14,
Operation signal A becomes L level, the output signal of inverter 52 becomes H level, sexagesimal counter 56 is reset, and detection signal D returns to L level. Therefore, the output signal of the OR gate 24 becomes L level, the AND gate 26 is closed, and the AND gate 3
4 is opened, and the first pulse train signal is supplied to the drive circuit 40 instead of the third pulse train signal. As a result, the pointer 46 returns to its normal operating state.

(Effect of the invention) According to the invention, normally, when the correction switch is operated for a short time, the correction is made at a low speed, and when the time is adjusted for more than one hour, the correction is made at a high speed. In the first correction operation after turning on the power battery, which often requires corrections that take a long time, the time required for the correction is short because the correction is performed at high speed from the beginning.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a timepiece according to an embodiment of the present invention. Figure 2 is the time chart of Figure 1. 2... Oscillator, 4... Frequency dividing circuit, 6... Initial reset circuit, 12... Initial fast forward circuit, 14...
Correction switch, 22... Second switching gate circuit, 30... First switching gate circuit, 40...
... Drive circuit, 42 ... Motor, 44 ... Wheel train, 4
6...Pointer, 48...Counter circuit.

Claims (1)

[Claims for Utility Model Registration] An oscillator, a frequency dividing circuit that divides the signal from the oscillator and outputs a plurality of types of pulse train signals with different periods, a correction switch, and when the correction switch is not operated, a first switching gate circuit that outputs a first pulse train signal with a period of one minute among the pulse train signals output from the circuit, and outputs a second pulse train signal with a shorter period than the first pulse train during operation; , a counter circuit that counts the second pulse train signal output from the first switching gate circuit and outputs a detection signal from when the count value reaches "60"; and a detection signal generation from this counter circuit. a second switching gate circuit that outputs a switching signal that sometimes causes the first switching gate circuit to output a third pulse train signal having a shorter period instead of the second pulse train signal; a motor; A drive circuit that converts a pulse train signal output from a switching gate circuit into a signal for driving the motor, a wheel train that is rotationally driven by the motor, and displays the hours and minutes of the time when the wheel train is driven. and an initial reset circuit that detects power-on and outputs a pulse that temporarily resets the frequency dividing circuit, the first operation of the correction switch after the pulse is generated from the initial reset circuit. Sometimes the first
A timepiece correcting device comprising: an initial fast-forwarding circuit that outputs a control signal for controlling the second switching gate circuit so as to forcibly supply the switching signal to the second switching gate circuit.